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make testbench successfully deactivate TimerIntM so as to create a nice pulse

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This commit is contained in:
bbracker 2021-09-07 15:36:47 -04:00
parent 28fed18421
commit b3f00f2682
1 changed files with 61 additions and 67 deletions
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20
wally-pipelined/testbench/testbench-linux.sv
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@ -126,6 +126,7 @@ module testbench();
string ExpectedCSRArrayW[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
logic [`XLEN-1:0] ExpectedIntType;
logic forcedInterrupt;
integer NumCSRMIndex;
integer NumCSRWIndex;
integer NumCSRPostWIndex;
@ -246,19 +247,17 @@ module testbench();
//what type?
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
forcedInterrupt = 1;
if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b1;
$display("Force SwIntM");
end
else if(ExpectedIntType == 4) begin
end else if(ExpectedIntType == 4) begin
force dut.hart.priv.TimerIntM = 1'b1;
$display("Force TimeIntM");
end
else if(ExpectedIntType == 8) begin
end else if(ExpectedIntType == 8) begin
force dut.hart.priv.ExtIntM = 1'b1;
$display("Force ExtIntM");
end
end else forcedInterrupt = 0;
end
NumCSRM++;
end
@ -338,12 +337,8 @@ module testbench();
end
// force interrupts to 0
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
//what type?
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
if (forcedInterrupt) begin
forcedInterrupt = 0;
if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b0;
$display("Force SwIntM");
@ -360,7 +355,6 @@ module testbench();
end
end
end
end
// step2: make all checks in the write back stage.
always @(negedge clk) begin