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some FPU test fixes

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This commit is contained in:
Katherine Parry 2022-01-06 23:03:20 +00:00
parent e1db967417
commit b3ebce0365
6 changed files with 10 additions and 14 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

2
pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv64gc arch64d" vsim -do "do wally-pipelined.do rv32gc arch32f"

2
pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-pipelined-batch.do rv64gc arch64d do wally-pipelined-batch.do rv32gc arch32f
! !

10
pipelined/src/fpu/fma.sv
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@ -557,7 +557,6 @@ module normalize(
output logic [`NE+1:0] SumExp, // exponent of the normalized sum output logic [`NE+1:0] SumExp, // exponent of the normalized sum
output logic ResultDenorm // is the result denormalized output logic ResultDenorm // is the result denormalized
); );
logic [`NE+1:0] FracLen; // length of the fraction
logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later
logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction
@ -574,9 +573,6 @@ module normalize(
// Determine if the sum is zero // Determine if the sum is zero
assign SumZero = ~(|SumM); assign SumZero = ~(|SumM);
// determine the length of the fraction based on precision
assign FracLen = FmtM ? `NF+1 : 13'd24;
// calculate the sum's exponent // calculate the sum's exponent
assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
@ -752,6 +748,7 @@ module fmaflags(
output logic [4:0] FMAFlgM // FMA flags output logic [4:0] FMAFlgM // FMA flags
); );
logic SigNaN; // is an input a signaling NaN logic SigNaN; // is an input a signaling NaN
logic GtMaxExp; // is exponent greater than the maximum
logic UnderflowFlag, Inexact; // flags logic UnderflowFlag, Inexact; // flags
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -770,9 +767,8 @@ module fmaflags(
// Set Overflow flag if the number is too big to be represented // Set Overflow flag if the number is too big to be represented
// - Don't set the overflow flag if an overflowed result isn't outputed // - Don't set the overflow flag if an overflowed result isn't outputed
logic LtMaxExp; assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8];
assign LtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8]; assign Overflow = GtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
assign Overflow = LtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
// Set Underflow flag if the number is too small to be represented in normal numbers // Set Underflow flag if the number is too small to be represented in normal numbers
// - Don't set the underflow flag if the result is exact // - Don't set the underflow flag if the result is exact

6
pipelined/testbench/tests.vh
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@ -1283,7 +1283,7 @@ string imperas32f[] = '{
"rv32i_m/F/feq_b1-01", "6220", "rv32i_m/F/feq_b1-01", "6220",
"rv32i_m/F/feq_b19-01", "a190", "rv32i_m/F/feq_b19-01", "a190",
"rv32i_m/F/fle_b1-01", "6220", "rv32i_m/F/fle_b1-01", "6220",
"rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity? "rv32i_m/F/fle_b19-01", "a190",
"rv32i_m/F/flt_b1-01", "6220", "rv32i_m/F/flt_b1-01", "6220",
"rv32i_m/F/flt_b19-01", "8ee0", "rv32i_m/F/flt_b19-01", "8ee0",
"rv32i_m/F/flw-align-01", "2010", "rv32i_m/F/flw-align-01", "2010",
@ -1298,7 +1298,7 @@ string imperas32f[] = '{
"rv32i_m/F/fmadd_b4-01", "3700", "rv32i_m/F/fmadd_b4-01", "3700",
"rv32i_m/F/fmadd_b5-01", "3ac0", "rv32i_m/F/fmadd_b5-01", "3ac0",
"rv32i_m/F/fmadd_b6-01", "3700", "rv32i_m/F/fmadd_b6-01", "3700",
//"rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test; didn't run even with fixed memfile "rv32i_m/F/fmadd_b7-01", "37f0",
"rv32i_m/F/fmadd_b8-01", "13f30", "rv32i_m/F/fmadd_b8-01", "13f30",
"rv32i_m/F/fmax_b1-01", "7220", "rv32i_m/F/fmax_b1-01", "7220",
"rv32i_m/F/fmax_b19-01", "9e00", "rv32i_m/F/fmax_b19-01", "9e00",
@ -1355,7 +1355,7 @@ string imperas32f[] = '{
"rv32i_m/F/fnmsub_b17-01", "39d0", "rv32i_m/F/fnmsub_b17-01", "39d0",
"rv32i_m/F/fnmsub_b18-01", "4d10", "rv32i_m/F/fnmsub_b18-01", "4d10",
"rv32i_m/F/fnmsub_b2-01", "4d60", "rv32i_m/F/fnmsub_b2-01", "4d60",
//"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile "rv32i_m/F/fnmsub_b3-01", "d4f0",
"rv32i_m/F/fnmsub_b4-01", "3700", "rv32i_m/F/fnmsub_b4-01", "3700",
"rv32i_m/F/fnmsub_b5-01", "3ac0", "rv32i_m/F/fnmsub_b5-01", "3ac0",
"rv32i_m/F/fnmsub_b6-01", "3700", "rv32i_m/F/fnmsub_b6-01", "3700",