From b3849d8abbb9e1bd4fcc7af59dcd13b0f9fbf83f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Aug 2021 10:58:19 -0500 Subject: [PATCH] Moved data path logic from icacheCntrl to icache. --- wally-pipelined/src/cache/ICacheCntrl.sv | 34 +++---------------- wally-pipelined/src/cache/icache.sv | 26 ++++++++++++-- .../testbench/testbench-imperas.sv | 2 +- wally-pipelined/testbench/testbench-linux.sv | 2 +- 4 files changed, 30 insertions(+), 34 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index db5592a05..ea3257aa8 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -48,12 +48,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) output logic ICacheMemWriteEnable, output logic [BLOCKLEN-1:0] ICacheMemWriteData, - // Outputs to rest of ifu - // High if the instruction in the fetch stage is compressed - output logic CompressedF, // The instruction that was requested // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros - output logic [31:0] FinalInstrRawF, // Outputs to pipeline control stuff output logic ICacheStallF, EndFetchState, @@ -67,7 +63,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) input logic InstrAckF, // The read we request from main memory output logic [`PA_BITS-1:0] InstrPAdrF, - output logic InstrReadF + output logic InstrReadF, + + output logic spill, + output logic spillSave ); // FSM states @@ -130,12 +129,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) statetype CurrState, NextState; - logic hit, spill; + logic hit; logic SavePC; logic [1:0] PCMux; logic CntReset; logic PreCntEn, CntEn; - logic spillSave; logic UnalignedSelect; logic FetchCountFlag; localparam FetchCountThreshold = WORDSPERLINE - 1; @@ -146,7 +144,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; - logic [15:0] SpillDataBlock0; localparam [31:0] NOP = 32'h13; @@ -181,9 +178,6 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) // truncate the offset from PCPF for memory address generation assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; - // Detect if the instruction is compressed - assign CompressedF = FinalInstrRawF[1:0] != 2'b11; - // the FSM is always runing, do not stall. always_ff @(posedge clk, posedge reset) @@ -436,23 +430,5 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) // what address is used to write the SRAM? - // spills require storing the first cache block so it can merged - // with the second - // can optimize size, for now just make it the size of the data - // leaving the cache memory. - flopenr #(16) SpillInstrReg(.clk(clk), - .en(spillSave), - .reset(reset), - .d(ICacheMemReadData[15:0]), - .q(SpillDataBlock0)); - - // use the not quite final PC to do the final selection. - logic [1:1] PCPreFinalF_q; - flopenr #(1) PCFReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(PCPreFinalF[1]), - .q(PCPreFinalF_q[1])); - assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData; endmodule diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 954828fd5..1d034f711 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -68,6 +68,11 @@ module icache logic ICacheReadEn; logic [BLOCKLEN-1:0] ReadLineF; + + logic [15:0] SpillDataBlock0; + logic spill; + logic spillSave; + ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES)) cachemem(.clk, @@ -104,6 +109,21 @@ module icache endcase end + // spills require storing the first cache block so it can merged + // with the second + // can optimize size, for now just make it the size of the data + // leaving the cache memory. + flopenr #(16) SpillInstrReg(.clk(clk), + .en(spillSave), + .reset(reset), + .d(ICacheMemReadData[15:0]), + .q(SpillDataBlock0)); + + assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData; + + // Detect if the instruction is compressed + assign CompressedF = FinalInstrRawF[1:0] != 2'b11; + ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.clk, @@ -120,8 +140,6 @@ module icache .ICacheReadEn, .ICacheMemWriteEnable, .ICacheMemWriteData, - .CompressedF, - .FinalInstrRawF, .ICacheStallF, . EndFetchState, .ITLBMissF, @@ -130,7 +148,9 @@ module icache .InstrInF, .InstrAckF, .InstrPAdrF, - .InstrReadF); + .InstrReadF, + .spill, + .spillSave); // For now, assume no writes to executable memory assign FlushMem = 1'b0; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 8cc37aff3..38436752e 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -577,7 +577,7 @@ string tests32f[] = '{ // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.icache.controller.FinalInstrRawF, + dut.hart.ifu.icache.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 44446098d..aa7de3801 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -619,7 +619,7 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.icache.controller.FinalInstrRawF, + dut.hart.ifu.icache.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);