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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
added comments for RAM and bootram, removed trailing whitepace
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@ -164,6 +164,17 @@ module testbench_busybear();
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end
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endgenerate
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// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
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// including subwords. Brief explanation on signals:
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//
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// readMask: bitmask of bits to read / write, left-shifted to align with
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// nearest 64-bit boundary - examples
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// HSIZE = 0 -> readMask = 11111111
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// HSIZE = 1 -> readMask = 1111111111111111
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//
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// In the linux boot, the processor spends the first ~5 instructions in
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// bootram, before jr jumps to main RAM
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logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
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logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
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logic [`XLEN-1:0] readRAM, readPC;
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@ -175,7 +186,7 @@ module testbench_busybear();
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always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
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if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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if (HWRITE) begin
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RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask);
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RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size
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end else begin
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readRAM = RAM[RAMAdr] & readMask;
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end
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