Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

added comments for RAM and bootram, removed trailing whitepace

Browse Source
This commit is contained in:
kaveh pezeshki 2021-02-23 21:28:33 -08:00
parent c8e9edcc43
commit b36a5614b4
1 changed files with 30 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -164,6 +164,17 @@ module testbench_busybear();
end end
endgenerate endgenerate
// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
// including subwords. Brief explanation on signals:
//
// readMask: bitmask of bits to read / write, left-shifted to align with
// nearest 64-bit boundary - examples
// HSIZE = 0 -> readMask = 11111111
// HSIZE = 1 -> readMask = 1111111111111111
//
// In the linux boot, the processor spends the first ~5 instructions in
// bootram, before jr jumps to main RAM
logic [`XLEN-1:0] RAM[('h8000000 >> 3):0]; logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
logic [`XLEN-1:0] bootram[('h2000 >> 3):0]; logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
logic [`XLEN-1:0] readRAM, readPC; logic [`XLEN-1:0] readRAM, readPC;
@ -175,7 +186,7 @@ module testbench_busybear();
always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
if (HWRITE) begin if (HWRITE) begin
RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size
end else begin end else begin
readRAM = RAM[RAMAdr] & readMask; readRAM = RAM[RAMAdr] & readMask;
end end