mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
Removed unused Makefiles and Makefrags from wally-riscv-arch-test now that it is only used by riscof
This commit is contained in:
David Harris
parent
d094201362
commit
b362320dd9
@ -1,123 +0,0 @@
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#
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# Ensure the compiler and necessary executables are on the search PATH
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#
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#
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# Ensure you have set the following Variables
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#
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#
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export ROOTDIR = $(shell pwd)
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export WORK ?= $(ROOTDIR)/work
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include Makefile.include
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pipe:= |
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empty:=
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comma:= ,
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space:= $(empty) $(empty)
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RISCV_ISA_ALL = $(shell ls $(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m)
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RISCV_ISA_OPT = $(subst $(space),$(pipe),$(RISCV_ISA_ALL))
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RISCV_ISA_ALL := $(filter-out Makefile.include,$(RISCV_ISA_ALL))
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ifeq ($(RISCV_DEVICE),)
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RISCV_DEVICE = I
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DEFAULT_TARGET=all_variant
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else
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DEFAULT_TARGET=variant
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endif
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export SUITEDIR = $(ROOTDIR)/riscv-test-suite/rv$(XLEN)i_m/$(RISCV_DEVICE)
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$(info )
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$(info ============================ VARIABLE INFO ==================================)
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$(info ROOTDIR: ${ROOTDIR} [origin: $(origin ROOTDIR)])
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$(info WORK: ${WORK} [origin: $(origin WORK)])
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$(info TARGETDIR: ${TARGETDIR} [origin: $(origin TARGETDIR)])
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$(info RISCV_TARGET: ${RISCV_TARGET} [origin: $(origin RISCV_TARGET)])
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$(info XLEN: ${XLEN} [origin: $(origin XLEN)])
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$(info RISCV_DEVICE: ${RISCV_DEVICE} [origin: $(origin RISCV_DEVICE)])
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$(info =============================================================================)
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$(info )
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RVTEST_DEFINES =
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ifeq ($(RISCV_ASSERT),1)
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RVTEST_DEFINES += -DRVMODEL_ASSERT
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endif
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export RVTEST_DEFINES
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VERBOSE ?= 0
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ifeq ($(VERBOSE),1)
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export V=
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export REDIR1 =
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export REDIR2 =
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else
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export V=@
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export REDIR1 = 1>/dev/null
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export REDIR2 = 2>/dev/null
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endif
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default: $(DEFAULT_TARGET)
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variant: compile simulate verify
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all_variant:
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@for isa in $(RISCV_ISA_ALL); do \
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$(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa variant; \
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rc=$$?; \
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if [ $$rc -ne 0 ]; then \
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exit $$rc; \
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fi \
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done
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build: compile
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run: simulate
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clean_all: clean
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compile:
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$(MAKE) $(JOBS) \
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RISCV_TARGET=$(RISCV_TARGET) \
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RISCV_DEVICE=$(RISCV_DEVICE) \
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compile -C $(SUITEDIR)
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simulate:
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$(MAKE) $(JOBS) \
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RISCV_TARGET=$(RISCV_TARGET) \
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RISCV_DEVICE=$(RISCV_DEVICE) \
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run -C $(SUITEDIR)
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verify: simulate
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riscv-test-env/verify.sh
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postverify:
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ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
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$(info No post verify script found $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh)
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else
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$(TARGETDIR)/$(RISCV_TARGET)/postverify.sh
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endif
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clean:
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$(MAKE) $(JOBS) \
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RISCV_TARGET=$(RISCV_TARGET) \
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RISCV_DEVICE=$(RISCV_DEVICE) \
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clean -C $(SUITEDIR)
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help:
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@echo "RISC-V Architectural Tests"
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@echo ""
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@echo " Makefile Environment Variables to be set per Target"
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@echo " -- TARGETDIR='<directory containing the target folder>'"
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@echo " -- XLEN='<make supported xlen>'"
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@echo " -- RISCV_TARGET='<name of target>'"
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@echo " -- RISCV_TARGET_FLAGS='<any flags to be passed to target>'"
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@echo " -- RISCV_DEVICE='$(RISCV_ISA_OPT)' [ leave empty to run all devices ]"
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@echo " -- RISCV_TEST='<name of the test. eg. I-ADD-01'"
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@echo " "
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@echo " Makefile targets available"
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@echo " -- build: To compile all the tests within the RISCV_DEVICE suite and generate the elfs. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
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@echo " -- run: To run compiled tests on the target model and generate signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
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@echo " -- verify: To verify if the generated signatures match the corresponding reference signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
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@echo " -- postverify: To run post verification processing for a target, for example with this, riscvOVPsim runs instructional functional coverage on the tests"
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@echo " -- clean : removes the working directory from the root folder and also from the respective device folders of the target"
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@echo " -- default: build, run, and verify on all devices enabled"
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@ -1,27 +0,0 @@
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# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
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export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target
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export RISCV_PREFIX = riscv64-unknown-elf-
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# set XLEN to max supported XLEN. Allowed values are 32 and 64
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export XLEN ?= 64
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# name of the target. Note a folder of the same name must exist in the TARGETDIR directory
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export RISCV_TARGET ?= spike
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# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify.
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# Leave this blank if you want to iterate through all the supported extensions available in the target
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export RISCV_DEVICE ?=
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# set this to a string which needs to be passed to your target Makefile.include files
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export RISCV_TARGET_FLAGS ?=
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# set this if you want to enable assertions on the test-suites. Currently no tests support
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# assertions.
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export RISCV_ASSERT ?= 0
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# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure
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# that no common files across jobs are created/overwritten leading to unknown behavior
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JOBS= -j1
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@ -1,77 +0,0 @@
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#=======================================================================
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# Makefile for riscv-tests/isa
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#-----------------------------------------------------------------------
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act_dir := .
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src_dir := $(act_dir)/src
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ref_dir := $(act_dir)/references
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work_dir := $(WORK)
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work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE)
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include $(act_dir)/Makefrag
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ifneq ($(RISCV_TEST),)
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target_tests = $(RISCV_TEST).elf
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target_tests_nosim = $(empty)
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endif
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default: all
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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vpath %.S $(act_dir)
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INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m/$(RISCV_DEVICE)/Makefile.include
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ifeq ($(wildcard $(INCLUDE)),)
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$(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
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endif
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-include $(INCLUDE)
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#------------------------------------------------------------
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# Build and run assembly tests
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%.log: %.elf
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$(V) echo "Execute $(@)"
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$(V) $(RUN_TARGET)
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define compile_template
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$(work_dir_isa)/%.elf: $(src_dir)/%.S
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$(V) echo "Compile $$(@)"
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@mkdir -p $$(@D)
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$(V) $(COMPILE_TARGET)
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.PRECIOUS: $(work_dir_isa)/%.elf
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endef
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target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
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target_elf_nosim = $(foreach e,$(addsuffix .elf, $(target_tests_nosim)),$(work_dir_isa)/$(e))
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combined_elf = $(target_elf_nosim) $(target_elf)
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target_log = $(patsubst %.elf,%.log,$(target_elf))
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ifdef target_tests_nosim
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compile: copy
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# now copy must be performed before compile,
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# allowing us to copy over outputs if they won't simulate on spike correctly.
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endif
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copy:
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@mkdir -p $(work_dir_isa)
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$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
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$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
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$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
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$(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)"
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$(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
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compile: $(combined_elf)
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run: $(target_log)
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# note that run doesnt use the combined elf so it doesnt run the nosim tests.
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#------------------------------------------------------------
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# Clean up
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clean:
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rm -rf $(work_dir)
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@ -1,3 +0,0 @@
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include ../../Makefile.include
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$(eval $(call compile_template,-march=rv32ic -mabi=ilp32 -DXLEN=$(XLEN)))
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@ -1,34 +0,0 @@
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# RISC-V Architecture Test RV32I Makefrag
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#
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# Copyright (c) 2017, Codasip Ltd.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
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||||
# Description: Makefrag for RV32I architectural tests
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rv32i_sc_tests = \
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rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
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target_tests += $(rv32i_tests)
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@ -1,3 +0,0 @@
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include ../../Makefile.include
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$(eval $(call compile_template,-march=rv32if -mabi=ilp32 -DXLEN=$(XLEN) -DFLEN=32))
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@ -1,14 +0,0 @@
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# RISC-V Architecture Test RV32IF Makefrag
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#
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# Copyright (c) 2021. IIT Madras. All rights reserved.
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Description: Makefrag for RV32IF architectural tests
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rv32if_sc_tests = \
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rv32if_tests = $(addsuffix .elf, $(rv32if_sc_tests))
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target_tests += $(rv32if_tests)
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@ -1,3 +0,0 @@
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include ../../Makefile.include
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$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN)))
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||||
@ -1,76 +0,0 @@
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||||
# RISC-V Architecture Test RV32I Makefrag
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||||
#
|
||||
# Copyright (c) 2017, Codasip Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV32I architectural tests
|
||||
|
||||
rv32i_sc_tests = \
|
||||
E-add-01 \
|
||||
E-addi-01 \
|
||||
E-and-01 \
|
||||
E-andi-01 \
|
||||
E-auipc-01 \
|
||||
E-beq-01 \
|
||||
E-bge-01 \
|
||||
E-bgeu-01 \
|
||||
E-blt-01 \
|
||||
E-bltu-01 \
|
||||
E-bne-01 \
|
||||
E-jal-01 \
|
||||
E-jalr-01 \
|
||||
E-lb-align-01 \
|
||||
E-lbu-align-01 \
|
||||
E-lh-align-01 \
|
||||
E-lhu-align-01 \
|
||||
E-lui-01 \
|
||||
E-lw-align-01 \
|
||||
E-or-01 \
|
||||
E-ori-01 \
|
||||
E-sb-align-01 \
|
||||
E-sh-align-01 \
|
||||
E-sll-01 \
|
||||
E-slli-01 \
|
||||
E-slt-01 \
|
||||
E-slti-01 \
|
||||
E-sltiu-01 \
|
||||
E-sltu-01 \
|
||||
E-sra-01 \
|
||||
E-srai-01 \
|
||||
E-srl-01 \
|
||||
E-srli-01 \
|
||||
E-sub-01 \
|
||||
E-sw-align-01 \
|
||||
E-xor-01 \
|
||||
E-xori-01 \
|
||||
WALLY-ADD \
|
||||
WALLY-SLT \
|
||||
WALLY-SLTU \
|
||||
WALLY-SUB \
|
||||
WALLY-XOR
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
target_tests += $(rv32i_tests)
|
||||
@ -1,3 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv32im -mabi=ilp32 -DXLEN=$(XLEN)))
|
||||
@ -1,35 +0,0 @@
|
||||
# RISC-V Architecture Test RV32IM Makefrag
|
||||
#
|
||||
# Copyright (c) 2018, Imperas Software Ltd.
|
||||
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Imperas Software Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV32IM architectural tests
|
||||
|
||||
rv32im_sc_tests = \
|
||||
|
||||
rv32im_tests = $(addsuffix .elf, $(rv32im_sc_tests))
|
||||
|
||||
target_tests += $(rv32im_tests)
|
||||
@ -1,5 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
|
||||
|
||||
$(eval $(call compile_template,-march=rv32iaf -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
@ -1,65 +0,0 @@
|
||||
# RISC-V Architecture Test RV32I Makefrag
|
||||
#
|
||||
# Copyright (c) 2017, Codasip Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV32I architectural tests
|
||||
|
||||
rv32i_sc_tests = \
|
||||
WALLY-mmu-sv32 \
|
||||
WALLY-pm-01 \
|
||||
WALLY-csr-permission-s-01 \
|
||||
WALLY-csr-permission-u-01 \
|
||||
WALLY-misa-01 \
|
||||
WALLY-lrsc-01 \
|
||||
WALLY-status-mie-01 \
|
||||
WALLY-trap-sret-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-cbom-01 \
|
||||
|
||||
target_tests_nosim = \
|
||||
WALLY-pma-01 \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
WALLY-mie-01 \
|
||||
WALLY-sie-01 \
|
||||
WALLY-trap-01 \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
WALLY-wfi-01 \
|
||||
WALLY-status-sie-01 \
|
||||
WALLY-status-tw-01 \
|
||||
WALLY-gpio-01 \
|
||||
WALLY-clint-01 \
|
||||
WALLY-plic-01 \
|
||||
WALLY-uart-01 \
|
||||
WALLY-spi-01 \
|
||||
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
target_tests += $(rv32i_tests)
|
||||
@ -1,3 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv64ic -mabi=lp64 -DXLEN=$(XLEN)))
|
||||
@ -1,35 +0,0 @@
|
||||
# RISC-V Architecture Test RV64I Makefrag
|
||||
#
|
||||
# Copyright (c) 2017, Codasip Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64I architectural tests
|
||||
|
||||
rv64i_sc_tests = \
|
||||
|
||||
|
||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||
|
||||
target_tests += $(rv64i_tests)
|
||||
@ -1,3 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN)))
|
||||
@ -1,35 +0,0 @@
|
||||
# RISC-V Architecture Test RV64IM Makefrag
|
||||
#
|
||||
# Copyright (c) 2018, Imperas Software Ltd.
|
||||
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Imperas Software Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64IM architectural tests
|
||||
|
||||
rv64im_sc_tests = \
|
||||
|
||||
rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests))
|
||||
|
||||
target_tests += $(rv64im_tests)
|
||||
@ -1,3 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN)))
|
||||
@ -1,40 +0,0 @@
|
||||
# RISC-V Architecture Test RV64I Makefrag
|
||||
#
|
||||
# Copyright (c) 2017, Codasip Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64I architectural tests
|
||||
|
||||
rv64i_sc_tests = \
|
||||
WALLY-ADD \
|
||||
WALLY-SUB \
|
||||
WALLY-SLT \
|
||||
WALLY-SLTU \
|
||||
WALLY-XOR \
|
||||
|
||||
|
||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||
|
||||
target_tests += $(rv64i_tests)
|
||||
@ -1,3 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
$(eval $(call compile_template,-march=rv64im -mabi=lp64 -DXLEN=$(XLEN)))
|
||||
@ -1,35 +0,0 @@
|
||||
# RISC-V Architecture Test RV64IM Makefrag
|
||||
#
|
||||
# Copyright (c) 2018, Imperas Software Ltd.
|
||||
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Imperas Software Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64IM architectural tests
|
||||
|
||||
rv64im_sc_tests = \
|
||||
|
||||
rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests))
|
||||
|
||||
target_tests += $(rv64im_tests)
|
||||
@ -1,5 +0,0 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
|
||||
|
||||
$(eval $(call compile_template,-march=rv64iaf -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
@ -1,73 +0,0 @@
|
||||
# RISC-V Architecture Test RV64I Makefrag
|
||||
#
|
||||
# Copyright (c) 2017, Codasip Ltd.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of the Codasip Ltd. nor the
|
||||
# names of its contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Description: Makefrag for RV64I architectural tests
|
||||
|
||||
rv64i_sc_tests = \
|
||||
WALLY-mmu-sv39-01 \
|
||||
WALLY-mmu-sv48-01 \
|
||||
WALLY-pmp-01 \
|
||||
WALLY-csr-permission-s-01 \
|
||||
WALLY-csr-permission-u-01 \
|
||||
WALLY-misa-01 \
|
||||
WALLY-lrsc-01 \
|
||||
WALLY-trap-sret-01 \
|
||||
WALLY-status-mie-01 \
|
||||
WALLY-status-sie-01 \
|
||||
WALLY-status-tw-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-misaligned-access-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-cboz-01 \
|
||||
WALLY-cbom-01 \
|
||||
|
||||
|
||||
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
||||
target_tests_nosim = \
|
||||
WALLY-pma-01 \
|
||||
WALLY-periph-01 \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
WALLY-mie-01 \
|
||||
WALLY-sie-01 \
|
||||
WALLY-trap-01 \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
WALLY-spi-01 \
|
||||
WALLY-gpio-01 \
|
||||
WALLY-uart-01 \
|
||||
WALLY-wfi-01 \
|
||||
|
||||
|
||||
# unclear why status-fp-enabled and wfi aren't simulating ok
|
||||
# DH 10/9/23: minfo needs Privileged Spec 1.12 for the mconfigptr register, but
|
||||
# we don't have the right ISA string so it's compiling at 1.11
|
||||
# and Sail throws an illegal instruction exception on csrr mconfigptr
|
||||
|
||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||
|
||||
target_tests += $(rv64i_tests)
|
||||
Loading…
Reference in New Issue
Block a user