From b3506c755aa26d7b655a867d1bb9ecd5399a7562 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 28 Mar 2022 17:04:58 -0500 Subject: [PATCH] test. --- fpga/generator/wally.tcl | 3 ++ pipelined/src/uncore/ram.sv | 84 ++++++++++++++++++------------------- 2 files changed, 45 insertions(+), 42 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 824574d9c..60666077a 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -52,6 +52,9 @@ report_utilization -hierarchical -file re report_cdc -file reports/cdc.rpt report_clock_interaction -file reports/clock_interaction.rpt +write_verilog -force -mode funcsim sim/syn-funcsim.v + + source ../constraints/debug2.xdc diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index e9b0af32d..61dec5a5c 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -60,48 +60,48 @@ module ram #(parameter BASE=0, RANGE = 65535) ( // *** need to address this preload for fpga. It should work as a preload file // but for some reason vivado is not synthesizing the preload. //$readmemh(PRELOAD, RAM); - RAM[0] = 64'h94e1819300002197; - RAM[1] = 64'h4281420141014081; - RAM[2] = 64'h4481440143814301; - RAM[3] = 64'h4681460145814501; - RAM[4] = 64'h4881480147814701; - RAM[5] = 64'h4a814a0149814901; - RAM[6] = 64'h4c814c014b814b01; - RAM[7] = 64'h4e814e014d814d01; - RAM[8] = 64'h0110011b4f814f01; - RAM[9] = 64'h059b45011161016e; - RAM[10] = 64'h0004063705fe0010; - RAM[11] = 64'h05a000ef8006061b; - RAM[12] = 64'h0ff003930000100f; - RAM[13] = 64'h4e952e3110060e37; - RAM[14] = 64'hc602829b0053f2b7; - RAM[15] = 64'h2023fe02dfe312fd; - RAM[16] = 64'h829b0053f2b7007e; - RAM[17] = 64'hfe02dfe312fdc602; - RAM[18] = 64'h4de31efd000e2023; - RAM[19] = 64'h059bf1402573fdd0; - RAM[20] = 64'h0000061705e20870; - RAM[21] = 64'h0010029b01260613; - RAM[22] = 64'h11010002806702fe; - RAM[23] = 64'h84b2842ae426e822; - RAM[24] = 64'h892ee04aec064505; - RAM[25] = 64'h06e000ef07e000ef; - RAM[26] = 64'h979334fd02905563; - RAM[27] = 64'h07930177d4930204; - RAM[28] = 64'h4089093394be2004; - RAM[29] = 64'h04138522008905b3; - RAM[30] = 64'h19e3014000ef2004; - RAM[31] = 64'h64a2644260e2fe94; - RAM[32] = 64'h6749808261056902; - RAM[33] = 64'hdfed8b8510472783; - RAM[34] = 64'h2423479110a73823; - RAM[35] = 64'h10472783674910f7; - RAM[36] = 64'h20058693ffed8b89; - RAM[37] = 64'h05a1118737836749; - RAM[38] = 64'hfed59be3fef5bc23; - RAM[39] = 64'h1047278367498082; - RAM[40] = 64'h67c98082dfed8b85; - RAM[41] = 64'h0000808210a7a023; + RAM[BASE+0] = 64'h94e1819300002197; + RAM[BASE+1] = 64'h4281420141014081; + RAM[BASE+2] = 64'h4481440143814301; + RAM[BASE+3] = 64'h4681460145814501; + RAM[BASE+4] = 64'h4881480147814701; + RAM[BASE+5] = 64'h4a814a0149814901; + RAM[BASE+6] = 64'h4c814c014b814b01; + RAM[BASE+7] = 64'h4e814e014d814d01; + RAM[BASE+8] = 64'h0110011b4f814f01; + RAM[BASE+9] = 64'h059b45011161016e; + RAM[BASE+10] = 64'h0004063705fe0010; + RAM[BASE+11] = 64'h05a000ef8006061b; + RAM[BASE+12] = 64'h0ff003930000100f; + RAM[BASE+13] = 64'h4e952e3110060e37; + RAM[BASE+14] = 64'hc602829b0053f2b7; + RAM[BASE+15] = 64'h2023fe02dfe312fd; + RAM[BASE+16] = 64'h829b0053f2b7007e; + RAM[BASE+17] = 64'hfe02dfe312fdc602; + RAM[BASE+18] = 64'h4de31efd000e2023; + RAM[BASE+19] = 64'h059bf1402573fdd0; + RAM[BASE+20] = 64'h0000061705e20870; + RAM[BASE+21] = 64'h0010029b01260613; + RAM[BASE+22] = 64'h11010002806702fe; + RAM[BASE+23] = 64'h84b2842ae426e822; + RAM[BASE+24] = 64'h892ee04aec064505; + RAM[BASE+25] = 64'h06e000ef07e000ef; + RAM[BASE+26] = 64'h979334fd02905563; + RAM[BASE+27] = 64'h07930177d4930204; + RAM[BASE+28] = 64'h4089093394be2004; + RAM[BASE+29] = 64'h04138522008905b3; + RAM[BASE+30] = 64'h19e3014000ef2004; + RAM[BASE+31] = 64'h64a2644260e2fe94; + RAM[BASE+32] = 64'h6749808261056902; + RAM[BASE+33] = 64'hdfed8b8510472783; + RAM[BASE+34] = 64'h2423479110a73823; + RAM[BASE+35] = 64'h10472783674910f7; + RAM[BASE+36] = 64'h20058693ffed8b89; + RAM[BASE+37] = 64'h05a1118737836749; + RAM[BASE+38] = 64'hfed59be3fef5bc23; + RAM[BASE+39] = 64'h1047278367498082; + RAM[BASE+40] = 64'h67c98082dfed8b85; + RAM[BASE+41] = 64'h0000808210a7a023; end // initial begin end // if (FPGA)