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busybear: more adapting to new memory system

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This commit is contained in:
Noah Boorstin 2021-03-01 18:50:42 +00:00
parent f11b3108d8
commit b3247eadd2
4 changed files with 99 additions and 114 deletions
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14
wally-pipelined/regression/wally-busybear.do
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@ -37,8 +37,10 @@ mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -fillda
mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
mem load -startaddress 0 -endaddress 16777216 -filltype value -fillradix hex -filldata 0 /testbench_busybear/RAM mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/maindtim/RAM
mem load -startaddress 0 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/RAM mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/maindtim/RAM
mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM
mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM
view wave view wave
@ -57,7 +59,12 @@ add wave /testbench_busybear/lastCheckInstrF
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
add wave -divider add wave -divider
add wave -hex /testbench_busybear/readRAM add wave /testbench_busybear/dut/uncore/HSELBootTim
add wave /testbench_busybear/dut/uncore/HSELTim
add wave /testbench_busybear/dut/uncore/HREADTim
add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYTim
add wave /testbench_busybear/dut/uncore/HADDR
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
@ -73,6 +80,7 @@ add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
add wave -hex /testbench_busybear/HWDATA add wave -hex /testbench_busybear/HWDATA
add wave -hex /testbench_busybear/HRDATA add wave -hex /testbench_busybear/HRDATA
add wave -hex /testbench_busybear/HADDR add wave -hex /testbench_busybear/HADDR
add wave -hex /testbench_busybear/readAdrExpected
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]

22
wally-pipelined/src/uncore/dtim.sv
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@ -28,7 +28,7 @@
module dtim #(parameter BASE=0, RANGE = 65535) ( module dtim #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic [1:0] MemRWtim, input logic [1:0] MemRWtim,
input logic [18:0] HADDR, input logic [31:0] HADDR,
input logic [`XLEN-1:0] HWDATA, input logic [`XLEN-1:0] HWDATA,
input logic HSELTim, input logic HSELTim,
output logic [`XLEN-1:0] HREADTim, output logic [`XLEN-1:0] HREADTim,
@ -36,8 +36,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
); );
//logic [`XLEN-1:0] RAM[0:65535]; //logic [`XLEN-1:0] RAM[0:65535];
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE-BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [18:0] HWADDR; logic [31:0] HWADDR;
logic [`XLEN-1:0] HREADTim0; logic [`XLEN-1:0] HREADTim0;
// logic [`XLEN-1:0] write; // logic [`XLEN-1:0] write;
@ -83,21 +83,21 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
generate generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
// always_ff @(negedge HCLK) // always_ff @(negedge HCLK)
// if (memwrite) RAM[HWADDR[17:3]] <= HWDATA; // if (memwrite) RAM[HWADDR[31:3]] <= HWDATA;
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
//if (memwrite) RAM[HADDR[17:3]] <= HWDATA; //if (memwrite) RAM[HADDR[31:3]] <= HWDATA;
HWADDR <= HADDR; HWADDR <= HADDR;
HREADTim0 <= RAM[HADDR[17:3]]; HREADTim0 <= RAM[HADDR[31:3]];
if (memwrite && HREADYTim) RAM[HWADDR[17:3]] <= HWDATA; if (memwrite && HREADYTim) RAM[HWADDR[31:3]] <= HWDATA;
end end
end else begin end else begin
// always_ff @(negedge HCLK) // always_ff @(negedge HCLK)
// if (memwrite) RAM[HWADDR[17:2]] <= HWDATA; // if (memwrite) RAM[HWADDR[31:2]] <= HWDATA;
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
//if (memwrite) RAM[HADDR[17:2]] <= HWDATA; //if (memwrite) RAM[HADDR[31:2]] <= HWDATA;
HWADDR <= HADDR; HWADDR <= HADDR;
HREADTim0 <= RAM[HADDR[17:2]]; HREADTim0 <= RAM[HADDR[31:2]];
if (memwrite && HREADYTim) RAM[HWADDR[17:2]] <= HWDATA; if (memwrite && HREADYTim) RAM[HWADDR[31:2]] <= HWDATA;
end end
end end
endgenerate endgenerate

10
wally-pipelined/src/uncore/uncore.sv
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@ -95,8 +95,8 @@ module uncore (
subwordwrite sww(.*); subwordwrite sww(.*);
// tightly integrated memory // tightly integrated memory
dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.HADDR(HADDR[18:0]), .*); dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.*);
dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.HADDR(HADDR[18:0]), .MemRWtim(MemRWboottim), dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.MemRWtim(MemRWboottim),
.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); .HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
@ -110,11 +110,11 @@ module uncore (
// AHB Read Multiplexer // AHB Read Multiplexer
assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) | assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) |
({`XLEN{HSELBootTim}} & HREADBootTim) | ({`XLEN{HSELUART}} & HREADUART); ({`XLEN{HSELBootTim}} & HREADBootTim) | ({`XLEN{HSELUART}} & HREADUART);
assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELGPIO & HRESPGPIO | HSELUART & HRESPUART; assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELUART & HRESPUART;
assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELGPIO & HREADYGPIO | HSELUART & HREADYUART; assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | HSELUART & HREADYUART;
// Faults // Faults
assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELGPIO | HSELUART); assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELUART);
endmodule endmodule

43
wally-pipelined/testbench/testbench-busybear.sv
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@ -174,52 +174,27 @@ module testbench_busybear();
// In the linux boot, the processor spends the first ~5 instructions in // In the linux boot, the processor spends the first ~5 instructions in
// bootram, before jr jumps to main RAM // bootram, before jr jumps to main RAM
logic [`XLEN-1:0] RAM[('h8000000 >> 3):0];
logic [`XLEN-1:0] bootram[('h2000 >> 3):0];
logic [`XLEN-1:0] readRAM;
integer RAMAdr, RAMPC;
assign RAMAdr = (HADDR - (HADDR > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
assign RAMPC = (dut.PCF - (dut.PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
logic [63:0] readMask; logic [63:0] readMask;
assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
logic [`XLEN-1:0] readAdrExpected; logic [`XLEN-1:0] readAdrExpected;
always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
if (HWRITE) begin
RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size
end else begin
readRAM = RAM[RAMAdr] & readMask;
end
end
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin
if (HWRITE) begin
bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask);
end else begin
readRAM = bootram[RAMAdr] & readMask;
end
end
end
always @(dut.hart.MemRWM[1] or HADDR) begin always @(dut.hart.MemRWM[1] or HADDR) begin
if (dut.hart.MemRWM[1]) begin if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");
`ERROR `ERROR
end end
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
#1; #2;
if (~equal(HADDR,readAdrExpected,4)) begin if (~equal(HADDR,readAdrExpected,4)) begin
$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
`ERROR `ERROR
end end
if (((readMask & HRDATA) !== (readMask & readRAM)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
$display("warning %0t ps, instr %0d: HRDATA does not equal readRAM: %x, %x from address %x, %x", $time, instrs, HRDATA, readRAM, HADDR, HSIZE); $display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
warningCount += 1; warningCount += 1;
`ERROR `ERROR
end end
@ -360,7 +335,8 @@ module testbench_busybear();
end end
logic [31:0] InstrMask; logic [31:0] InstrMask;
logic forcedInstr; logic forcedInstr;
always @(dut.PCF) begin always @(dut.PCF or dut.hart.ifu.InstrF) begin
if (~reset && dut.hart.ifu.InstrF !== {32{1'bx}}) begin
lastCheckInstrF = CheckInstrF; lastCheckInstrF = CheckInstrF;
lastPC <= dut.PCF; lastPC <= dut.PCF;
lastPC2 <= lastPC; lastPC2 <= lastPC;
@ -430,17 +406,18 @@ module testbench_busybear();
`ERROR `ERROR
end end
InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF; InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.InstrF) !== (InstrMask & CheckInstrF))) begin if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrF) !== (InstrMask & CheckInstrF))) begin
$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.InstrF, CheckInstrF, dut.PCF); $display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrF, CheckInstrF, dut.PCF);
`ERROR `ERROR
end end
end end
end end
end
// Track names of instructions // Track names of instructions
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
instrNameDecTB dec(dut.InstrF, InstrFName); instrNameDecTB dec(dut.hart.ifu.InstrF, InstrFName);
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, InstrW, dut.hart.ifu.InstrM, InstrW,