Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

removed now-redundant zero-extend mux in alu

Browse Source
This commit is contained in:
Kevin Kim 2023-02-24 17:14:12 -08:00
parent 0fe1d3b9f3
commit b3180d7307
1 changed files with 5 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/ieu/alu.sv
View File

@ -78,22 +78,17 @@ module alu #(parameter WIDTH=32) (
// shifter rotate source select mux
if (`ZBB_SUPPORTED) begin
if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A;
else assign rotA = A; // NOTE: change this for the future!
else assign rotA = A;
end else assign rotA = A;
if (`ZBA_SUPPORTED) begin: zbamuxes
// Zero Extend Mux
if (WIDTH == 64) begin
assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage?
end else assign CondZextA = A;
// Pre-Shift Mux
always_comb
case (Funct3[2:1] & {2{BSelect[3]}})
2'b00: CondShiftA = CondZextA;
2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add
2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add
2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add
2'b00: CondShiftA = shA[63:0];
2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add
2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add
2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add
endcase
end else assign CondShiftA = A;