From 6bec559ba60d568493e33c3e7b7435232fc49dee Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Tue, 21 Nov 2023 19:49:14 -0800
Subject: [PATCH 01/48] Removed stale signals from wave.do

---
 sim/wave.do | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/sim/wave.do b/sim/wave.do
index 3f2bcd72a..3a5fd9369 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -120,7 +120,6 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/z
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/ByteMaskMuxM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM
-add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/LSUWriteDataShiftedM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask
@@ -128,14 +127,12 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/b
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel
 add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData}
-add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ziccslm_align/align/IncrementAmount
 add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE
 add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM
 add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
@@ -212,7 +209,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}

From d1bb5c7512957b3bc4c1cf5956526182ddbfe254 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Tue, 21 Nov 2023 21:52:11 -0800
Subject: [PATCH 02/48] Imperas fix for satp modes supported

---
 linux/Makefile | 3 ++-
 sim/imperas.ic | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/linux/Makefile b/linux/Makefile
index 520c7cd44..a2cded5ea 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -39,6 +39,7 @@ Image:
 	# source ../setup.sh; $(MAKE) disassemble
 
 install:
+	sudo rm -rf $(RISCV)/$(BUILDROOT)
 	sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
 
 # Temp rule for debugging
@@ -62,10 +63,10 @@ $(RISCV):
 
 
 disassemble:
+	rm -rf $(BUILDROOT)/output/images/disassembly
 	find  $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs  cp -t $(BUILDROOT)/output/images/
 	mkdir -p $(DIS)
 	make -j $(OBJDUMPS)
-	make -j $(OBJDUMPS).addr
 
 $(DIS)/%.objdump: $(IMAGES)/%.elf
 	riscv64-unknown-elf-objdump -DS $< >> $@
diff --git a/sim/imperas.ic b/sim/imperas.ic
index 4106968ed..be6b7cca6 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -32,6 +32,9 @@
 --override cpu/Svpbmt=T
 --override cpu/Svnapot_page_mask=65536
 
+# SV39 and SV48 supported
+--override cpu/Sv_modes=768
+
 
 #  clarify
 #--override refRoot/cpu/mtvec_sext=F

From 35d30a5a31b82251d5b479b55e050060a199f553 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 22 Nov 2023 15:23:03 +0300
Subject: [PATCH 03/48] Fix testplan link

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 0dc68f1c1..b9d378fc3 100644
--- a/README.md
+++ b/README.md
@@ -8,7 +8,7 @@ Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by H
 
 # Verification
 
-Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplan.md) for details.
+Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplans/testplan.md) for details.
 
 # New User Setup
 

From e66adcca9dc3d03949f163236f6f09bbe45a7c23 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 22 Nov 2023 05:25:09 -0800
Subject: [PATCH 04/48] Cleaned up genInitMem script to only generate necessary
 files and eliminate prompts

---
 linux/testvector-generation/genInitMem.sh | 109 ++++++++++------------
 1 file changed, 50 insertions(+), 59 deletions(-)

diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh
index d34b758f8..b9c1d8c41 100755
--- a/linux/testvector-generation/genInitMem.sh
+++ b/linux/testvector-generation/genInitMem.sh
@@ -10,63 +10,54 @@ rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin"
 untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin"
 DEVICE_TREE=${imageDir}/wally-virt.dtb
 
-read -p "Warning: running this script will overwrite the contents of:
-  * $rawRamFile
-  * $ramFile
-  * $rawBootmemFile
-  * $bootmemFile
-  * $rawUntrimmedBootmemFile
-  * $untrimmedBootmemFile
-Would you like to proceed? (y/n) " -n 1 -r
-echo
-if [[ $REPLY =~ ^[Yy]$ ]]
-then
-    if [ ! -d "$tvDir" ]; then
-        echo "Error: linux testvector directory $tvDir not found!">&2
-        echo "Please create it. For example:">&2
-        echo "    sudo mkdir -p $tvDir">&2
-        exit 1
-    fi
-    test -w $tvDir
-    if [ ! $? -eq 0 ]; then
-        echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
-        echo "Please chmod it. For example:">&2
-        echo "    sudo chmod -R a+rw $tvDir">&2
-        exit 1
-    fi
-
-    echo "Launching QEMU in replay mode!"
-    (qemu-system-riscv64 \
-    -M virt -m 256M -dtb $DEVICE_TREE \
-    -nographic \
-    -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-    -gdb tcp::$tcpPort -S) \
-    & riscv64-unknown-elf-gdb --quiet \
-    -ex "set pagination off" \
-    -ex "set logging overwrite on" \
-    -ex "set logging redirect on" \
-    -ex "set confirm off" \
-    -ex "target extended-remote :$tcpPort" \
-    -ex "maintenance packet Qqemu.PhyMemMode:1" \
-    -ex "printf \"Creating $rawBootmemFile\n\"" \
-    -ex "dump binary memory $rawBootmemFile 0x1000 0x1fff" \
-    -ex "printf \"Creating $rawUntrimmedBootmemFile\n\"" \
-    -ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \
-    -ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \
-    -ex "printf \"Creating $rawRamFile\n\"" \
-    -ex "dump binary memory $rawRamFile 0x80000000 0x8fffffff" \
-    -ex "kill" \
-    -ex "q"
-
-    echo "Changing Endianness"
-    make fixBinMem
-    ./fixBinMem "$rawRamFile" "$ramFile"
-    ./fixBinMem "$rawBootmemFile" "$bootmemFile"
-    ./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile"
-
-    echo "genInitMem.sh completed!"
-    echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
-    echo "Run the following:"
-    echo "    sudo chown -R cad:cad $tvDir"
-    echo "    sudo chmod -R go-w $tvDir"
+if [ ! -d "$tvDir" ]; then
+    echo "Error: linux testvector directory $tvDir not found!">&2
+    echo "Please create it. For example:">&2
+    echo "    sudo mkdir -p $tvDir">&2
+    exit 1
 fi
+test -w $tvDir
+if [ ! $? -eq 0 ]; then
+    echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
+    echo "Please chmod it. For example:">&2
+    echo "    sudo chmod -R a+rw $tvDir">&2
+    exit 1
+fi
+
+echo "Launching QEMU in replay mode!"
+(qemu-system-riscv64 \
+-M virt -m 256M -dtb $DEVICE_TREE \
+-nographic \
+-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+-gdb tcp::$tcpPort -S) \
+& riscv64-unknown-elf-gdb --quiet \
+-ex "set pagination off" \
+-ex "set logging overwrite on" \
+-ex "set logging redirect on" \
+-ex "set confirm off" \
+-ex "target extended-remote :$tcpPort" \
+-ex "maintenance packet Qqemu.PhyMemMode:1" \
+-ex "printf \"Creating $rawBootmemFile\n\"" \
+-ex "dump binary memory $rawBootmemFile 0x1000 0x1fff" \
+-ex "printf \"Creating $rawRamFile\n\"" \
+-ex "dump binary memory $rawRamFile 0x80000000 0x8fffffff" \
+-ex "kill" \
+-ex "q"
+
+#-ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \
+#-ex "printf \"Creating $rawUntrimmedBootmemFile\n\"" \
+#-ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \
+
+echo "Changing Endianness"
+make fixBinMem
+./fixBinMem "$rawRamFile" "$ramFile"
+./fixBinMem "$rawBootmemFile" "$bootmemFile"
+#./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile"  # doesn't seem to be used for anything
+rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile"
+
+echo "genInitMem.sh completed!"
+echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
+echo "Run the following:"
+echo "    sudo chown -R cad:cad $tvDir"
+echo "    sudo chmod -R go-w $tvDir"
+

From c64ad9ff355db32e521b2b5af86c0e7c0db6e92a Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 22 Nov 2023 06:28:38 -0800
Subject: [PATCH 05/48] Extract rootfs during disassembly

---
 linux/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/linux/Makefile b/linux/Makefile
index a2cded5ea..cc19c7f2a 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -67,6 +67,10 @@ disassemble:
 	find  $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs  cp -t $(BUILDROOT)/output/images/
 	mkdir -p $(DIS)
 	make -j $(OBJDUMPS)
+	# extract rootfs
+	mkdir -p $(BUILDROOT)/output/images/disassembly/rootfs
+	echo "Ignore error about dev/console when extracting rootfs from rootfs.cpio"
+	-cpio -i -D $(BUILDROOT)/output/images/disassembly/rootfs < $(BUILDROOT)/output/images/rootfs.cpio
 
 $(DIS)/%.objdump: $(IMAGES)/%.elf
 	riscv64-unknown-elf-objdump -DS $< >> $@

From 1d234c05c99bb1679c8a26140915cb90b7a22cf6 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 22 Nov 2023 22:17:01 -0800
Subject: [PATCH 06/48] disassembleBootTrace works on first 50M lines of boot

---
 .gitignore                                    |  2 +
 linux/bootmem.txt                             |  2 +-
 .../disassembleBootTrace.py                   | 74 +++++++++++++++++++
 3 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100755 linux/testvector-generation/disassembleBootTrace.py

diff --git a/.gitignore b/.gitignore
index 3990c3823..f0afc3a98 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,6 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
+linux/testvector-generation/boottrace.S
+linux/testvector-generation/boottrace_disasm.log
 sim/slack-notifier/slack-webhook-url.txt
 sim/logs
 fpga/generator/IP
diff --git a/linux/bootmem.txt b/linux/bootmem.txt
index 047cf5529..7cf7d8453 100644
--- a/linux/bootmem.txt
+++ b/linux/bootmem.txt
@@ -5,7 +5,7 @@
 00001010: 0182b283		ld t0, 24(t0)		# t0 = 80000000 - start of firmware
 00001014: 00028067		jr t0			# jump to firmware
 00001018: 0000000080000000			# firmware start address
-00001020: 0000000087000000			# flattened device tree load address
+00001020: 000000008fe00000			# flattened device tree load address
 00001028: 000000004942534f			# a2 points to this 8 dword data structure
 00001030: 0000000000000002
 00001038: 0000000080200000
diff --git a/linux/testvector-generation/disassembleBootTrace.py b/linux/testvector-generation/disassembleBootTrace.py
new file mode 100755
index 000000000..12e2202cb
--- /dev/null
+++ b/linux/testvector-generation/disassembleBootTrace.py
@@ -0,0 +1,74 @@
+#!/usr/bin/python3
+# 
+# disassembleBootTrace.py
+# David_Harris@hmc.edu 22 November 2023
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# 
+# Reads boottrace.log and disassembles the machine code
+#
+
+import csv
+import os
+import re
+
+# read a file from sim/logs/boottrace.log and extract the second comma-separated field containing the instruction
+print("Reading boottrace.log")
+trace = []
+count = 0
+with open('../../sim/logs/boottrace.log') as f:
+    reader = csv.reader(f, delimiter=',')
+    for row in reader:
+        trace.append(row)
+        count = count + 1
+        if count > 50000000:
+            break
+f.close()
+
+print("Disassembling boottrace.log instructions")
+# Write an assembly language file with the machine code
+with (open('boottrace.S', 'w')) as f:
+    f.write('main:\n')
+    for row in trace:
+        instr = row[1]
+        # scrape off leading white space from instr
+        instr = instr.lstrip()
+        # check if last character indicates an compressed or uncompressed instruction
+        lastNibble = instr[-1]
+        if (lastNibble == '3' or lastNibble == '7' or lastNibble == 'b' or lastNibble == 'f'): 
+            # uncompressed
+             f.write('.word 0x' + instr + '\n')
+        else:
+            # compressed
+            instr = instr[-4:]
+            f.write('.hword 0x' + instr + '\n')
+f.close()
+
+# Then assemble and disassemble the file
+os.system('riscv64-unknown-elf-gcc -march=rv64gqc_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64d -c boottrace.S')
+os.system('riscv64-unknown-elf-objdump -D boottrace.o > boottrace.objdump')
+
+# Patch disassembly back into boottrace
+print("Inserting disassembly into trace")
+dumpedLines = []
+with (open('boottrace.objdump', 'r')) as f:
+    lines = f.readlines()
+    f.close()
+lines = lines[7:]       # skip header
+p = r'[^:]*:\s*(\S*)\s*(.*)'
+for line in lines:
+    match = re.search(p, line)
+    if (match):
+        dump = [match.group(1), match.group(2)]
+        dumpedLines.append(dump)
+
+linenum = 0
+for i in range(len(trace)):
+    row = trace[i]
+    row.insert(2, dumpedLines[i][1])
+
+# write trace back to csv file
+print("Writing trace back to boottrace_disasm.log")
+with (open('boottrace_disasm.log', 'w')) as f:
+    writer = csv.writer(f)
+    writer.writerows(trace)
+f.close()

From 1ab75220642fa06b2ef5239d1c1292bdd7c94d58 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Thu, 23 Nov 2023 17:56:51 -0600
Subject: [PATCH 07/48] Update fix for cvtint testbench-fp

---
 sim/testfloat.do          |  2 +-
 testbench/testbench-fp.sv | 13 +++++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/sim/testfloat.do b/sim/testfloat.do
index 85bd6dfc5..f21975389 100644
--- a/sim/testfloat.do
+++ b/sim/testfloat.do
@@ -28,7 +28,7 @@ vlib work
 vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
 # Change TEST_SIZE to only test certain FP width
-# values are QP, DP, SP, HP
+# values are QP, DP, SP, HP or all for all tests
 vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" 
 
 # Set WAV variable to avoid having any output to wave (to limit disk space)
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index e5f215e07..84b1ae3c7 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -964,11 +964,16 @@ module testbenchfp;
 
       // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but 
       // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
+
+      // Note: Went through and determined that this is not needed with new module additions
+      // Just needs to check flags against TestFloat (left just in case (remove after check one more time)) 
+      // else if ((UnitVal === `CVTINTUNIT) & 
+      //       ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | 
+      //		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | 
+      //	  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
+      //	  (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
       else if ((UnitVal === `CVTINTUNIT) & 
-	       ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | 
-		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | 
-		  (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
-		  (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
+		  ~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin	 
 	 errors += 1;
 	 $display("There is an error in %s", Tests[TestNum]);
 	 $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);

From 1f57df7f8b378cea00e66cd82d962df5af8d4d20 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 23 Nov 2023 20:29:10 -0800
Subject: [PATCH 08/48] Fixed reference to deleted atomic signal in cache

---
 src/lsu/lsu.sv              | 4 ++--
 testbench/common/loggers.sv | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 396fa1515..5c21d7ecd 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -196,8 +196,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign PreLSURWM = MemRWM; 
     assign IHAdrM = IEUAdrExtM;
     assign LSUFunct3M = Funct3M;
-  assign LSUFunct7M = Funct7M; 
-  assign LSUAtomicM = AtomicM;
+    assign LSUFunct7M = Funct7M; 
+    assign LSUAtomicM = AtomicM;
     assign IHWriteDataM = WriteDataM;
     assign LoadAccessFaultM = LSULoadAccessFaultM;
     assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;   
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 1cf719085..e1cc1795f 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -182,7 +182,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
                       (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
                       dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
       AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
-                         dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
+                         dut.core.lsu.LSUAtomicM[1] ? "A" :
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
                          "NULL";

From 3df4c13daa8fa7485c0f1f2dbdb08ed4ab1adfe7 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 23 Nov 2023 20:36:45 -0800
Subject: [PATCH 09/48] Updated wallyTracer for Linux boot and wally-batch.do
 to remove buildroot checkpoint support

---
 sim/wally-batch.do              | 8 ++++----
 testbench/common/wallyTracer.sv | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/sim/wally-batch.do b/sim/wally-batch.do
index 29d31bd25..df34aa0b3 100644
--- a/sim/wally-batch.do
+++ b/sim/wally-batch.do
@@ -58,15 +58,15 @@ if {$argc >= 3} {
 
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32imc rv32imc
-if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
+if {$2 eq "buildroot"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
     if { $coverage } {
         echo "wally-batch buildroot coverage"
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt +cover=sbecf
         vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7 -cover
      } else {
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt 
         vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
     }
 
@@ -76,7 +76,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 } elseif {$2 eq "buildroot-no-trace"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt 
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -G NO_SPOOFING=1 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 1ba7f010d..746fde068 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -23,7 +23,7 @@
 `define NUM_REGS 32
 `define NUM_CSRS 4096
 
-`define STD_LOG 0
+`define STD_LOG 1
 `define PRINT_PC_INSTR 0
 `define PRINT_MOST 0
 `define PRINT_ALL 0
@@ -502,7 +502,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   if(`STD_LOG) begin
     instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName);
     initial begin
-      LogFile = "logs/InstrTrace.log";
+      LogFile = "logs/boottrace.log";
       file = $fopen(LogFile, "w");
     end
   end

From 0c789c2fbda255884ebf0cbdc0189bff51eead73 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 26 Nov 2023 15:34:40 -0600
Subject: [PATCH 10/48] Fixed subtle bug in the embench makefile if the
 sim/wkdir directory did not exist.

---
 benchmarks/embench/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index d7a18b7e2..d8fbddae9 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -43,6 +43,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
+	mkdir -p ../../sim/wkdir
 	(cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
@@ -82,4 +83,4 @@ clean:
 allclean: clean
 	rm -rf $(embench_dir)/logs/
 
-# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c
\ No newline at end of file
+# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c

From e747f97dceb1ba23d45217f660cf508a06fe0e0c Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 26 Nov 2023 17:30:11 -0600
Subject: [PATCH 11/48] Fixed repeatability issues with the branch predictor
 simulator results generation. I reran using a clean clone of the repo so this
 should be working now.

---
 bin/CModelBTBAccuracy.sh    |  8 ++++----
 bin/CModelBranchAccuracy.sh |  2 +-
 bin/parseHPMC.py            | 13 +++++++------
 3 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh
index e4a26fb85..479340eb2 100755
--- a/bin/CModelBTBAccuracy.sh
+++ b/bin/CModelBTBAccuracy.sh
@@ -40,18 +40,18 @@ do
 	lines=`sim_bp gshare 16 16 $Size 1  $File | tail -5`
         Total=`echo "$lines" | head -1 | awk '{print $5}'`
         Miss=`echo "$lines" | tail -2 | head -1 | awk '{print $8}'`
-        BMDR=`echo "$Miss / $Total" | bc -l`
+        BMDR=`echo "100.0 * $Miss / $Total" | bc -l`
         BMDRArray+=("$BMDR")
         if [ $Miss -eq 0 ]; then
-	    Product=`echo "scale=200; $Product / $Total" | bc -l`
+	    Product=`echo "scale=200; $Product * 100 / $Total" | bc -l`
         else
-            Product=`echo "scale=200; $Product * $Miss / $Total" | bc -l`
+            Product=`echo "scale=200; $Product * $BMDR" | bc -l`
         fi
 	Count=$((Count+1))
     done
     # with such long precision bc outputs onto multiple lines
     # must remove \n and \ from string
     Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'`
-    GeoMean=`perl -E "say $Product**(1/$Count) * 100"`
+    GeoMean=`perl -E "say $Product**(1/$Count)"`
     echo "$Pred$Size $GeoMean"
 done
diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh
index 1b94f7c9a..8253891bb 100755
--- a/bin/CModelBranchAccuracy.sh
+++ b/bin/CModelBranchAccuracy.sh
@@ -46,7 +46,7 @@ do
 	do
 	    #echo "sim_bp $Pred $Size $Size 18 1 $File | tail -1 | awk '{print $4}'"
 	    #echo "sim_bp $Pred $SizeString $File | tail -1 | awk '{print $4}'"
-	    BMDR=`sim_bp $Pred $SizeString $File | tail -1 | awk '{print $4}'`
+	    BMDR=`sim_bp -c $Pred $SizeString $File | tail -1 | awk '{print $4}'`
 	    Product=`echo "$Product * $BMDR" | bc`
 	    Count=$((Count+1))
 	done
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index a11296b3e..f9a961c18 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -32,12 +32,13 @@ import math
 import numpy as np
 import argparse
 
-RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
-           ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
-           ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
-           ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
-RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.11806778745097), ('BTBCModel8', 'BTBCModel', 256, 0.183833943219956), ('BTBCModel10', 'BTBCModel', 1024, 0.0109271020749376),
-              ('BTBCModel12', 'BTBCModel', 4096, 0.00437600802791213), ('BTBCModel14', 'BTBCModel', 16384, 0.00188756234204305), ('BTBCModel16', 'BTBCModel', 65536, 0.00188756234204305)]
+
+RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 7.29493318805151),
+           ('twobitCModel12', 'twobitCModel', 4096, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 5.68432926870082),
+           ('gshareCModel6', 'gshareCModel', 64, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 6.32975690693015),
+           ('gshareCModel12', 'gshareCModel', 4096, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 1.90424999467293)]
+RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 0.0117345454469572),
+              ('BTBCModel12', 'BTBCModel', 4096, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 0.000732471628510962)]
 
 def ParseBranchListFile(path):
     '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File

From 93c356d50dd4953fd3d648df103f9a26209371b9 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 26 Nov 2023 17:31:23 -0600
Subject: [PATCH 12/48] Added files to ignore file.

---
 .gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.gitignore b/.gitignore
index f0afc3a98..1664b939f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -180,3 +180,5 @@ sim/branch*.log
 benchmarks/embench/wally*.json
 benchmarks/embench/run*
 sim/cfi.log
+sim/cfi/*
+sim/branch/*

From 3dfca61c3fbf081d1844fa851dbfebfe4cd224e3 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 26 Nov 2023 22:19:34 -0600
Subject: [PATCH 13/48] Changes to support concurrent simulation of all the
 branch predictor sweeps.

---
 bin/parseHPMC.py               | 13 +++++++------
 sim/bp-results/branch-list.txt | 24 ++++++++++++------------
 sim/bp-results/btb-list.txt    | 12 ++++++------
 sim/bp-results/class-list.txt  | 12 ++++++------
 sim/bpred-sim.py               |  2 +-
 5 files changed, 32 insertions(+), 31 deletions(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index f9a961c18..d76a52d29 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -276,7 +276,7 @@ def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
     return(xlabelListTrunk, seriesDictTrunk)
 
 
-def ReportAsGraph(benchmarkDict, bar):
+def ReportAsGraph(benchmarkDict, bar, FileName):
     def FormatToPlot(currBenchmark):
         names = []
         sizes = []
@@ -330,8 +330,8 @@ def ReportAsGraph(benchmarkDict, bar):
         axes.set_xticks(xdata)
         axes.set_xticklabels(xdata)
         axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
-        plt.show()
-        
+        if(FileName == None): plt.show()
+        else: plt.savefig(FileName)        
 
     # if(not args.summary):
     #     size = len(benchmarkDict)
@@ -390,7 +390,7 @@ def ReportAsGraph(benchmarkDict, bar):
         # on each piece.
         for row in range(0, math.ceil(NumBenchmarks / BenchPerRow)):
             (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
-            FileName = 'barSegment%d.png' % row
+            FileName = 'barSegment%d.svg' % row
             groupLen = len(xlabelListTrunk)
             BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName, (row == 0))
 
@@ -415,7 +415,8 @@ displayMode.add_argument('--text', action='store_const', help='Display in text f
 displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
 displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
 displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
-parser.add_argument('sources', nargs=1)
+parser.add_argument('sources', nargs=1, help='File lists the input Questa transcripts to process.')
+parser.add_argument('FileName', metavar='FileName', type=str, nargs='?', help='output graph to file <name>.png If not included outputs to screen.', default=None)
 
 args = parser.parse_args()
 
@@ -455,7 +456,7 @@ if(ReportMode == 'text'):
     ReportAsText(benchmarkDict)
 
 if(ReportMode == 'gui'):
-    ReportAsGraph(benchmarkDict, args.bar)
+    ReportAsGraph(benchmarkDict, args.bar, args.FileName)
             
 # *** this is only needed of -b (no -s)
 
diff --git a/sim/bp-results/branch-list.txt b/sim/bp-results/branch-list.txt
index c241610d3..956fc9847 100644
--- a/sim/bp-results/branch-list.txt
+++ b/sim/bp-results/branch-list.txt
@@ -1,12 +1,12 @@
-gshare6.log gshare 6
-gshare8.log gshare 8
-gshare10.log gshare 10
-gshare12.log gshare 12
-gshare14.log gshare 14
-gshare16.log gshare 16
-twobit6.log twobit 6
-twobit8.log twobit 8
-twobit10.log twobit 10
-twobit12.log twobit 12
-twobit14.log twobit 14
-twobit16.log twobit 16
+../logs/rv32gc_gshare6.log gshare 6
+../logs/rv32gc_gshare8.log gshare 8
+../logs/rv32gc_gshare10.log gshare 10
+../logs/rv32gc_gshare12.log gshare 12
+../logs/rv32gc_gshare14.log gshare 14
+../logs/rv32gc_gshare16.log gshare 16
+../logs/rv32gc_twobit6.log twobit 6
+../logs/rv32gc_twobit8.log twobit 8
+../logs/rv32gc_twobit10.log twobit 10
+../logs/rv32gc_twobit12.log twobit 12
+../logs/rv32gc_twobit14.log twobit 14
+../logs/rv32gc_twobit16.log twobit 16
diff --git a/sim/bp-results/btb-list.txt b/sim/bp-results/btb-list.txt
index 741efdf24..30811459e 100644
--- a/sim/bp-results/btb-list.txt
+++ b/sim/bp-results/btb-list.txt
@@ -1,6 +1,6 @@
-btb6.log btb 6
-btb8.log btb 8
-btb10.log btb 10
-btb12.log btb 12
-btb14.log btb 14
-btb16.log btb 16
+../logs/rv32gc_BTB6.log btb 6
+../logs/rv32gc_BTB8.log btb 8
+../logs/rv32gc_BTB10.log btb 10
+../logs/rv32gc_BTB12.log btb 12
+../logs/rv32gc_BTB14.log btb 14
+../logs/rv32gc_BTB16.log btb 16
diff --git a/sim/bp-results/class-list.txt b/sim/bp-results/class-list.txt
index 0d24aa6ee..3926af969 100644
--- a/sim/bp-results/class-list.txt
+++ b/sim/bp-results/class-list.txt
@@ -1,6 +1,6 @@
-class6.log class 6
-class8.log class 8
-class10.log class 10
-class12.log class 12
-class14.log class 14
-class16.log class 16
+../logs/rv32gc_class6.log class 6
+../logs/rv32gc_class8.log class 8
+../logs/rv32gc_class10.log class 10
+../logs/rv32gc_class12.log class 12
+../logs/rv32gc_class14.log class 14
+../logs/rv32gc_class16.log class 16
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 60af41298..c04b9bd51 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -132,7 +132,7 @@ def main():
         # BTB and class size sweep
         bpdSize = [6, 8, 10, 12, 14, 16]
         for CurrBPSize in bpdSize:
-            name = 'BTB'+str(CurrBPSize)
+            name = 'class'+str(CurrBPSize)
             configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+RAS_SIZE=16+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE" 
             tc = TestCase(
                 name=name,

From 7b0e29c9f7f1af7dffcb48e83cc0efd4b3a81e62 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 26 Nov 2023 23:13:14 -0600
Subject: [PATCH 14/48] Fixed subtle bug in branch prediction post processing
 script.

---
 bin/parseHPMC.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index d76a52d29..7e8eb7cde 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -255,9 +255,9 @@ def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName, IncludeLegend):
     fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
     colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
     for name in seriesDict:
-        xpos = np.arange(BenchPerRow)
-        xpos = [x + index*barWidth for x in xpos]
         values = seriesDict[name]
+        xpos = np.arange(len(values))
+        xpos = [x + index*barWidth for x in xpos]
         plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
         index += 1
     plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)

From 35a7b2bd24184100a9c74612509c273d6c2cac9f Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 00:35:22 -0600
Subject: [PATCH 15/48] Last little hickups out of the branch predictor results
 parsing.

---
 sim/bp-results/ras-list.txt | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/sim/bp-results/ras-list.txt b/sim/bp-results/ras-list.txt
index b3e273a3d..c7628ffaa 100644
--- a/sim/bp-results/ras-list.txt
+++ b/sim/bp-results/ras-list.txt
@@ -1,5 +1,5 @@
-ras3.log ras 3
-ras4.log ras 4
-ras6.log ras 6
-ras10.log ras 10
-ras16.log ras 16
+../logs/rv32gc_RAS3.log ras 3
+../logs/rv32gc_RAS4.log ras 4
+../logs/rv32gc_RAS6.log ras 6
+../logs/rv32gc_RAS10.log ras 10
+../logs/rv32gc_RAS16.log ras 16

From d918791a6078deeb98a1a21eef667bbc05812993 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 01:26:49 -0600
Subject: [PATCH 16/48] Fixed bug in the wally do script.

---
 sim/wally-batch.do | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/wally-batch.do b/sim/wally-batch.do
index df34aa0b3..b117e1691 100644
--- a/sim/wally-batch.do
+++ b/sim/wally-batch.do
@@ -63,10 +63,10 @@ if {$2 eq "buildroot"} {
     # start and run simulation
     if { $coverage } {
         echo "wally-batch buildroot coverage"
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt +cover=sbecf
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt +cover=sbecf
         vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7 -cover
      } else {
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -o testbenchopt 
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt 
         vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
     }
 
@@ -76,7 +76,7 @@ if {$2 eq "buildroot"} {
 } elseif {$2 eq "buildroot-no-trace"} {
     vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G -G NO_SPOOFING=1 -o testbenchopt 
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt 
     vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
 
     #-- Run the Simulation

From d7ef490c125c385130b8f0dab6a22142122e8289 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 01:27:09 -0600
Subject: [PATCH 17/48] Sutble bug in the cacheway logic for cacheline
 invalidation.

---
 src/cache/cacheway.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 9fb836e93..67f4f5a74 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -68,7 +68,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic                               SelTag;
   logic                               SelectedWriteWordEn;
   logic [LINELEN/8-1:0]               FinalByteMask;
-  logic                               SetValidEN;
+  logic                               SetValidEN, ClearValidEN;
   logic                               SetValidWay;
   logic                               ClearValidWay;
   logic                               SetDirtyWay;
@@ -102,6 +102,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   assign ClearDirtyWay = ClearDirty & SelData;
   assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;  // exclusion-tag: icache SelectedWiteWordEn
   assign SetValidEN = SetValidWay & ~FlushStage;                           // exclusion-tag: cache SetValidEN
+  assign ClearValidEN = ClearValidWay & ~FlushStage;                           // exclusion-tag: cache SetValidEN
 
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
@@ -156,7 +157,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
     if(CacheEn) begin 
       ValidWay <= #1 ValidBits[CacheSet];
       if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
-      else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay;
+      else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay;
+      else if (ClearValidEN) ValidBits[CacheSet] <= #1 '0;
     end
   end
 

From c3da4c3c31fa133567f31e7ca99766728d0fcb7f Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 12:56:11 -0600
Subject: [PATCH 18/48] Clarified names in cacheway.

---
 src/cache/cacheway.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 67f4f5a74..382d9ae6d 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -65,7 +65,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic [LINELEN-1:0]                 ReadDataLine;
   logic [TAGLEN-1:0]                  ReadTag;
   logic                               Dirty;
-  logic                               SelTag;
+  logic                               SelDirty;
   logic                               SelectedWriteWordEn;
   logic [LINELEN/8-1:0]               FinalByteMask;
   logic                               SetValidEN, ClearValidEN;
@@ -78,7 +78,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   
   if (!READ_ONLY_CACHE) begin:flushlogic
     logic                               FlushWayEn;
-    mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
+    mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelDirty);
 
     // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
     // coverage off -item e 1 -fecexprrow 3
@@ -86,11 +86,11 @@ module cacheway import cvw::*; #(parameter cvw_t P,
     assign FlushWayEn = FlushWay & SelFlush;
     assign SelNonHit = FlushWayEn | SelWay; 
   end else begin:flushlogic // no flush operation for read-only caches.
-    assign SelTag = VictimWay;
+    assign SelDirty = VictimWay;
     assign SelNonHit = SelWay;
   end
 
-  mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
+  mux2 #(1) selectedwaymux(HitWay, SelDirty, SelNonHit , SelData);
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Enable demux
@@ -117,7 +117,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   // AND portion of distributed tag multiplexer
   assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
-  assign DirtyWay = SelTag & Dirty & ValidWay;
+  assign DirtyWay = SelDirty & Dirty & ValidWay;
   assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
 
   /////////////////////////////////////////////////////////////////////////////////////////////

From 08549446ef576c5bee9143a1ef18a2bb7a01e49b Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 13:13:36 -0600
Subject: [PATCH 19/48] Reduced cache fsm complexity.

---
 src/cache/cachefsm.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 8a11dd735..0e07793d6 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -130,8 +130,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
       STATE_READ_HOLD:       if(Stall)                                         NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_READY;
       // exclusion-tag-start: icache case
-      STATE_WRITEBACK:       if (CacheBusAck & (CMOp[1] | CMOp[2]))            NextState = STATE_READ_HOLD;
-                             else if(CacheBusAck & ~CMOp[3])                   NextState = STATE_FETCH;
+      STATE_WRITEBACK:       if(CacheBusAck & ~CMOp[3])                        NextState = STATE_FETCH;
                              else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.

From 337903d8dd7019f7201e5e4c615bc914015990fc Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 14:59:42 -0600
Subject: [PATCH 20/48] More cache simplifications.

---
 src/cache/cache.sv    | 13 +++----------
 src/cache/cachefsm.sv |  3 ---
 src/lsu/lsu.sv        | 13 ++++++++++---
 3 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index 4701fc4c7..c527f0eae 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -98,8 +98,6 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic                          SelWay;
   logic [LINELEN/8-1:0]          LineByteMask;
   logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
-  logic                                                   ZeroCacheLine;
-  logic [LINELEN-1:0]                                     PreLineWriteData;
   genvar                         index;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
@@ -161,11 +159,6 @@ module cache import cvw::*; #(parameter cvw_t P,
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path
   /////////////////////////////////////////////////////////////////////////////////////////////
-  if(P.ZICBOZ_SUPPORTED) begin : cboz_supported
-    mux2 #(LINELEN) WriteDataMux(FetchBuffer, '0, ZeroCacheLine, PreLineWriteData);
-  end else begin
-    assign PreLineWriteData = FetchBuffer;
-  end
   if(!READ_ONLY_CACHE) begin:WriteSelLogic
     logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;
 
@@ -185,14 +178,14 @@ module cache import cvw::*; #(parameter cvw_t P,
     // Merge write data into fetched cache line for store miss
     for(index = 0; index < LINELEN/8; index++) begin
       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
-        .d1(PreLineWriteData[8*index+7:8*index]), .s(FetchBufferByteSel[index] | ZeroCacheLine), .y(LineWriteData[8*index+7:8*index]));
+        .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index] & ~CMOp[3]), .y(LineWriteData[8*index+7:8*index]));
     end
     assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
   end
   else
     begin:WriteSelLogic
       // No need for this mux if the cache does not handle writes.
-      assign LineWriteData = PreLineWriteData;
+      assign LineWriteData = FetchBuffer;
       assign LineByteMask = '1;
     end
   
@@ -227,7 +220,7 @@ module cache import cvw::*; #(parameter cvw_t P,
     .FlushStage, .CacheRW, .Stall,
     .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, 
     .CacheMiss, .CacheAccess, .SelAdr, .SelWay,
-    .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush,
+    .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush,
     .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
     .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
     .InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn);
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 0e07793d6..e7e5e0306 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -58,7 +58,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   output logic       ClearValid,        // Clear the valid bit in the selected way and set
   output logic       SetDirty,          // Set the dirty bit in the selected way and set
   output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
-  output logic       ZeroCacheLine,     // Write zeros to all bytes of cacheline
   output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback
   output logic       LRUWriteEn,        // Update the LRU state
   output logic       SelFlush,          // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
@@ -174,8 +173,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
                   (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) | 
                   (CurrState == STATE_WRITE_LINE);
-  assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) | 
-                                               (CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));  
   assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
                         (CurrState == STATE_READY & AnyMiss & LineDirty);
   assign SelFlush = (CurrState == STATE_READY & FlushCache) |
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 5c21d7ecd..d82c9c02d 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -148,7 +148,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
   logic                  IgnoreRequest;                          // On FlushM or TLB miss ignore memory operation
   logic                  SelDTIM;                                // Select DTIM rather than bus or D$
-
+  logic [P.XLEN-1:0]     WriteDataZM;
+  
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
   // Zero-extend address to 34 bits for XLEN=32
@@ -176,6 +177,12 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign {SpillStallM, SelStoreDelay} = '0;
   end
 
+    if(P.ZICBOZ_SUPPORTED) begin : cboz
+      mux2 #(P.XLEN) writedatacbozmux(WriteDataM, '0, CMOpM[3], WriteDataZM);
+    end else begin : cboz
+      assign WriteDataZM = WriteDataM;
+    end
+
   /////////////////////////////////////////////////////////////////////////////////////////////
   // HPTW (only needed if VM supported)
   // MMU include PMP and is needed if any privileged supported
@@ -187,7 +194,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_HADE, .PrivilegeModeW,
       .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
-      .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
+      .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
       .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
       .IHAdrM, .HPTWStall, .SelHPTW,
       .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, 
@@ -198,7 +205,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign LSUFunct3M = Funct3M;
     assign LSUFunct7M = Funct7M; 
     assign LSUAtomicM = AtomicM;
-    assign IHWriteDataM = WriteDataM;
+    assign IHWriteDataM = WriteDataZM;
     assign LoadAccessFaultM = LSULoadAccessFaultM;
     assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;   
     assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;

From beb95dd592431023408113658263a6613c9b3333 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 17:44:11 -0600
Subject: [PATCH 21/48] Modified the pmachecker to correctly check the
 permissions for cmo instructions. However this isn't fully tested.

---
 src/ifu/ifu.sv        |  2 +-
 src/lsu/lsu.sv        | 12 ++++++++----
 src/mmu/adrdecs.sv    | 12 ++++++------
 src/mmu/mmu.sv        |  3 ++-
 src/mmu/pmachecker.sv | 11 +++++++----
 src/uncore/uncore.sv  |  2 +-
 6 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 831d9e6bb..7d61bd4db 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -182,7 +182,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
          .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
          .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
          .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
-         .UpdateDA(InstrUpdateDAF),
+         .UpdateDA(InstrUpdateDAF), .CMOp(4'b0),
          .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
          .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
 
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index d82c9c02d..2bb604d39 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -228,7 +228,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
     logic WriteAccessM;
     assign DisableTranslation = SelHPTW | FlushDCacheM;
-    assign WriteAccessM = PreLSURWM[0] | (|CMOpM);
+    assign WriteAccessM = PreLSURWM[0];
     mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
     dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
       .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
@@ -238,7 +238,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM, 
     .StoreAmoPageFaultM,
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,   // *** these faults need to be supressed during hptw.
-      .UpdateDA(DataUpdateDAM),
+      .UpdateDA(DataUpdateDAM), .CMOp(CMOpM),
       .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), 
       .WriteAccessM, .ReadAccessM(PreLSURWM[1]),
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
@@ -301,8 +301,12 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       logic                    FlushDCache;                                      // Suppress d cache flush if there is an ITLB miss.
       logic                    CacheStall;
       logic [1:0]              CacheBusRWTemp;
-      
-      assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
+
+      if(P.ZICBOZ_SUPPORTED) begin 
+        assign BusRW = ~CacheableM & ~SelDTIM ? CMOpM[3] ? 2'b01 : LSURWM : '0;
+      end else begin
+        assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
+      end
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
       assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0;
       assign FlushDCache = FlushDCacheM & ~(SelHPTW);
diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index 3ee9c23d5..69b3a8c1d 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -30,18 +30,18 @@
 
 module adrdecs import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0] PhysicalAddress,
-  input  logic                 AccessRW, AccessRX, AccessRWX,
+  input  logic                 AccessRW, AccessRX, AccessRWXZ, AccessRWZ, AccessRXZ,
   input  logic [1:0]           Size,
   output logic [11:0]          SelRegions
 );
 
   localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
  // Determine which region of physical memory (if any) is being accessed
-  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]);  
-  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[10]);  
-  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[9]);  
-  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[8]);
-  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[7]);
+  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRWZ, Size, SUPPORTED_SIZE, SelRegions[11]);  
+  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRXZ, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[9]);  
+  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRXZ, Size, SUPPORTED_SIZE, SelRegions[8]);
+  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[7]);
   adrdec #(P.PA_BITS) clintdec(PhysicalAddress, P.CLINT_BASE[P.PA_BITS-1:0], P.CLINT_RANGE[P.PA_BITS-1:0], P.CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[6]);
   adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[5]);
   adrdec #(P.PA_BITS) uartdec(PhysicalAddress, P.UART_BASE[P.PA_BITS-1:0], P.UART_RANGE[P.PA_BITS-1:0], P.UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[4]);
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index a497b6da7..16016ac47 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -55,6 +55,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   output logic                 UpdateDA,                                                  // page fault due to setting dirty or access bit
   output logic                 LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
   // PMA checker signals
+  input  logic [3:0]           CMOp,                                                      // Cache management instructions
   input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
   input var logic [7:0]        PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],                      // PMP configuration
   input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0]                   // PMP addresses
@@ -106,7 +107,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   // Check physical memory accesses
   ///////////////////////////////////////////
 
-  pmachecker #(P) pmachecker(.PhysicalAddress, .Size,
+  pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOp, 
     .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
     .Cacheable, .Idempotent, .SelTIM, 
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index 7aa20fc2f..1ccf6501c 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -31,6 +31,7 @@
 module pmachecker import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0] PhysicalAddress,
   input  logic [1:0]           Size,
+  input  logic [3:0]           CMOp,
   input  logic                 AtomicAccessM,  // Atomic access
   input  logic                 ExecuteAccessF, // Execute access 
   input  logic                 WriteAccessM,   // Write access 
@@ -43,18 +44,20 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 );
 
   logic                        PMAAccessFault;
-  logic                        AccessRW, AccessRWX, AccessRX;
+  logic                        AccessRW, AccessRWXZ, AccessRX, AccessRWZ, AccessRXZ;
   logic [11:0]                 SelRegions;
   logic                        AtomicAllowed;
   logic                        CacheableRegion, IdempotentRegion;
 
   // Determine what type of access is being made
   assign AccessRW  = ReadAccessM | WriteAccessM;
-  assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
+  assign AccessRWZ  = AccessRW | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
+  assign AccessRWXZ = ReadAccessM | WriteAccessM | ExecuteAccessF | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & (CMOp[3]));
   assign AccessRX  = ReadAccessM | ExecuteAccessF;
+  assign AccessRXZ  = AccessRX | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
 
   // Determine which region of physical memory (if any) is being accessed
-  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
+  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXZ, AccessRWZ, AccessRXZ, Size, SelRegions);
 
   // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
   assign CacheableRegion = SelRegions[9] | SelRegions[8] | SelRegions[7];  // exclusion-tag: unused-cachable
@@ -71,7 +74,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   assign SelTIM = SelRegions[11] | SelRegions[10]; // exclusion-tag: unused-idempotent
 
   // Detect access faults
-  assign PMAAccessFault          = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;  
+  assign PMAAccessFault          = (SelRegions[0]) & AccessRWXZ | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
   assign PMAStoreAmoAccessFaultM = WriteAccessM   & PMAAccessFault;
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index 60d197f78..ee93c2904 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -88,7 +88,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   // Determine which region of physical memory (if any) is being accessed
   // Use a trimmed down portion of the PMA checker - only the address decoders
   // Set access types to all 1 as don't cares because the MMU has already done access checking
-  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
+  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
   assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELEXTSDC, HSELSPI} = HSELRegions[11:1];

From 9290c3f95798df94d01bce762c41802307ca482a Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 20:57:33 -0600
Subject: [PATCH 22/48] Added correct cbo fault behavior.

---
 src/mmu/pmachecker.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index 1ccf6501c..a48ccd241 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -77,5 +77,5 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   assign PMAAccessFault          = (SelRegions[0]) & AccessRWXZ | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
-  assign PMAStoreAmoAccessFaultM = WriteAccessM   & PMAAccessFault;
+  assign PMAStoreAmoAccessFaultM = (WriteAccessM | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & CMOp[3]))   & PMAAccessFault;
 endmodule

From 195def58080d68602520b8eab28e301776397390 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 21:24:30 -0600
Subject: [PATCH 23/48] Extended the abhcacheinterface to zero a cacheline's
 worth of uncached memory on cbo.zero.

---
 src/ebu/ahbcacheinterface.sv |  9 ++++++---
 src/ebu/buscachefsm.sv       | 16 ++++++++++------
 src/ifu/ifu.sv               |  2 +-
 src/lsu/lsu.sv               |  8 +++++---
 4 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
index 054022106..78b0d15e8 100644
--- a/src/ebu/ahbcacheinterface.sv
+++ b/src/ebu/ahbcacheinterface.sv
@@ -66,6 +66,7 @@ module ahbcacheinterface #(
   input logic [LLEN-1:0]      WriteDataM,              // IEU write data for uncached store
   input logic [1:0]           BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
   input logic [2:0]           Funct3,                  // Size of uncached memory operation
+  input logic                 BusCMOZero,               // Uncached cbo.zero must write zero to full sized cacheline without going through the cache
 
   // lsu/ifu interface
   input logic                 Stall,                   // Core pipeline is stalled
@@ -80,6 +81,7 @@ module ahbcacheinterface #(
   logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
   logic [AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
   logic [AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
+  logic [PA_BITS-1:0]         PAdrZero;
 
   genvar                      index;
 
@@ -91,10 +93,11 @@ module ahbcacheinterface #(
       .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW]));
   end
 
-  mux2 #(PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
+  assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr;
+  mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR);
   assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR;
 
-  mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
+  mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE));
 
   // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
   logic [AHBW-1:0]          CacheReadDataWordAHB;
@@ -119,6 +122,6 @@ module ahbcacheinterface #(
   
   buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
     .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
-    .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
+    .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed,
     .HREADY, .HTRANS, .HWRITE, .HBURST);
 endmodule
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index 4d1d475d8..45f66762f 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -42,6 +42,7 @@ module buscachefsm #(
   input  logic                   Stall,              // Core pipeline is stalled
   input  logic                   Flush,              // Pipeline stage flush. Prevents bus transaction from starting
   input  logic [1:0]             BusRW,              // Uncached memory operation read/write control: 10: read, 01: write
+  input  logic                   BusCMOZero,         // Uncached cbo.zero must write zero to full sized cacheline without going through the cache
   output logic                   BusStall,           // Bus is busy with an in flight memory operation
   output logic                   BusCommitted,       // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
                             
@@ -75,6 +76,9 @@ module buscachefsm #(
   logic                   BeatCntEn;
   logic                   BeatCntReset;
   logic                   CacheAccess;
+  logic                   BusWrite;
+
+  assign BusWrite = CacheBusRW[0] | BusCMOZero;
   
   always_ff @(posedge HCLK)
     if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
@@ -83,18 +87,18 @@ module buscachefsm #(
   always_comb begin
       case(CurrState)
         ADR_PHASE: if (HREADY & |BusRW)                             NextState = DATA_PHASE;
-                   else if (HREADY & CacheBusRW[0])                 NextState = CACHE_WRITEBACK;
+                   else if (HREADY & BusWrite)                 NextState = CACHE_WRITEBACK;
                    else if (HREADY & CacheBusRW[1])                 NextState = CACHE_FETCH;
                    else                                             NextState = ADR_PHASE;
       DATA_PHASE:  if(HREADY)                                       NextState = MEM3;
                    else                                             NextState = DATA_PHASE;
       MEM3:        if(Stall)                                        NextState = MEM3;
                    else                                             NextState = ADR_PHASE;
-      CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0])      NextState = CACHE_WRITEBACK;
+      CACHE_FETCH: if(HREADY & FinalBeatCount & BusWrite)      NextState = CACHE_WRITEBACK;
                    else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
                    else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
                    else                                             NextState = CACHE_FETCH;
-      CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0])  NextState = CACHE_WRITEBACK;
+      CACHE_WRITEBACK: if(HREADY & FinalBeatCount & BusWrite)  NextState = CACHE_WRITEBACK;
                    else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
                    else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
                    else                                             NextState = CACHE_WRITEBACK;
@@ -128,7 +132,7 @@ module buscachefsm #(
                   (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
                   (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
 
-  assign HWRITE = (BusRW[0] | CacheBusRW[0] & ~Flush) | (CurrState == CACHE_WRITEBACK & |BeatCount);
+  assign HWRITE = (BusRW[0] | BusWrite & ~Flush) | (CurrState == CACHE_WRITEBACK & |BeatCount);
   assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;  
   
   always_comb begin
@@ -142,8 +146,8 @@ module buscachefsm #(
   end
 
   // communication to cache
-  assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount);
-  assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
+  assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount & ~BusCMOZero);
+  assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | BusWrite)) |
                       (CurrState == DATA_PHASE & BusRW[0]) |
                       (CurrState == CACHE_WRITEBACK) |
                       (CurrState == CACHE_FETCH);
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 7d61bd4db..4a02848b5 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -252,7 +252,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
       ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
             .HRDATA,
-            .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
+            .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
             .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
             .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
             .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 2bb604d39..6fe4377fc 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -301,12 +301,14 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       logic                    FlushDCache;                                      // Suppress d cache flush if there is an ITLB miss.
       logic                    CacheStall;
       logic [1:0]              CacheBusRWTemp;
+      logic                    BusCMOZero;
 
       if(P.ZICBOZ_SUPPORTED) begin 
-        assign BusRW = ~CacheableM & ~SelDTIM ? CMOpM[3] ? 2'b01 : LSURWM : '0;
+        assign BusCMOZero = CMOpM[3] & ~CacheableM;
       end else begin
-        assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
+        assign BusCMOZero = '0;
       end
+      assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
       assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0;
       assign FlushDCache = FlushDCacheM & ~(SelHPTW);
@@ -332,7 +334,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
         .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
         .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
         .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM),
-        .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
+        .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusCMOZero, .CacheableOrFlushCacheM,
         .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
         .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
         .BusStall, .BusCommitted(BusCommittedM));

From 69653e5faacff63c4165e0e4ef45a3a3bca7e881 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 27 Nov 2023 23:38:53 -0600
Subject: [PATCH 24/48] Fixed minor bug in the cbo hazard logic.

---
 src/ieu/controller.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index a489b7f86..c9195132c 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -426,5 +426,8 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // atomic operations are also detected as MemRWD[1]
   //assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
   // *** RT: Modify for ZICBOZ
-  assign StoreStallD = (MemRWE[0] | (|CMOpE & P.ZICBOM_SUPPORTED)) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | (|CMOpD & P.ZICBOM_SUPPORTED)));
+  logic cboD, cboE;
+  assign cboE = (|CMOpE[2:0] & P.ZICBOM_SUPPORTED) | (CMOpE[3] & P.ZICBOZ_SUPPORTED);
+  assign cboD = (|CMOpD[2:0] & P.ZICBOM_SUPPORTED) | (CMOpD[3] & P.ZICBOZ_SUPPORTED);
+  assign StoreStallD = (MemRWE[0] | cboE) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | cboD));
 endmodule

From 9a24a5d9570f846ffb2c555932cdb369ebac73a1 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 00:05:12 -0600
Subject: [PATCH 25/48] Renamed signal in pmachecker.

---
 src/mmu/adrdecs.sv    | 8 ++++----
 src/mmu/pmachecker.sv | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index 69b3a8c1d..922b98efb 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -30,17 +30,17 @@
 
 module adrdecs import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0] PhysicalAddress,
-  input  logic                 AccessRW, AccessRX, AccessRWXZ, AccessRWZ, AccessRXZ,
+  input  logic                 AccessRW, AccessRX, AccessRWXZ, AccessRWC, AccessRXC,
   input  logic [1:0]           Size,
   output logic [11:0]          SelRegions
 );
 
   localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
  // Determine which region of physical memory (if any) is being accessed
-  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRWZ, Size, SUPPORTED_SIZE, SelRegions[11]);  
-  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRXZ, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRWC, Size, SUPPORTED_SIZE, SelRegions[11]);  
+  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRXC, Size, SUPPORTED_SIZE, SelRegions[10]);  
   adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[9]);  
-  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRXZ, Size, SUPPORTED_SIZE, SelRegions[8]);
+  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRXC, Size, SUPPORTED_SIZE, SelRegions[8]);
   adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[7]);
   adrdec #(P.PA_BITS) clintdec(PhysicalAddress, P.CLINT_BASE[P.PA_BITS-1:0], P.CLINT_RANGE[P.PA_BITS-1:0], P.CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[6]);
   adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[5]);
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index a48ccd241..016d4defe 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -44,20 +44,20 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 );
 
   logic                        PMAAccessFault;
-  logic                        AccessRW, AccessRWXZ, AccessRX, AccessRWZ, AccessRXZ;
+  logic                        AccessRW, AccessRWXZ, AccessRX, AccessRWC, AccessRXC;
   logic [11:0]                 SelRegions;
   logic                        AtomicAllowed;
   logic                        CacheableRegion, IdempotentRegion;
 
   // Determine what type of access is being made
   assign AccessRW  = ReadAccessM | WriteAccessM;
-  assign AccessRWZ  = AccessRW | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
+  assign AccessRWC  = AccessRW | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
   assign AccessRWXZ = ReadAccessM | WriteAccessM | ExecuteAccessF | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & (CMOp[3]));
   assign AccessRX  = ReadAccessM | ExecuteAccessF;
-  assign AccessRXZ  = AccessRX | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
+  assign AccessRXC  = AccessRX | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
 
   // Determine which region of physical memory (if any) is being accessed
-  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXZ, AccessRWZ, AccessRXZ, Size, SelRegions);
+  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXZ, AccessRWC, AccessRXC, Size, SelRegions);
 
   // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
   assign CacheableRegion = SelRegions[9] | SelRegions[8] | SelRegions[7];  // exclusion-tag: unused-cachable

From 0229df4a0ff383e876f13c7b1d74524933b714a8 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 01:03:48 -0600
Subject: [PATCH 26/48] Oups. Introduced undetected bug into the cache's cbo
 insructions.

---
 src/cache/cachefsm.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index e7e5e0306..f7edfb733 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -129,7 +129,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
       STATE_READ_HOLD:       if(Stall)                                         NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_READY;
       // exclusion-tag-start: icache case
-      STATE_WRITEBACK:       if(CacheBusAck & ~CMOp[3])                        NextState = STATE_FETCH;
+      STATE_WRITEBACK:       if(CacheBusAck & ~(|CMOp[3:1]))                   NextState = STATE_FETCH;
                              else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.

From 4d4790ecf9a73ef93e628de619630a3110744bd7 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 14:18:06 -0600
Subject: [PATCH 27/48] Optimizations to cclsm.

---
 src/lsu/align.sv | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index ce704a316..a52ebdd02 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -65,12 +65,12 @@ module align import cvw::*;  #(parameter cvw_t P) (
   typedef enum logic [1:0]  {STATE_READY, STATE_SPILL, STATE_STORE_DELAY} statetype;
 
   statetype          CurrState, NextState;
-  logic              TakeSpillM;
+  logic              ValidSpillM;
   logic              SpillM;
   logic              SelSpillM;
   logic              SpillSaveM;
   logic [P.LLEN-1:0]   ReadDataWordFirstHalfM;
-  logic              MisalignedM;
+  logic              ValidMisalignedM, MisalignedM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
 
@@ -78,7 +78,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   logic [(P.LLEN-1)*2/8:0] ByteMaskSaveM;
   logic [(P.LLEN-1)*2/8:0] ByteMaskMuxM;
-  logic                    SaveByteMask;
   logic HalfMisalignedM, WordMisalignedM;
   logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
   logic [$clog2(LLENINBYTES)-1:0]                 ByteOffsetM;
@@ -118,7 +117,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10;
   assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM;
   assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM;
-  assign ValidAccess = (|MemRWM) & ~SelHPTW;
+  assign ValidAccess = (|MemRWM);
 
   if(P.LLEN == 64) begin
     logic DoubleSpillM;
@@ -126,15 +125,16 @@ module align import cvw::*;  #(parameter cvw_t P) (
     assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11;
     assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM;
     assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM | DoubleMisalignedM);
-    assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM);
+    assign SpillM = ValidAccess & (HalfSpillM | WordSpillM | DoubleSpillM);
   end else begin
-    assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM);
+    assign SpillM = ValidAccess & (HalfSpillM | WordSpillM);
     assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM);
   end
       
   // align by shifting
   // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
-  assign TakeSpillM = SpillM & ~CacheBusHPWTStall & ~(DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM));
+  assign ValidSpillM = SpillM & ~CacheBusHPWTStall;
+  assign ValidMisalignedM = MisalignedM & ~SelHPTW;
   
   always_ff @(posedge clk)
     if (reset | FlushM)    CurrState <= #1 STATE_READY;
@@ -142,8 +142,8 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   always_comb begin
     case (CurrState)
-      STATE_READY: if (TakeSpillM & ~MemRWM[0])   NextState = STATE_SPILL;
-                   else if(TakeSpillM & MemRWM[0])NextState = STATE_STORE_DELAY;
+      STATE_READY: if (ValidSpillM & ~MemRWM[0])   NextState = STATE_SPILL;
+                   else if(ValidSpillM & MemRWM[0])NextState = STATE_STORE_DELAY;
                    else                           NextState = STATE_READY;
       STATE_SPILL: if(StallM)                     NextState = STATE_SPILL;
                    else                           NextState = STATE_READY;
@@ -153,9 +153,8 @@ module align import cvw::*;  #(parameter cvw_t P) (
   end
 
   assign SelSpillM = (CurrState == STATE_SPILL | CurrState == STATE_STORE_DELAY);
-  assign SelSpillE = (CurrState == STATE_READY & TakeSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
-  assign SaveByteMask = (CurrState == STATE_READY & TakeSpillM);
-  assign SpillSaveM = (CurrState == STATE_READY) & TakeSpillM & ~FlushM;
+  assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
+  assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
   assign SelStoreDelay = (CurrState == STATE_STORE_DELAY);  // *** Can this be merged into the PreLSURWM logic?
   assign SpillStallM = SelSpillE | CurrState == STATE_STORE_DELAY;
   mux2 #(2) memrwmux(MemRWM, 2'b00, SelStoreDelay, MemRWSpillM);
@@ -173,14 +172,14 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> (MisalignedM ? 8 * AccessByteOffsetM : '0);
+  assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 
   // write path. Also has the 8:1 shifter muxing for the byteoffset
   // then it also has the mux to select when a spill occurs
   logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM;  // *** RT: Find a better way.  I've extending in both directions so we don't shift in zeros.  The cache expects the writedata to not have any zero data, but instead replicated data.
 
-  assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << (MisalignedM ? 8 * AccessByteOffsetM : '0);
+  assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
   assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
 
   mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
@@ -188,6 +187,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
                                       {{{P.LLEN/8}{1'b0}}, ByteMaskMuxM[P.LLEN*2/8-1:P.LLEN/8]}, // spill, second half
                                       {SelSpillM, SelSpillE}, ByteMaskSpillM);
 
-  flopenr #(P.LLEN*2/8) bytemaskreg(clk, reset, SaveByteMask, {ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM);
+  flopenr #(P.LLEN*2/8) bytemaskreg(clk, reset, SpillSaveM, {ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM);
   mux2 #(P.LLEN*2/8) bytemasksavemux({ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM, SelSpillM, ByteMaskMuxM);
 endmodule

From df854280413d5f81c83f53d79413be29a94623ac Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 14:19:30 -0600
Subject: [PATCH 28/48] More optimizations for cclsm.

---
 src/lsu/align.sv | 3 ---
 src/lsu/lsu.sv   | 4 ++--
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index a52ebdd02..1f7f50ec4 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -37,7 +37,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   input logic [P.XLEN-1:0]        IEUAdrE, // The next IEUAdrM
   input logic [2:0]               Funct3M, // Size of memory operation
   input logic [1:0]               MemRWM, 
-  input logic                     CacheableM,
   input logic [P.LLEN*2-1:0]      DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
   input logic                     CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
   input logic                     DTLBMissM, // ITLB miss, ignore memory request
@@ -54,7 +53,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0]       IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
   output logic [P.XLEN-1:0]       IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
   output logic                    SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic [1:0]              MemRWSpillM, 
   output logic                    SelStoreDelay, //*** this is bad.  really don't like moving this outside
   output logic [P.LLEN-1:0]       DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction
   output logic                    SpillStallM);
@@ -157,7 +155,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
   assign SelStoreDelay = (CurrState == STATE_STORE_DELAY);  // *** Can this be merged into the PreLSURWM logic?
   assign SpillStallM = SelSpillE | CurrState == STATE_STORE_DELAY;
-  mux2 #(2) memrwmux(MemRWM, 2'b00, SelStoreDelay, MemRWSpillM);
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Merge spilled data
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 6fe4377fc..81da2c075 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -159,10 +159,10 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   if(MISALIGN_SUPPORT) begin : ziccslm_align
     logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
-                     .MemRWM, .CacheableM,
+                     .MemRWM,
                      .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .SelHPTW,
                      .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
-                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM,
+                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM,
                      .SelStoreDelay);
     assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; 
     assign IEUAdrExtE = {2'b00, IEUAdrSpillE};

From f4e77e96694722d678e551c2a92f1ac7b285ba0b Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 14:21:37 -0600
Subject: [PATCH 29/48] Clean up.

---
 src/lsu/align.sv | 2 --
 src/lsu/lsu.sv   | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 1f7f50ec4..645054058 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -39,8 +39,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   input logic [1:0]               MemRWM, 
   input logic [P.LLEN*2-1:0]      DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
   input logic                     CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic                     DTLBMissM, // ITLB miss, ignore memory request
-  input logic                     DataUpdateDAM, // ITLB miss, ignore memory request
   input logic                     SelHPTW,
 
   input logic [(P.LLEN-1)/8:0]    ByteMaskM,
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 81da2c075..2b8a65ac6 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -160,7 +160,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
                      .MemRWM,
-                     .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .SelHPTW,
+                     .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
                      .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
                      .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM,
                      .SelStoreDelay);

From 865ebf8b9bb60dad52897dd42d06a9a1316ceb51 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 19:41:46 -0600
Subject: [PATCH 30/48] cclsm cleanup.

---
 src/lsu/align.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 645054058..00261ca24 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -79,6 +79,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic [$clog2(LLENINBYTES)-1:0]                 ByteOffsetM;
   logic                                HalfSpillM, WordSpillM;
   logic [$clog2(LLENINBYTES)-1:0]      AccessByteOffsetM;
+  logic [$clog2(LLENINBYTES)+2:0]      ShiftAmount;
   logic                                ValidAccess;
 
   /* verilator lint_off WIDTHEXPAND */
@@ -167,14 +168,15 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
+  assign ShiftAmount = ValidMisalignedM ? 8 * AccessByteOffsetM : '0;
+  assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 
   // write path. Also has the 8:1 shifter muxing for the byteoffset
   // then it also has the mux to select when a spill occurs
   logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM;  // *** RT: Find a better way.  I've extending in both directions so we don't shift in zeros.  The cache expects the writedata to not have any zero data, but instead replicated data.
 
-  assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << (ValidMisalignedM ? 8 * AccessByteOffsetM : '0);
+  assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
   assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
 
   mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill

From a69a70ba7fd8867a14a0ec30e643ae19fb14174b Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 19:54:25 -0600
Subject: [PATCH 31/48] Removed unused hardware from alignment.

---
 src/lsu/align.sv | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 00261ca24..b3a20e9b4 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -65,22 +65,20 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic              SpillM;
   logic              SelSpillM;
   logic              SpillSaveM;
-  logic [P.LLEN-1:0]   ReadDataWordFirstHalfM;
+  logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
   logic              ValidMisalignedM, MisalignedM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
 
-  logic [P.XLEN-1:0]     IEUAdrIncrementM;
+  logic [P.XLEN-1:0]   IEUAdrIncrementM;
 
-  logic [(P.LLEN-1)*2/8:0] ByteMaskSaveM;
-  logic [(P.LLEN-1)*2/8:0] ByteMaskMuxM;
-  logic HalfMisalignedM, WordMisalignedM;
+  logic                HalfMisalignedM, WordMisalignedM;
   logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
-  logic [$clog2(LLENINBYTES)-1:0]                 ByteOffsetM;
-  logic                                HalfSpillM, WordSpillM;
-  logic [$clog2(LLENINBYTES)-1:0]      AccessByteOffsetM;
-  logic [$clog2(LLENINBYTES)+2:0]      ShiftAmount;
-  logic                                ValidAccess;
+  logic [$clog2(LLENINBYTES)-1:0]              ByteOffsetM;
+  logic                                        HalfSpillM, WordSpillM;
+  logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
+  logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
+  logic                                        ValidAccess;
 
   /* verilator lint_off WIDTHEXPAND */
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@@ -179,11 +177,9 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
   assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
 
-  mux3 #(2*P.LLEN/8) bytemaskspillmux(ByteMaskMuxM, // no spill
+  mux3 #(2*P.LLEN/8) bytemaskspillmux({ByteMaskExtendedM, ByteMaskM}, // no spill
                                       {{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
-                                      {{{P.LLEN/8}{1'b0}}, ByteMaskMuxM[P.LLEN*2/8-1:P.LLEN/8]}, // spill, second half
+                                      {{{P.LLEN/8}{1'b0}}, ByteMaskExtendedM}, // spill, second half
                                       {SelSpillM, SelSpillE}, ByteMaskSpillM);
 
-  flopenr #(P.LLEN*2/8) bytemaskreg(clk, reset, SpillSaveM, {ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM);
-  mux2 #(P.LLEN*2/8) bytemasksavemux({ByteMaskExtendedM, ByteMaskM}, ByteMaskSaveM, SelSpillM, ByteMaskMuxM);
 endmodule

From 143c6ca4d190aff8b288429c15112a65256e3fe7 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 22:28:11 -0600
Subject: [PATCH 32/48] Simplification to alignment.

---
 src/lsu/align.sv | 40 ++++++++++++++--------------------------
 1 file changed, 14 insertions(+), 26 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index b3a20e9b4..91eda1b8c 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -72,13 +72,10 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   logic [P.XLEN-1:0]   IEUAdrIncrementM;
 
-  logic                HalfMisalignedM, WordMisalignedM;
-  logic [OFFSET_BIT_POS-1:$clog2(LLENINBYTES)] WordOffsetM;
-  logic [$clog2(LLENINBYTES)-1:0]              ByteOffsetM;
-  logic                                        HalfSpillM, WordSpillM;
   logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
   logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
   logic                                        ValidAccess;
+  logic                                        PotentialSpillM;
 
   /* verilator lint_off WIDTHEXPAND */
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@@ -95,36 +92,27 @@ module align import cvw::*;  #(parameter cvw_t P) (
   // 2) offset
   // 3) access location within the cacheline
   
-  assign {WordOffsetM, ByteOffsetM} = IEUAdrM[OFFSET_BIT_POS-1:0];
-
   always_comb begin
     case (Funct3M[1:0]) 
       2'b00: AccessByteOffsetM = '0; // byte access
-      2'b01: AccessByteOffsetM = {2'b00, ByteOffsetM[0]}; // half access
-      2'b10: AccessByteOffsetM = {1'b0, ByteOffsetM[1:0]}; // word access
-      2'b11: AccessByteOffsetM = ByteOffsetM; // double access
-      default: AccessByteOffsetM = ByteOffsetM;
+      2'b01: AccessByteOffsetM = {2'b00, IEUAdrM[0]}; // half access
+      2'b10: AccessByteOffsetM = {1'b0, IEUAdrM[1:0]}; // word access
+      2'b11: AccessByteOffsetM = IEUAdrM[2:0]; // double access
+      default: AccessByteOffsetM = IEUAdrM[2:0];
+    endcase
+    case (Funct3M[1:0]) 
+      2'b00: PotentialSpillM = '0; // byte access
+      2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access
+      2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access
+      2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access
+      default: PotentialSpillM = '0;
     endcase
   end
+  assign MisalignedM = ValidAccess & (AccessByteOffsetM != '0);
+  assign SpillM = MisalignedM & PotentialSpillM;
 
   // compute misalignement
-  assign HalfMisalignedM = (ByteOffsetM[0] != '0) & Funct3M[1:0] == 2'b01;
-  assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10;
-  assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM;
-  assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM;
   assign ValidAccess = (|MemRWM);
-
-  if(P.LLEN == 64) begin
-    logic DoubleSpillM;
-    logic DoubleMisalignedM;
-    assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11;
-    assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM;
-    assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM | DoubleMisalignedM);
-    assign SpillM = ValidAccess & (HalfSpillM | WordSpillM | DoubleSpillM);
-  end else begin
-    assign SpillM = ValidAccess & (HalfSpillM | WordSpillM);
-    assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM);
-  end
       
   // align by shifting
   // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits

From 4149ae6c11aeb58198e8a8d89ace92810bfa82a0 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 23:05:47 -0600
Subject: [PATCH 33/48] More cleanup.

---
 src/lsu/align.sv | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 91eda1b8c..a3e2dadac 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -66,7 +66,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic              SelSpillM;
   logic              SpillSaveM;
   logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
-  logic              ValidMisalignedM, MisalignedM;
+  logic              MisalignedM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
   logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
 
@@ -92,6 +92,9 @@ module align import cvw::*;  #(parameter cvw_t P) (
   // 2) offset
   // 3) access location within the cacheline
   
+  assign ValidAccess = (|MemRWM);
+
+  // compute misalignement
   always_comb begin
     case (Funct3M[1:0]) 
       2'b00: AccessByteOffsetM = '0; // byte access
@@ -110,14 +113,8 @@ module align import cvw::*;  #(parameter cvw_t P) (
   end
   assign MisalignedM = ValidAccess & (AccessByteOffsetM != '0);
   assign SpillM = MisalignedM & PotentialSpillM;
-
-  // compute misalignement
-  assign ValidAccess = (|MemRWM);
       
-  // align by shifting
-  // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
-  assign ValidSpillM = SpillM & ~CacheBusHPWTStall;
-  assign ValidMisalignedM = MisalignedM & ~SelHPTW;
+  assign ValidSpillM = SpillM & ~CacheBusHPWTStall;   // Don't take the spill if there is a stall
   
   always_ff @(posedge clk)
     if (reset | FlushM)    CurrState <= #1 STATE_READY;
@@ -154,7 +151,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ShiftAmount = ValidMisalignedM ? 8 * AccessByteOffsetM : '0;
+  assign ShiftAmount = MisalignedM & ~SelHPTW ? {AccessByteOffsetM, 3'b0} : '0; // AND gate
   assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 

From d29b2b95f7b059063b912f2ec9754f5c6032038a Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 28 Nov 2023 23:28:50 -0600
Subject: [PATCH 34/48] Additional cleanup.

---
 src/lsu/align.sv | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index a3e2dadac..c618bb605 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -62,7 +62,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   statetype          CurrState, NextState;
   logic              ValidSpillM;
-  logic              SpillM;
   logic              SelSpillM;
   logic              SpillSaveM;
   logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
@@ -74,7 +73,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
   logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
-  logic                                        ValidAccess;
   logic                                        PotentialSpillM;
 
   /* verilator lint_off WIDTHEXPAND */
@@ -92,8 +90,6 @@ module align import cvw::*;  #(parameter cvw_t P) (
   // 2) offset
   // 3) access location within the cacheline
   
-  assign ValidAccess = (|MemRWM);
-
   // compute misalignement
   always_comb begin
     case (Funct3M[1:0]) 
@@ -111,10 +107,9 @@ module align import cvw::*;  #(parameter cvw_t P) (
       default: PotentialSpillM = '0;
     endcase
   end
-  assign MisalignedM = ValidAccess & (AccessByteOffsetM != '0);
-  assign SpillM = MisalignedM & PotentialSpillM;
+  assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != '0);
       
-  assign ValidSpillM = SpillM & ~CacheBusHPWTStall;   // Don't take the spill if there is a stall
+  assign ValidSpillM = MisalignedM & PotentialSpillM & ~CacheBusHPWTStall;   // Don't take the spill if there is a stall
   
   always_ff @(posedge clk)
     if (reset | FlushM)    CurrState <= #1 STATE_READY;

From 053b0946201921c928e1e6b5bcec34e9dfada1f9 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 12:26:18 -0600
Subject: [PATCH 35/48] Simpilified pmachecker for cmo.

---
 src/mmu/adrdecs.sv    | 12 ++++++------
 src/mmu/pmachecker.sv | 10 ++++------
 src/uncore/uncore.sv  |  2 +-
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index 922b98efb..576bb21b8 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -30,18 +30,18 @@
 
 module adrdecs import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0] PhysicalAddress,
-  input  logic                 AccessRW, AccessRX, AccessRWXZ, AccessRWC, AccessRXC,
+  input  logic                 AccessRW, AccessRX, AccessRWXC,
   input  logic [1:0]           Size,
   output logic [11:0]          SelRegions
 );
 
   localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
  // Determine which region of physical memory (if any) is being accessed
-  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRWC, Size, SUPPORTED_SIZE, SelRegions[11]);  
-  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRXC, Size, SUPPORTED_SIZE, SelRegions[10]);  
-  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[9]);  
-  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRXC, Size, SUPPORTED_SIZE, SelRegions[8]);
-  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWXZ, Size, SUPPORTED_SIZE, SelRegions[7]);
+  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]);  
+  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWXC, Size, SUPPORTED_SIZE, SelRegions[9]);  
+  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[8]);
+  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWXC, Size, SUPPORTED_SIZE, SelRegions[7]);
   adrdec #(P.PA_BITS) clintdec(PhysicalAddress, P.CLINT_BASE[P.PA_BITS-1:0], P.CLINT_RANGE[P.PA_BITS-1:0], P.CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[6]);
   adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[5]);
   adrdec #(P.PA_BITS) uartdec(PhysicalAddress, P.UART_BASE[P.PA_BITS-1:0], P.UART_RANGE[P.PA_BITS-1:0], P.UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[4]);
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index 016d4defe..f88479753 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -44,20 +44,18 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 );
 
   logic                        PMAAccessFault;
-  logic                        AccessRW, AccessRWXZ, AccessRX, AccessRWC, AccessRXC;
+  logic                        AccessRW, AccessRWXC, AccessRX;
   logic [11:0]                 SelRegions;
   logic                        AtomicAllowed;
   logic                        CacheableRegion, IdempotentRegion;
 
   // Determine what type of access is being made
   assign AccessRW  = ReadAccessM | WriteAccessM;
-  assign AccessRWC  = AccessRW | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
-  assign AccessRWXZ = ReadAccessM | WriteAccessM | ExecuteAccessF | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & (CMOp[3]));
+  assign AccessRWXC = ReadAccessM | WriteAccessM | ExecuteAccessF | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & (CMOp[3]));
   assign AccessRX  = ReadAccessM | ExecuteAccessF;
-  assign AccessRXC  = AccessRX | (P.ZICBOM_SUPPORTED & (|CMOp[2:0]));
 
   // Determine which region of physical memory (if any) is being accessed
-  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXZ, AccessRWC, AccessRXC, Size, SelRegions);
+  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXC, Size, SelRegions);
 
   // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
   assign CacheableRegion = SelRegions[9] | SelRegions[8] | SelRegions[7];  // exclusion-tag: unused-cachable
@@ -74,7 +72,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   assign SelTIM = SelRegions[11] | SelRegions[10]; // exclusion-tag: unused-idempotent
 
   // Detect access faults
-  assign PMAAccessFault          = (SelRegions[0]) & AccessRWXZ | AtomicAccessM & ~AtomicAllowed;  
+  assign PMAAccessFault          = (SelRegions[0]) & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
   assign PMAStoreAmoAccessFaultM = (WriteAccessM | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & CMOp[3]))   & PMAAccessFault;
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index ee93c2904..60d197f78 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -88,7 +88,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   // Determine which region of physical memory (if any) is being accessed
   // Use a trimmed down portion of the PMA checker - only the address decoders
   // Set access types to all 1 as don't cares because the MMU has already done access checking
-  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
+  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
   assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELEXTSDC, HSELSPI} = HSELRegions[11:1];

From 80336493f5f16329a03768f71564381bb5f9e126 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 15:20:49 -0600
Subject: [PATCH 36/48] Cleaned up redundant ZICBOM/Z_SUPPORTED.

---
 src/cache/cachefsm.sv | 24 ++++++++++++------------
 src/ieu/controller.sv | 10 ++++------
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index f7edfb733..b8f2130f7 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -94,7 +94,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
   assign AnyUpdateHit = (CacheRW[0]) & CacheHit;                            // exclusion-tag: icache storeAMO1
   assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
-  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit;
+  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit; // *** why does this not include dirty?
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
   assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
   assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
@@ -130,7 +130,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
                              else                                              NextState = STATE_READY;
       // exclusion-tag-start: icache case
       STATE_WRITEBACK:       if(CacheBusAck & ~(|CMOp[3:1]))                   NextState = STATE_FETCH;
-                             else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
+                             else if(CacheBusAck)                              NextState = STATE_READ_HOLD; // *** why not Ready?
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
       STATE_FLUSH:           if(LineDirty)                                     NextState = STATE_FLUSH_WRITEBACK;
@@ -154,24 +154,24 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
                       (CurrState == STATE_FLUSH_WRITEBACK);
   // write enables internal to cache
   assign SetValid = CurrState == STATE_WRITE_LINE | 
-                    (P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction) |
-                    (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]); 
-  assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
-                      (CurrState == STATE_WRITEBACK & CMOp[2] & CacheBusAck));
+                    (CurrState == STATE_READY & CMOZeroNoEviction) |
+                    (CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]); 
+  assign ClearValid = (CurrState == STATE_READY & CMOp[0]) |
+                      (CurrState == STATE_WRITEBACK & CMOp[2] & CacheBusAck);
   // coverage off -item e 1 -fecexprrow 8
   assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
                        (CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
-                      (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck);
+                      (CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck);
   // exclusion-tag-start: icache flushdirtycontrols
   assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) |         // exclusion-tag: icache SetDirty  
                     (CurrState == STATE_WRITE_LINE & (CacheRW[0])) |
-                    (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck));                    
+                    (CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck));                    
   assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) |   // exclusion-tag: icache ClearDirty
                       (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   // Flush and eviction controls
-                      (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
-  assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
-                  (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) | 
+                      CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck;
+  assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (CacheBusAck & CMOp[3]))) |
+                  (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~CacheHit))) | 
                   (CurrState == STATE_WRITE_LINE);
   assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
                         (CurrState == STATE_READY & AnyMiss & LineDirty);
@@ -194,7 +194,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
                          (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                          (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
-                         (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
+                         (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
 
   assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
                   (CurrState == STATE_FETCH) |
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index c9195132c..41be3941a 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -357,8 +357,10 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // Cache Management instructions
   always_comb begin
     CMOpD = 4'b0000; // default: not a cbo instruction
-    if ((P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) & CMOD) begin
+    if ((P.ZICBOZ_SUPPORTED) & CMOD) begin
       CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero
+    end
+    if ((P.ZICBOM_SUPPORTED) & CMOD) begin
       CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean
       CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush 
       CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval
@@ -425,9 +427,5 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // a cache cannot read or write immediately after a write
   // atomic operations are also detected as MemRWD[1]
   //assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
-  // *** RT: Modify for ZICBOZ
-  logic cboD, cboE;
-  assign cboE = (|CMOpE[2:0] & P.ZICBOM_SUPPORTED) | (CMOpE[3] & P.ZICBOZ_SUPPORTED);
-  assign cboD = (|CMOpD[2:0] & P.ZICBOM_SUPPORTED) | (CMOpD[3] & P.ZICBOZ_SUPPORTED);
-  assign StoreStallD = (MemRWE[0] | cboE) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | cboD));
+  assign StoreStallD = (MemRWE[0] | (|CMOpE)) & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED) | (|CMOpD)));
 endmodule

From fc04b6f7d87319ec8e601a6e9e1261bd84acc359 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 15:39:39 -0600
Subject: [PATCH 37/48] Removed redundant ZICBOM/Z_SUPPORTED from pmachecker.

---
 src/mmu/pmachecker.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index f88479753..3c23d3623 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -51,7 +51,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 
   // Determine what type of access is being made
   assign AccessRW  = ReadAccessM | WriteAccessM;
-  assign AccessRWXC = ReadAccessM | WriteAccessM | ExecuteAccessF | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & (CMOp[3]));
+  assign AccessRWXC = ReadAccessM | WriteAccessM | ExecuteAccessF | (|CMOp);
   assign AccessRX  = ReadAccessM | ExecuteAccessF;
 
   // Determine which region of physical memory (if any) is being accessed
@@ -75,5 +75,5 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   assign PMAAccessFault          = (SelRegions[0]) & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
   assign PMALoadAccessFaultM     = ReadAccessM    & PMAAccessFault;
-  assign PMAStoreAmoAccessFaultM = (WriteAccessM | (P.ZICBOM_SUPPORTED & (|CMOp[2:0])) | (P.ZICBOZ_SUPPORTED & CMOp[3]))   & PMAAccessFault;
+  assign PMAStoreAmoAccessFaultM = (WriteAccessM | (|CMOp))   & PMAAccessFault;
 endmodule

From f4e4aac8b5c78120e1f62a8fbc03470903b389ff Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 16:09:31 -0600
Subject: [PATCH 38/48] Added CMOp to pmp checker

---
 src/mmu/mmu.sv        | 2 +-
 src/mmu/pmpchecker.sv | 9 ++++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index 16016ac47..f9af52139 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -115,7 +115,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   if (P.PMP_ENTRIES > 0) begin : pmp
     pmpchecker #(P) pmpchecker(.PhysicalAddress, .PrivilegeModeW,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-      .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
+      .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .CMOp, 
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
   end else begin
     assign PMPInstrAccessFaultF     = 0;
diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
index 89c22c486..ddd7e72b0 100644
--- a/src/mmu/pmpchecker.sv
+++ b/src/mmu/pmpchecker.sv
@@ -42,6 +42,7 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   input  var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
   input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
   input  logic                     ExecuteAccessF, WriteAccessM, ReadAccessM,
+  input  logic [3:0]               CMOp,
   output logic                     PMPInstrAccessFaultF,
   output logic                     PMPLoadAccessFaultM,
   output logic                     PMPStoreAmoAccessFaultM
@@ -53,6 +54,8 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   logic [P.PMP_ENTRIES-1:0]        FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
   logic [P.PMP_ENTRIES-1:0]        L, X, W, R; // PMP matches and has flag set
   logic [P.PMP_ENTRIES-1:0]        PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
+  logic                            PMPCMOAccessFault, PMPCBOMAccessFault, PMPCBOZAccessFault;
+  
 
   if (P.PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
     pmpadrdec #(P) pmpadrdecs[P.PMP_ENTRIES-1:0](
@@ -69,7 +72,11 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
   assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode
 
+  assign PMPCBOMAccessFault     = EnforcePMP & (|CMOp[2:0]) & ~|((R|W) & FirstMatch) ;
+  assign PMPCBOZAccessFault     = EnforcePMP & CMOp[3] & ~|(W & FirstMatch) ;
+  assign PMPCMOAccessFault      = PMPCBOZAccessFault | PMPCBOMAccessFault;
+  
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
-  assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
+  assign PMPStoreAmoAccessFaultM  = (EnforcePMP & WriteAccessM   & ~|(W & FirstMatch))  | PMPCMOAccessFault;
   assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
  endmodule

From f11f88ac2b78bda02cf83a20d4f28346bdfc565d Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 16:20:43 -0600
Subject: [PATCH 39/48] Updates to tlb to check access permissions for cbo*

---
 src/mmu/mmu.sv            | 2 +-
 src/mmu/tlb/tlb.sv        | 3 ++-
 src/mmu/tlb/tlbcontrol.sv | 8 ++++++--
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index f9af52139..e8d87503c 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -85,7 +85,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
           .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
           .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
           .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
-          .PrivilegeModeW, .ReadAccess, .WriteAccess,
+          .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp,
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
           .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv
index 861e721b6..a5f95c70d 100644
--- a/src/mmu/tlb/tlb.sv
+++ b/src/mmu/tlb/tlb.sv
@@ -62,6 +62,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   input  logic [1:0]               PrivilegeModeW,   // Current privilege level of the processeor
   input  logic                     ReadAccess, 
   input  logic                     WriteAccess,
+  input  logic [3:0]               CMOp,
   input  logic                     DisableTranslation,
   input  logic [P.XLEN-1:0]        VAdr,             // address input before translation (could be physical or virtual)
   input  logic [P.XLEN-1:0]        PTE,              // page table entry to write
@@ -106,7 +107,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   assign VPN = VAdr[P.VPN_BITS+11:12];
 
   tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
-    .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
+    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush,
     .PTEAccessBits, .CAMHit, .Misaligned, 
     .TLBMiss, .TLBHit, .TLBPageFault, 
     .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 31312f767..dd296b892 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -35,6 +35,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic                     ENVCFG_HADE,        // HPTW A/D Update enable
   input  logic [1:0]               PrivilegeModeW,     // Current privilege level of the processeor
   input  logic                     ReadAccess, WriteAccess,
+  input  logic [3:0]               CMOp,
   input  logic                     DisableTranslation,
   input  logic                     TLBFlush,           // Invalidate all TLB entries
   input  logic [11:0]              PTEAccessBits,
@@ -67,7 +68,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeMode != P.M_MODE) & ~DisableTranslation; 
 
   // Determine whether TLB is being used
-  assign TLBAccess = ReadAccess | WriteAccess;
+  assign TLBAccess = ReadAccess | WriteAccess | (|CMOp);
 
   // Check that upper bits are legal (all 0s or all 1s)
   vm64check #(P) vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
@@ -98,6 +99,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
     assign InvalidAccess = ~PTE_X;
  end else begin:dtlb // Data TLB fault checking
     logic InvalidRead, InvalidWrite;
+    logic InvalidCBOM, InvalidCBOZ;
 
     // User mode may only load/store from user mode pages, and supervisor mode
     // may only access user mode pages when STATUS_SUM is low.
@@ -110,7 +112,9 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
     // Check for write error. Writes are invalid when the page's write bit is
     // low.
     assign InvalidWrite = WriteAccess & ~PTE_W;
-    assign InvalidAccess = InvalidRead | InvalidWrite;
+    assign InvalidCBOM = (|CMOp[2:0]) & (~PTE_W | (~PTE_R & (~STATUS_MXR | ~PTE_X)));
+    assign InvalidCBOZ = CMOp[3] & ~PTE_W;
+    assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ;
     assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D;
   end
 

From ab68a76e77834368d6f7d79ff47f35503584ee02 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 17:35:26 -0600
Subject: [PATCH 40/48] LineDirty is either the Victim Way or the Flush way
 dirty, but never the hitway dirty.  CBO instructions require hitway dirty. 
 However we cannot mux hitway dirty into LineDirty wihtout creating a
 combinational loop so we need a separate port.

---
 src/cache/cache.sv    | 9 +++++----
 src/cache/cachefsm.sv | 6 ++++--
 src/cache/cacheway.sv | 6 ++++--
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index c527f0eae..80f5559cf 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -79,8 +79,8 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic [LINELEN-1:0]            ReadDataLineWay [NUMWAYS-1:0];
   logic [NUMWAYS-1:0]            HitWay, ValidWay;
   logic                          CacheHit;
-  logic [NUMWAYS-1:0]            VictimWay, DirtyWay;
-  logic                          LineDirty;
+  logic [NUMWAYS-1:0]            VictimWay, DirtyWay, HitWayDirtyWay;
+  logic                          LineDirty, HitWayLineDirty;
   logic [TAGLEN-1:0]             TagWay [NUMWAYS-1:0];
   logic [TAGLEN-1:0]             Tag;
   logic [SETLEN-1:0]             FlushAdr, NextFlushAdr, FlushAdrP1;
@@ -116,7 +116,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
     .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
-    .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
+    .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitWayDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
@@ -128,6 +128,7 @@ module cache import cvw::*; #(parameter cvw_t P,
 
   assign CacheHit = |HitWay;
   assign LineDirty = |DirtyWay;
+  assign HitWayLineDirty = |HitWayDirtyWay;
 
   // ReadDataLineWay is a 2d array of cache line len by number of ways.
   // Need to OR together each way in a bitwise manner.
@@ -218,7 +219,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   
   cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
     .FlushStage, .CacheRW, .Stall,
-    .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, 
+    .CacheHit, .LineDirty, .HitWayLineDirty, .CacheStall, .CacheCommitted, 
     .CacheMiss, .CacheAccess, .SelAdr, .SelWay,
     .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush,
     .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index b8f2130f7..7136fe331 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -51,6 +51,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   // cache internals
   input  logic       CacheHit,          // Exactly 1 way hits
   input  logic       LineDirty,         // The selected line and way is dirty
+  input  logic       HitWayLineDirty,   // The cache hit way is dirty
   input  logic       FlushAdrFlag,      // On last set of a cache flush
   input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
   output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
@@ -94,7 +95,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
   assign AnyUpdateHit = (CacheRW[0]) & CacheHit;                            // exclusion-tag: icache storeAMO1
   assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
-  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit; // *** why does this not include dirty?
+  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitWayLineDirty;
+  //assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit; // *** why does this not include dirty?  FIXME
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
   assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
   assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
@@ -130,7 +132,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
                              else                                              NextState = STATE_READY;
       // exclusion-tag-start: icache case
       STATE_WRITEBACK:       if(CacheBusAck & ~(|CMOp[3:1]))                   NextState = STATE_FETCH;
-                             else if(CacheBusAck)                              NextState = STATE_READ_HOLD; // *** why not Ready?
+                             else if(CacheBusAck)                              NextState = STATE_READ_HOLD; // Read_hold lowers CacheStall
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
       STATE_FLUSH:           if(LineDirty)                                     NextState = STATE_FLUSH_WRITEBACK;
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 382d9ae6d..3f250d69a 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -51,7 +51,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
   output logic                        HitWay,         // This way hits
   output logic                        ValidWay,       // This way is valid
-  output logic                        DirtyWay,       // This way is dirty
+  output logic                        HitWayDirtyWay, // The hit way is dirty
+  output logic                        DirtyWay   ,    // The selected way is dirty
   output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
   localparam                          WORDSPERLINE = LINELEN/XLEN;
@@ -117,7 +118,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   // AND portion of distributed tag multiplexer
   assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
-  assign DirtyWay = SelDirty & Dirty & ValidWay;
+  assign HitWayDirtyWay = Dirty & ValidWay;
+  assign DirtyWay = SelDirty & HitWayDirtyWay;
   assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
 
   /////////////////////////////////////////////////////////////////////////////////////////////

From 025b04ae8b4d74dccfb3a30091bd2f826f472c70 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 29 Nov 2023 19:44:59 -0600
Subject: [PATCH 41/48] Minior cleanup.

---
 src/cache/cachefsm.sv | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 7136fe331..b2a2ebf5a 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -96,7 +96,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign AnyUpdateHit = (CacheRW[0]) & CacheHit;                            // exclusion-tag: icache storeAMO1
   assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
   assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitWayLineDirty;
-  //assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit; // *** why does this not include dirty?  FIXME
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
   assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
   assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;

From 71066cae12941fa3a314b4941cf3bbc83b57c085 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Thu, 30 Nov 2023 17:51:15 -0600
Subject: [PATCH 42/48] Modified FPGA Makefile to override  with relative path.
 FPGA boots now.

---
 fpga/generator/Makefile | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 9c7f557f3..7f70955be 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -6,17 +6,17 @@ dst := IP
 #export board := vcu118
 
 # vcu108
-#export XILINX_PART := xcvu095-ffva2104-2-e
-#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
-#export board := vcu108
+export XILINX_PART := xcvu095-ffva2104-2-e
+export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
+export board := vcu108
 
 # Arty A7
-export XILINX_PART := xc7a100tcsg324-1
-export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
-export board := ArtyA7
+# export XILINX_PART := xc7a100tcsg324-1
+# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
+# export board := ArtyA7
 
 # for Arty A7 and S7 boards
-all: FPGA_Arty
+all: FPGA_VCU
 
 # VCU 108 and VCU 118 boards
 #all: FPGA_VCU
@@ -70,6 +70,7 @@ PreProcessFiles:
 	sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
 	sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
 	sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
+	sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 
 $(dst)/%.log: %.tcl
 	mkdir -p IP

From edd4f902833f01a4244b8b579e660b2d929186eb Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Fri, 1 Dec 2023 13:21:33 -0600
Subject: [PATCH 43/48] Disassemble target now called with correct environment
 variables, allowing for downloading, building, disassembling, and installing
 in one make call.

---
 linux/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/linux/Makefile b/linux/Makefile
index cc19c7f2a..a78b85229 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -30,13 +30,13 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
 
 .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
 
-all: download Image disassemble install
+all: download Image install # disassemble install
 
 Image:
 	make -C $(BUILDROOT) --jobs
 	$(MAKE) generate
 	# TODO: Need to find a way to set the PATH for child processes.
-	# source ../setup.sh; $(MAKE) disassemble
+	bash -c "source ../setup.sh; $(MAKE) disassemble"
 
 install:
 	sudo rm -rf $(RISCV)/$(BUILDROOT)

From f99cb03b89afcf3bdfd4941a6b595f769e0e2761 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Fri, 1 Dec 2023 15:02:26 -0600
Subject: [PATCH 44/48] Changed Linux makefile to unset LD_LIBRARY_PATH before
 running buildroot. This allows custom setup.sh scripts to be used per user.

---
 linux/Makefile | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/linux/Makefile b/linux/Makefile
index a78b85229..9ef677d55 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -30,13 +30,11 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
 
 .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
 
-all: download Image install # disassemble install
+all: download Image disassemble install
 
 Image:
-	make -C $(BUILDROOT) --jobs
+	bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;"
 	$(MAKE) generate
-	# TODO: Need to find a way to set the PATH for child processes.
-	bash -c "source ../setup.sh; $(MAKE) disassemble"
 
 install:
 	sudo rm -rf $(RISCV)/$(BUILDROOT)

From 6de6e55acf5caf3533934bfbb6cde7236a1853f5 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 3 Dec 2023 10:38:17 -0600
Subject: [PATCH 45/48] Sarah updated top level figure.

---
 wallyriscvTopAll.png | Bin 38694 -> 64792 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/wallyriscvTopAll.png b/wallyriscvTopAll.png
index 4f675507f68af7b8a86e98a76e3e7b1315de46fb..a0d0e7ccee92d634e81e94744edc4576b3b7521e 100644
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From 3bef2a2361623882acc11674a2aa62ec0dab4e01 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 3 Dec 2023 15:49:06 -0600
Subject: [PATCH 46/48] Better name for cache signals.

---
 src/cache/cache.sv    | 10 +++++-----
 src/cache/cachefsm.sv |  4 ++--
 src/cache/cacheway.sv |  6 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index 80f5559cf..12a81028f 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -79,8 +79,8 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic [LINELEN-1:0]            ReadDataLineWay [NUMWAYS-1:0];
   logic [NUMWAYS-1:0]            HitWay, ValidWay;
   logic                          CacheHit;
-  logic [NUMWAYS-1:0]            VictimWay, DirtyWay, HitWayDirtyWay;
-  logic                          LineDirty, HitWayLineDirty;
+  logic [NUMWAYS-1:0]            VictimWay, DirtyWay, HitDirtyWay;
+  logic                          LineDirty, HitLineDirty;
   logic [TAGLEN-1:0]             TagWay [NUMWAYS-1:0];
   logic [TAGLEN-1:0]             Tag;
   logic [SETLEN-1:0]             FlushAdr, NextFlushAdr, FlushAdrP1;
@@ -116,7 +116,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
     .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
-    .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitWayDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
+    .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
@@ -128,7 +128,7 @@ module cache import cvw::*; #(parameter cvw_t P,
 
   assign CacheHit = |HitWay;
   assign LineDirty = |DirtyWay;
-  assign HitWayLineDirty = |HitWayDirtyWay;
+  assign HitLineDirty = |HitDirtyWay;
 
   // ReadDataLineWay is a 2d array of cache line len by number of ways.
   // Need to OR together each way in a bitwise manner.
@@ -219,7 +219,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   
   cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
     .FlushStage, .CacheRW, .Stall,
-    .CacheHit, .LineDirty, .HitWayLineDirty, .CacheStall, .CacheCommitted, 
+    .CacheHit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, 
     .CacheMiss, .CacheAccess, .SelAdr, .SelWay,
     .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush,
     .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index b2a2ebf5a..9428bf5b1 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -51,7 +51,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   // cache internals
   input  logic       CacheHit,          // Exactly 1 way hits
   input  logic       LineDirty,         // The selected line and way is dirty
-  input  logic       HitWayLineDirty,   // The cache hit way is dirty
+  input  logic       HitLineDirty,   // The cache hit way is dirty
   input  logic       FlushAdrFlag,      // On last set of a cache flush
   input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
   output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
@@ -95,7 +95,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
   assign AnyUpdateHit = (CacheRW[0]) & CacheHit;                            // exclusion-tag: icache storeAMO1
   assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
-  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitWayLineDirty;
+  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitLineDirty;
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
   assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
   assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 3f250d69a..82956fc29 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -51,7 +51,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
   output logic                        HitWay,         // This way hits
   output logic                        ValidWay,       // This way is valid
-  output logic                        HitWayDirtyWay, // The hit way is dirty
+  output logic                        HitDirtyWay, // The hit way is dirty
   output logic                        DirtyWay   ,    // The selected way is dirty
   output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
@@ -118,8 +118,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   // AND portion of distributed tag multiplexer
   assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
-  assign HitWayDirtyWay = Dirty & ValidWay;
-  assign DirtyWay = SelDirty & HitWayDirtyWay;
+  assign HitDirtyWay = Dirty & ValidWay;
+  assign DirtyWay = SelDirty & HitDirtyWay;
   assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
 
   /////////////////////////////////////////////////////////////////////////////////////////////

From 1ebc7aa95aba507c89bb1a22399e0412fc121fb0 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 3 Dec 2023 16:43:55 -0600
Subject: [PATCH 47/48] Optimized align.

---
 src/lsu/align.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index c618bb605..d3ca5ecc5 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -146,7 +146,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ShiftAmount = MisalignedM & ~SelHPTW ? {AccessByteOffsetM, 3'b0} : '0; // AND gate
+  assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate
   assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 

From 9348025727c3c2070e6f06116527649a0f291cd7 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 3 Dec 2023 18:19:00 -0600
Subject: [PATCH 48/48] Cachefsm simplifications.

---
 src/cache/cachefsm.sv | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 9428bf5b1..7c48e65dc 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -74,10 +74,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   logic              AnyUpdateHit, AnyHit;
   logic              AnyMiss;
   logic              FlushFlag;
-  logic              CMOWritebackHit;
   logic              CMOWriteback;
   logic              CMOZeroNoEviction;
-  logic              CMOZeroEviction;
 
   typedef enum logic [3:0]{STATE_READY, // hit states
                            // miss states
@@ -95,10 +93,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
   assign AnyUpdateHit = (CacheRW[0]) & CacheHit;                            // exclusion-tag: icache storeAMO1
   assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
-  assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitLineDirty;
   assign CMOZeroNoEviction = CMOp[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
-  assign CMOZeroEviction = CMOp[3] & LineDirty;   // (hit or miss) with writeback dirty line
-  assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
+  assign CMOWriteback = ((CMOp[1] | CMOp[2]) & CacheHit & HitLineDirty) | CMOp[3] & LineDirty;
   
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;