From b27447f552f45fa4e451aed2bfaca8ef549c40f7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 29 Nov 2024 15:41:36 -0800 Subject: [PATCH] Change addLockstepTestsByDir to addTestsByDir --- bin/regression-wally | 52 +++++++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index f53940d89..58e87b6a2 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -291,18 +291,35 @@ def addTests(tests, sim): configs.append(tc) -def addLockstepTestsByDir(dir, config, sim, fcovMode): - sim_logdir = WALLY+ "/sim/" + sim + "/logs/" - if (coverStr != ""): # use --fcov in place of --lockstep - cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config - else: - cmdPrefix="wsim --lockstep --sim " + sim + " " + config - if (os.path.isdir(dir)): +def addTestsByDir(dir, config, sim, lockstepMode=0): + if os.path.isdir(dir): + sim_logdir = WALLY+ "/sim/" + sim + "/logs/" + if coverStr == "--fcov": # use --fcov in place of --lockstep + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + gs="Mismatches : 0" + if ("cvw-arch-verif/tests" in dir and not "priv" in dir): + fileEnd = "ALL.elf" + else: + fileEnd = ".elf" + elif coverStr == "--ccov": + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + gs="Single Elf file tests are not signatured verified." + if ("cvw-arch-verif/tests" in dir and not "priv" in dir): + fileEnd = "ALL.elf" + else: + fileEnd = ".elf" + elif lockstepMode: + cmdPrefix="wsim --lockstep --sim " + sim + " " + config + gs="Mismatches : 0" + fileEnd = ".elf" + else: + cmdPrefix="wsim --sim " + sim + " " + config + gs="Single Elf file tests are not signatured verified." + fileEnd = ".elf" for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): for file in filenames: # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files - if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or - (file.endswith("ALL.elf") and fcovMode == 1)): + if file.endswith(fileEnd): fullfile = os.path.join(dirpath, file) fields = fullfile.rsplit('/', 3) if (fields[2] == "ref"): @@ -318,7 +335,7 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode): name=file, variant=config, cmd=cmdPrefix + " " + fullfile + " > " + sim_log, - grepstr="Mismatches : 0", + grepstr=gs, grepfile = sim_log) configs.append(tc) else: @@ -421,11 +438,10 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode if (args.fp): addTests(tests64gc_fp, coveragesim) elif (args.fcov): # run tests in lockstep in functional coverage mode - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1) - addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1) - #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim) + addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim) else: for sim in sims: @@ -437,9 +453,9 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0) + addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1) + addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.