AES cleanup

src/ieu/aes/aes64d.sv

@@ -32,13 +32,13 @@ module aes64d(
    output logic [63:0] result
 );
    
-   logic [63:0] 		    ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
+   logic [63:0] 		    ShiftRowsOut, SboxOut, MixcolIn, MixcolOut;
    
    // Apply inverse shiftrows to rs2 and rs1
-   aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
+   aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
    
    // Apply full word inverse substitution to lower doubleord of shiftrow out
-   aesinvsbox64 invsbox(ShiftRowOut,  SboxOut);
+   aesinvsbox64 invsbox(ShiftRowsOut,  SboxOut);
    
    mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
    

src/ieu/aes/aes64e.sv

@@ -34,17 +34,17 @@ module aes64e(
     output logic [63:0] result
 );
   
-    logic [63:0]  ShiftRowOut, SboxOut, MixcolOut;
+    logic [63:0]  ShiftRowsOut, SboxOut, MixcolOut;
                 
     // AES shiftrow unit
-    aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
+    aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
    
     // Apply substitution box to 2 lower words
     // Use the shared sbox in zknde64.sv for the first sbox
-    assign SboxEIn = ShiftRowOut[31:0];
+    assign SboxEIn = ShiftRowsOut[31:0];
     assign SboxOut[31:0] = Sbox0Out;
 
-    aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
+    aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
 
     // Apply MixColumns operations
     aesmixcolumns32 mw0(SboxOut[31:0],  MixcolOut[31:0]);

src/ieu/aes/aesinvshiftrows64.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aesinvshiftrow.sv
+// aesinvshiftrows64.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,9 +25,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvshiftrow64(
+module aesinvshiftrows64(
    input  logic [127:0] a, 
-   output logic [63:0] y
+   output logic [63:0]  y
 );
 
    assign y = {a[95:88],   a[119:112], a[15:8],    a[39:32],

src/ieu/aes/aesshiftrows64.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aesshiftrow.sv
+// aesshiftrows64.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesshiftrow64(
+module aesshiftrows64(
    input  logic [127:0] a, 
    output logic [63:0] y
 );

src/ieu/aes/aesshiftrows64.xv

@@ -0,0 +1,35 @@
+///////////////////////////////////////////
+// aesshiftrows64.sv
+//
+// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
+// Created: 20 February 2024
+//
+// Purpose: aesshiftrow for taking in first Data line
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module aesshiftrows64(
+   input  logic [127:0] a, 
+   output logic [63:0]  y
+);
+		    
+   assign y = {a[31:24],   a[119:112], a[79:72],   a[39:32],
+               a[127:120], a[87:80],   a[47:40],   a[7:0]};   
+endmodule