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More signal name cleanup in LSU.

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This commit is contained in:
Ross Thompson 2021-12-19 22:47:48 -06:00
parent 533c2f3556
commit b261b18aa8
1 changed files with 7 additions and 21 deletions
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28
wally-pipelined/src/lsu/lsu.sv
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@ -93,14 +93,11 @@ module lsu
logic DTLBPageFaultM; logic DTLBPageFaultM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
logic DTLBMissM; logic DTLBMissM;
logic DTLBWriteM; logic DTLBWriteM;
logic HPTWStall; logic HPTWStall;
logic [`PA_BITS-1:0] HPTWAdr; logic [`PA_BITS-1:0] HPTWAdr;
//logic [`PA_BITS-1:0] HPTWAdrM;
logic HPTWRead; logic HPTWRead;
logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoDCache;
logic [1:0] MemRWMtoLRSC; logic [1:0] MemRWMtoLRSC;
@ -121,7 +118,6 @@ module lsu
logic CommittedMfromDCache; logic CommittedMfromDCache;
logic PendingInterruptMtoDCache; logic PendingInterruptMtoDCache;
// logic FlushWtoDCache;
logic WalkerPageFaultM; logic WalkerPageFaultM;
logic AnyCPUReqM; logic AnyCPUReqM;
@ -251,21 +247,19 @@ module lsu
.PAdr(MemPAdrNoTranslate), .PAdr(MemPAdrNoTranslate),
.VAdr(IEUAdrM), .VAdr(IEUAdrM),
.Size(Funct3MtoDCache[1:0]), .Size(Funct3MtoDCache[1:0]),
.PTE(PTE), .PTE,
.PageTypeWriteVal(PageType), .PageTypeWriteVal(PageType),
.TLBWrite(DTLBWriteM), .TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .PhysicalAddress(MemPAdrM),
.TLBMiss(DTLBMissM), .TLBMiss(DTLBMissM),
.Cacheable(CacheableM), .Cacheable(CacheableM),
.Idempotent(), .Idempotent(), .AtomicAllowed(),
.AtomicAllowed(),
.TLBPageFault(DTLBPageFaultM), .TLBPageFault(DTLBPageFaultM),
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),
.WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]), .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
//.AtomicAccessM(AtomicMaskedM[1]),
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
@ -303,25 +297,17 @@ module lsu
// 3. wire pass-through // 3. wire pass-through
assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0]; assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
dcache dcache(.clk(clk), dcache dcache(.clk, .reset, .CPUBusy,
.reset(reset),
.CPUBusy(CPUBusy),
.MemRWM(MemRWMtoDCache), .MemRWM(MemRWMtoDCache),
.Funct3M(Funct3MtoDCache), .Funct3M(Funct3MtoDCache),
.Funct7M(Funct7M), .Funct7M, .FlushDCacheM,
.FlushDCacheM,
.AtomicM(AtomicMtoDCache), .AtomicM(AtomicMtoDCache),
.MemAdrE(MemAdrE_RENAME), .MemAdrE(MemAdrE_RENAME),
.MemPAdrM(MemPAdrM), .MemPAdrM,
.VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed. .VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed.
.WriteDataM(WriteDataM), .WriteDataM, .ReadDataM, .DCacheStall,
.ReadDataM(ReadDataM),
.DCacheStall(DCacheStall),
.CommittedM(CommittedMfromDCache), .CommittedM(CommittedMfromDCache),
.DCacheMiss, .DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest,
.DCacheAccess,
.ExceptionM(ExceptionM),
.IgnoreRequest,
.PendingInterruptM(PendingInterruptMtoDCache), .PendingInterruptM(PendingInterruptMtoDCache),
.CacheableM(CacheableMtoDCache), .CacheableM(CacheableMtoDCache),