From b2039e5b9a98c672fe1c01e3cc5a7f05f0017043 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 30 Mar 2021 14:21:45 -0500 Subject: [PATCH] Second update to divide that didn't get in for some silly git reason --- .../config/rv64imc/BTBPredictor.txt | 1024 +++++++++ .../config/rv64imc/twoBitPredictor.txt | 1024 +++++++++ .../config/rv64imc/wally-config.vh | 100 + .../config/rv64imc/wally-constants.vh | 31 + wally-pipelined/src/ieu/forward.sv | 15 +- wally-pipelined/src/ieu/ieu.sv | 46 +- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 1535 +++++++++++++ wally-pipelined/src/muldiv/div.sv~ | 1921 +++++++++++++++++ wally-pipelined/src/muldiv/div/divide4x32.sv | 312 +-- wally-pipelined/src/muldiv/div/divide4x64.sv | 598 +---- wally-pipelined/src/muldiv/div/int32div.do | 4 +- wally-pipelined/src/muldiv/div/int64div.do | 4 +- wally-pipelined/src/muldiv/div/iter32.do | 2 +- wally-pipelined/src/muldiv/div/iter64.do | 2 +- .../src/muldiv/div/{muxs.sv => mux_div.sv} | 0 .../src/muldiv/div/shifters_div.sv | 106 + .../div/{shifters.sv => shifters_div.sv~} | 0 .../src/muldiv/div/test_int32div.sv | 8 +- wally-pipelined/src/muldiv/muldiv.sv | 97 +- .../src/wally/wallypipelinedhart.sv | 17 +- .../testbench/testbench-imperas.sv | 2 +- 22 files changed, 5918 insertions(+), 932 deletions(-) create mode 100644 wally-pipelined/config/rv64imc/BTBPredictor.txt create mode 100644 wally-pipelined/config/rv64imc/twoBitPredictor.txt create mode 100644 wally-pipelined/config/rv64imc/wally-config.vh create mode 100644 wally-pipelined/config/rv64imc/wally-constants.vh create mode 100755 wally-pipelined/src/muldiv/div.sv create mode 100755 wally-pipelined/src/muldiv/div.sv~ rename wally-pipelined/src/muldiv/div/{muxs.sv => mux_div.sv} (100%) create mode 100644 wally-pipelined/src/muldiv/div/shifters_div.sv rename wally-pipelined/src/muldiv/div/{shifters.sv => shifters_div.sv~} (100%) diff --git a/wally-pipelined/config/rv64imc/BTBPredictor.txt b/wally-pipelined/config/rv64imc/BTBPredictor.txt new file mode 100644 index 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Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +//`define MISA (32'h00000105) +`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define COUNTERS 31 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Address space +`define RESET_VECTOR 64'h0000000080000000 + +// Bus Interface width +`define AHBW 64 + +// Peripheral Physiccal Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h0007FFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + +// Busybear special CSR config to match OVPSim +`define OVPSIM_CSR_CONFIG 0 + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ + +`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE diff --git a/wally-pipelined/config/rv64imc/wally-constants.vh b/wally-pipelined/config/rv64imc/wally-constants.vh new file mode 100644 index 000000000..55fb4e947 --- /dev/null +++ b/wally-pipelined/config/rv64imc/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv index 3f38004eb..dd79fcc7a 100644 --- a/wally-pipelined/src/ieu/forward.sv +++ b/wally-pipelined/src/ieu/forward.sv @@ -27,12 +27,13 @@ module forward( // Detect hazards - input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, - input logic MemReadE, MulDivE, CSRReadE, - input logic RegWriteM, RegWriteW, + input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, + input logic MemReadE, MulDivE, CSRReadE, + input logic RegWriteM, RegWriteW, + input logic DivDoneW, // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, - output logic LoadStallD, MulDivStallD, CSRRdStallD + output logic LoadStallD, MulDivStallD, CSRRdStallD ); always_comb begin @@ -48,8 +49,8 @@ module forward( end // Stall on dependent operations that finish in Mem Stage and can't bypass in time - assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE)); - assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)); // *** extend with stalls for divide - assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE)); + assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE)); + assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE&~DivDoneW; // *** extend with stalls for divide + assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE)); endmodule diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 85f029381..08d35fdfb 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -26,39 +26,40 @@ `include "wally-config.vh" module ieu ( - input logic clk, reset, + input logic clk, reset, // Decode Stage interface - input logic [31:0] InstrD, - input logic IllegalIEUInstrFaultD, - output logic IllegalBaseInstrFaultD, + input logic [31:0] InstrD, + input logic IllegalIEUInstrFaultD, + output logic IllegalBaseInstrFaultD, // Execute Stage interface - input logic [`XLEN-1:0] PCE, - input logic [`XLEN-1:0] PCLinkE, + input logic [`XLEN-1:0] PCE, + input logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCTargetE, - output logic MulDivE, W64E, - output logic [2:0] Funct3E, + output logic MulDivE, W64E, + output logic [2:0] Funct3E, output logic [`XLEN-1:0] SrcAE, SrcBE, // Memory stage interface - input logic DataMisalignedM, - input logic DataAccessFaultM, - input logic SquashSCW, - output logic [1:0] MemRWM, - output logic [1:0] AtomicM, + input logic DataMisalignedM, + input logic DataAccessFaultM, + input logic SquashSCW, + output logic [1:0] MemRWM, + output logic [1:0] AtomicM, output logic [`XLEN-1:0] MemAdrM, WriteDataM, output logic [`XLEN-1:0] SrcAM, - output logic [2:0] Funct3M, + output logic [2:0] Funct3M, // Writeback stage - input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, + input logic [`XLEN-1:0] CSRReadValW, ReadDataW, MulDivResultW, // input logic [`XLEN-1:0] PCLinkW, - output logic InstrValidW, + output logic InstrValidW, // hazards - input logic StallE, StallM, StallW, - input logic FlushE, FlushM, FlushW, - output logic LoadStallD, MulDivStallD, CSRRdStallD, - output logic PCSrcE, + input logic StallE, StallM, StallW, + input logic FlushE, FlushM, FlushW, + output logic LoadStallD, MulDivStallD, CSRRdStallD, + output logic PCSrcE, + input logic DivDoneW, - output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic CSRWritePendingDEM + output logic CSRReadM, CSRWriteM, PrivilegedM, + output logic CSRWritePendingDEM ); logic [2:0] ImmSrcD; @@ -78,5 +79,6 @@ module ieu ( controller c(.*); datapath dp(.*); forward fw(.*); + endmodule diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 35844fca0..d1b4fbf57 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -80,7 +80,7 @@ module ifu ( logic ITLBFlushF = '0; // logic ITLBWriteF = '0; tlb #(3) itlb(clk, reset, SATP_REGW, PrivilegeModeW, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, - ITLBInstrPAdrF, ITLBMissF, ITLBHitF); + ITLBInstrPAdrF, ITLBMissF, ITLBHitF); // branch predictor signals logic SelBPPredF; diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv new file mode 100755 index 000000000..2d515ce1d --- /dev/null +++ b/wally-pipelined/src/muldiv/div.sv @@ -0,0 +1,1535 @@ +/////////////////////////////////////////// +// mul.sv +// +// Written: James.Stine@okstate.edu 1 February 2021 +// Modified: +// +// Purpose: Integer Divide instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module div (Q, rem0, divdone, div0, N, D, clk, reset, start); + + input logic [63:0] N, D; + input logic clk; + input logic reset; + input logic start; + + output logic [63:0] Q; + output logic [63:0] rem0; + output logic div0; + output logic divdone; + + logic done; + logic enable; + logic state0; + logic V; + logic [7:0] Num; + logic [5:0] P, NumIter, RemShift; + logic [63:0] op1, op2, op1shift, Rem5; + logic [64:0] Qd, Rd, Qd2, Rd2; + logic [3:0] quotient; + logic otfzero; + logic shiftResult; + + // Divider goes the distance to 37 cycles + // (thanks the evil divisor for D = 0x1) + // but could theoretically be stopped when + // divdone is asserted. The enable signal + // turns off register storage thus invalidating + // any future cycles. + + // Shift D, if needed (for integer) + // needed to allow qst to be in range for integer + // division [1,2) and allow integer divide to work. + // + // The V or valid bit can be used to determine if D + // is 0 and thus a divide by 0 exception. This div0 + // exception is given to FSM to tell the operation to + // quit gracefully. + + // div0 produced output errors have untested results + // (it is assumed the OS would handle some output) + + lz64 p1 (P, V, D); + shifter_l64 p2 (op2, D, P); + assign op1 = N; + assign div0 = ~V; + + // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) + // v = 2 since \rho < 1 (add 4 to make sure its a ceil) + adder #(8) cpa1 ({2'b0, P}, + {5'h0, shiftResult, ~shiftResult, 1'b0}, + Num); + + // Determine whether need to add just Q/Rem + assign shiftResult = P[0]; + // div by 2 (ceil) + assign NumIter = Num[6:1]; + assign RemShift = P; + + // FSM to control integer divider + // assume inputs are postive edge and + // datapath (divider) is negative edge + fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, + start, div0, NumIter, ~clk, reset); + + flopr #(1) rega (~clk, reset, donev, done); + flopr #(1) regb (~clk, reset, divdonev, divdone); + flopr #(1) regc (~clk, reset, otfzerov, otfzero); + flopr #(1) regd (~clk, reset, enablev, enable); + flopr #(1) rege (~clk, reset, state0v, state0); + + // To obtain a correct remainder the last bit of the + // quotient has to be aligned with a radix-r boundary. + // Since the quotient is in the range 1/2 < q < 2 (one + // integer bit and m fractional bits), this is achieved by + // shifting N right by v+s so that (m+v+s) mod k = 0. And, + // the quotient has to be aligned to the integer position. + + // Used a Brent-Kung for no reason (just wanted prefix -- might + // have gotten away with a RCA) + + // Actual divider unit FIXME: r16 (jes) + divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + // Storage registers to hold contents stable + flopenr #(65) reg3 (clk, reset, enable, Rd, Rd2); + flopenr #(65) reg4 (clk, reset, enable, Qd, Qd2); + + // Probably not needed - just assigns results + assign Q = Qd2[63:0]; + assign Rem5 = Rd2[64:1]; + + // Adjust remainder by m (no need to adjust by + // n ln(r) + shifter_r64 p4 (rem0, Rem5, RemShift); + +endmodule // int32div + +module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + input logic [63:0] op1, op2; + input logic clk, state0; + input logic reset; + input logic enable; + input logic otfzero; + input logic shiftResult; + + output logic [64:0] rem0; + output logic [64:0] Q; + output logic [3:0] quotient; + + logic [67:0] Sum, Carry; + logic [64:0] Qstar; + logic [64:0] QMstar; + logic [7:0] qtotal; + logic [67:0] SumN, CarryN, SumN2, CarryN2; + logic [67:0] divi1, divi2, divi1c, divi2c, dive1; + logic [67:0] mdivi_temp, mdivi; + logic zero; + logic [1:0] qsel; + logic [1:0] Qin, QMin; + logic CshiftQ, CshiftQM; + logic [67:0] rem1, rem2, rem3; + logic [67:0] SumR, CarryR; + logic [64:0] Qt; + + // Create one's complement values of Divisor (for q*D) + assign divi1 = {3'h0, op2, 1'b0}; + assign divi2 = {2'h0, op2, 2'b0}; + assign divi1c = ~divi1; + assign divi2c = ~divi2; + // Shift x1 if not mod k + mux2 #(68) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); + + // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) + mux2 #(68) mx2 ({CarryN2[65:0], 2'h0}, 68'h0, state0, CarryN); + mux2 #(68) mx3 ({SumN2[65:0], 2'h0}, dive1, state0, SumN); + // Simplify QST + adder #(8) cpa1 (SumN[67:60], CarryN[67:60], qtotal); + // q = {+2, +1, -1, -2} else q = 0 + qst4 pd1 (qtotal[7:1], divi1[63:61], quotient); + assign ulp = quotient[2]|quotient[3]; + assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); + // Map to binary encoding + assign qsel[1] = quotient[3]|quotient[2]; + assign qsel[0] = quotient[3]|quotient[1]; + mux4 #(68) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); + mux2 #(68) mx5 (mdivi_temp, 68'h0, zero, mdivi); + csa #(68) csa1 (mdivi, SumN, {CarryN[67:1], ulp}, Sum, Carry); + // regs : save CSA + flopenr #(68) reg1 (clk, reset, enable, Sum, SumN2); + flopenr #(68) reg2 (clk, reset, enable, Carry, CarryN2); + // OTF + ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); + otf #(65) otf2 (Qin, QMin, CshiftQ, CshiftQM, clk, + otfzero, enable, Qstar, QMstar); + + // Correction and generation of Remainder + adder #(68) cpa2 (SumN2[67:0], CarryN2[67:0], rem1); + // Add back +D as correction + csa #(68) csa2 (CarryN2[67:0], SumN2[67:0], divi1, SumR, CarryR); + adder #(68) cpa3 (SumR, CarryR, rem2); + // Choose remainder (Rem or Rem+D) + mux2 #(68) mx6 (rem1, rem2, rem1[67], rem3); + // Choose correct Q or QM + mux2 #(65) mx7 (Qstar, QMstar, rem1[67], Qt); + // Final results + assign rem0 = rem3[64:0]; + assign Q = Qt; + +endmodule // divide4x64 + +module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); + + input logic [3:0] quot; + + output logic [1:0] Qin; + output logic [1:0] QMin; + output logic CshiftQ; + output logic CshiftQM; + + // Load/Store Control for OTF + assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); + assign Qin[0] = (quot[1]) | (quot[2]); + assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign QMin[0] = (quot[3]) | (quot[0]) | + (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign CshiftQ = (quot[1]) | (quot[0]); + assign CshiftQM = (quot[3]) | (quot[2]); + +endmodule + +// On-the-fly Conversion per Ercegovac/Lang + +module otf #(parameter WIDTH=8) + (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); + + input logic [1:0] Qin, QMin; + input logic CshiftQ, CshiftQM; + input logic clk; + input logic reset; + input logic enable; + + output logic [WIDTH-1:0] R2Q; + output logic [WIDTH-1:0] R1Q; + + logic [WIDTH-1:0] Qstar, QMstar; + logic [WIDTH-1:0] M1Q, M2Q; + + // QM + mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); + flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); + // Q + mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); + flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); + + assign Qstar = R2Q; + assign QMstar = R1Q; + +endmodule // otf8 + +module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; + +endmodule // adder + +module fa (input logic a, b, c, output logic sum, carry); + + assign sum = a^b^c; + assign carry = a&b|a&c|b&c; + +endmodule // fa + +module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, + output logic [WIDTH-1:0] sum, carry); + + logic [WIDTH:0] carry_temp; + genvar i; + generate + for (i=0;i B. LT and GT are both '0' if A = B. + +module magcompare2b (LT, GT, A, B); + + input logic [1:0] A; + input logic [1:0] B; + + output logic LT; + output logic GT; + + // Determine if A < B using a minimized sum-of-products expression + assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; + // Determine if A > B using a minimized sum-of-products expression + assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; + +endmodule // magcompare2b + +// J. E. Stine and M. J. Schulte, "A combined two's complement and +// floating-point comparator," 2005 IEEE International Symposium on +// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. +// doi: 10.1109/ISCAS.2005.1464531 + +module magcompare8 (LT, EQ, A, B); + + input logic [7:0] A; + input logic [7:0] B; + + logic [3:0] s; + logic [3:0] t; + logic [1:0] u; + logic [1:0] v; + logic GT; + //wire LT; + + output logic EQ; + output logic LT; + + magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); + magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); + magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); + magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); + + magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); + magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); + + magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); + + assign EQ = ~(GT | LT); + +endmodule // magcompare8 + +module shifter_l64 (Z, A, Shift); + + input logic [63:0] A; + input logic [5:0] Shift; + + logic [63:0] stage1; + logic [63:0] stage2; + logic [63:0] stage3; + logic [63:0] stage4; + logic [63:0] stage5; + logic [31:0] thirtytwozeros = 32'h0; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [63:0] Z; + + mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); + +endmodule // shifter_l64 + +module shifter_r64 (Z, A, Shift); + + input logic [63:0] A; + input logic [5:0] Shift; + + logic [63:0] stage1; + logic [63:0] stage2; + logic [63:0] stage3; + logic [63:0] stage4; + logic [63:0] stage5; + logic [31:0] thirtytwozeros = 32'h0; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [63:0] Z; + + mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); + +endmodule // shifter_r64 + +module shifter_l32 (Z, A, Shift); + + input logic [31:0] A; + input logic [4:0] Shift; + + logic [31:0] stage1; + logic [31:0] stage2; + logic [31:0] stage3; + logic [31:0] stage4; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [31:0] Z; + + mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); + +endmodule // shifter_l32 + +module shifter_r32 (Z, A, Shift); + + input logic [31:0] A; + input logic [4:0] Shift; + + logic [31:0] stage1; + logic [31:0] stage2; + logic [31:0] stage3; + logic [31:0] stage4; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [31:0] Z; + + mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); + +endmodule // shifter_r32 + diff --git a/wally-pipelined/src/muldiv/div.sv~ b/wally-pipelined/src/muldiv/div.sv~ new file mode 100755 index 000000000..0cb6b0554 --- /dev/null +++ b/wally-pipelined/src/muldiv/div.sv~ @@ -0,0 +1,1921 @@ +module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); + + input logic [63:0] N, D; + input logic clk; + input logic reset; + input logic start; + + output logic [63:0] Q; + output logic [63:0] rem0; + output logic div0; + output logic done; + output logic divdone; + + logic enable; + logic state0; + logic V; + logic [7:0] Num; + logic [5:0] P, NumIter, RemShift; + logic [63:0] op1, op2, op1shift, Rem5; + logic [64:0] Qd, Rd, Qd2, Rd2; + logic [3:0] quotient; + logic otfzero; + logic shiftResult; + + // Divider goes the distance to 37 cycles + // (thanks the evil divisor for D = 0x1) + // but could theoretically be stopped when + // divdone is asserted. The enable signal + // turns off register storage thus invalidating + // any future cycles. + + // Shift D, if needed (for integer) + // needed to allow qst to be in range for integer + // division [1,2) and allow integer divide to work. + // + // The V or valid bit can be used to determine if D + // is 0 and thus a divide by 0 exception. This div0 + // exception is given to FSM to tell the operation to + // quit gracefully. + + // div0 produced output errors have untested results + // (it is assumed the OS would handle some output) + + lz64 p1 (P, V, D); + shifter_l64 p2 (op2, D, P); + assign op1 = N; + assign div0 = ~V; + + // Brent-Kung adder chosen for the heck of it and + // since so small (maybe could have used a RCA) + + // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) + // v = 2 since \rho < 1 (add 4 to make sure its a ceil) + bk8 cpa1 (co1, Num, {2'b0, P}, + {5'h0, shiftResult, ~shiftResult, 1'b0}, 1'b0); + + // Determine whether need to add just Q/Rem + assign shiftResult = P[0]; + // div by 2 (ceil) + assign NumIter = Num[6:1]; + assign RemShift = P; + + // FSM to control integer divider + // assume inputs are postive edge and + // datapath (divider) is negative edge + fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, + start, div0, NumIter, ~clk, reset); + + flopr #(1) rega (~clk, reset, donev, done); + flopr #(1) regb (~clk, reset, divdonev, divdone); + flopr #(1) regc (~clk, reset, otfzerov, otfzero); + flopr #(1) regd (~clk, reset, enablev, enable); + flopr #(1) rege (~clk, reset, state0v, state0); + + // To obtain a correct remainder the last bit of the + // quotient has to be aligned with a radix-r boundary. + // Since the quotient is in the range 1/2 < q < 2 (one + // integer bit and m fractional bits), this is achieved by + // shifting N right by v+s so that (m+v+s) mod k = 0. And, + // the quotient has to be aligned to the integer position. + + // Used a Brent-Kung for no reason (just wanted prefix -- might + // have gotten away with a RCA) + + // Actual divider unit FIXME: r16 (jes) + divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + // Storage registers to hold contents stable + flopenr #(65) reg3 (clk, reset, enable, Rd, Rd2); + flopenr #(65) reg4 (clk, reset, enable, Qd, Qd2); + + // Probably not needed - just assigns results + assign Q = Qd2[63:0]; + assign Rem5 = Rd2[64:1]; + + // Adjust remainder by m (no need to adjust by + // n ln(r) + shifter_r64 p4 (rem0, Rem5, RemShift); + +endmodule // int32div + +module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + input logic [63:0] op1, op2; + input logic clk, state0; + input logic reset; + input logic enable; + input logic otfzero; + input logic shiftResult; + + output logic [64:0] rem0; + output logic [64:0] Q; + output logic [3:0] quotient; + + logic [67:0] Sum, Carry; + logic [64:0] Qstar; + logic [64:0] QMstar; + logic [7:0] qtotal; + logic [67:0] SumN, CarryN, SumN2, CarryN2; + logic [67:0] divi1, divi2, divi1c, divi2c, dive1; + logic [67:0] mdivi_temp, mdivi; + logic zero; + logic [1:0] qsel; + logic [1:0] Qin, QMin; + logic CshiftQ, CshiftQM; + logic [67:0] rem1, rem2, rem3; + logic [67:0] SumR, CarryR; + logic [64:0] Qt; + + // Create one's complement values of Divisor (for q*D) + assign divi1 = {3'h0, op2, 1'b0}; + assign divi2 = {2'h0, op2, 2'b0}; + assign divi1c = ~divi1; + assign divi2c = ~divi2; + // Shift x1 if not mod k + mux2 #(68) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); + + // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) + mux2 #(68) mx2 ({CarryN2[65:0], 2'h0}, 68'h0, state0, CarryN); + mux2 #(68) mx3 ({SumN2[65:0], 2'h0}, dive1, state0, SumN); + // Simplify QST + adder #(8) cpa1 (SumN[67:60], CarryN[67:60], qtotal); + // q = {+2, +1, -1, -2} else q = 0 + qst4 pd1 (qtotal[7:1], divi1[63:61], quotient); + assign ulp = quotient[2]|quotient[3]; + assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); + // Map to binary encoding + assign qsel[1] = quotient[3]|quotient[2]; + assign qsel[0] = quotient[3]|quotient[1]; + mux4 #(68) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); + mux2 #(68) mx5 (mdivi_temp, 68'h0, zero, mdivi); + csa #(68) csa1 (mdivi, SumN, {CarryN[67:1], ulp}, Sum, Carry); + // regs : save CSA + flopenr #(68) reg1 (clk, reset, enable, Sum, SumN2); + flopenr #(68) reg2 (clk, reset, enable, Carry, CarryN2); + // OTF + ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); + otf #(65) otf2 (Qin, QMin, CshiftQ, CshiftQM, clk, + otfzero, enable, Qstar, QMstar); + + // Correction and generation of Remainder + add68 cpa2 (cout1, rem1, SumN2[67:0], CarryN2[67:0], 1'b0); + // Add back +D as correction + csa #(68) csa2 (CarryN2[67:0], SumN2[67:0], divi1, SumR, CarryR); + add68 cpa3 (cout2, rem2, SumR, CarryR, 1'b0); + // Choose remainder (Rem or Rem+D) + mux2 #(68) mx6 (rem1, rem2, rem1[67], rem3); + // Choose correct Q or QM + mux2 #(65) mx7 (Qstar, QMstar, rem1[67], Qt); + // Final results + assign rem0 = rem3[64:0]; + assign Q = Qt; + +endmodule // divide4x64 + +module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); + + input logic [3:0] quot; + + output logic [1:0] Qin; + output logic [1:0] QMin; + output logic CshiftQ; + output logic CshiftQM; + + assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); + assign Qin[0] = (quot[1]) | (quot[2]); + assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign QMin[0] = (quot[3]) | (quot[0]) | + (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign CshiftQ = (quot[1]) | (quot[0]); + assign CshiftQM = (quot[3]) | (quot[2]); + + endmodule + +module otf #(parameter WIDTH=8) + (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); + + input logic [1:0] Qin, QMin; + input logic CshiftQ, CshiftQM; + input logic clk; + input logic reset; + input logic enable; + + output logic [WIDTH-1:0] R2Q; + output logic [WIDTH-1:0] R1Q; + + logic [WIDTH-1:0] Qstar, QMstar; + logic [WIDTH-1:0] M1Q, M2Q; + + // QM + mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); + flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); + // Q + mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); + flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); + + assign Qstar = R2Q; + assign QMstar = R1Q; + + endmodule // otf8 + + module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; + + endmodule // adder + + module fa (input logic a, b, c, output logic sum, carry); + + assign sum = a^b^c; + assign carry = a&b|a&c|b&c; + + endmodule // fa + + module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, + output logic [WIDTH-1:0] sum, carry); + + logic [WIDTH:0] carry_temp; + genvar i; + generate + for (i=0;i B. LT and GT are both '0' if A = B. + +module magcompare2b (LT, GT, A, B); + + input logic [1:0] A; + input logic [1:0] B; + + output logic LT; + output logic GT; + + // Determine if A < B using a minimized sum-of-products expression + assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; + // Determine if A > B using a minimized sum-of-products expression + assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; + +endmodule // magcompare2b + +// J. E. Stine and M. J. Schulte, "A combined two's complement and +// floating-point comparator," 2005 IEEE International Symposium on +// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. +// doi: 10.1109/ISCAS.2005.1464531 + +module magcompare8 (LT, EQ, A, B); + + input logic [7:0] A; + input logic [7:0] B; + + logic [3:0] s; + logic [3:0] t; + logic [1:0] u; + logic [1:0] v; + logic GT; + //wire LT; + + output logic EQ; + output logic LT; + + magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); + magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); + magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); + magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); + + magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); + magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); + + magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); + + assign EQ = ~(GT | LT); + +endmodule // magcompare8 diff --git a/wally-pipelined/src/muldiv/div/divide4x32.sv b/wally-pipelined/src/muldiv/div/divide4x32.sv index 9b0ac2b4c..c5c311701 100755 --- a/wally-pipelined/src/muldiv/div/divide4x32.sv +++ b/wally-pipelined/src/muldiv/div/divide4x32.sv @@ -50,8 +50,9 @@ module int32div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) // v = 2 since \rho < 1 (add 4 to make sure its a ceil) - bk6 cpa1 (co1, Num, {1'b0, P}, - {3'h0, shiftResult, ~shiftResult,1'b0}, 1'b0); + adder #(6) cpa1 ({1'b0, P}, + {3'h0, shiftResult, ~shiftResult,1'b0}, + Num); // Determine whether need to add just Q/Rem assign shiftResult = P[0]; @@ -160,10 +161,10 @@ module divide4x32 (Q, rem0, quotient, op1, op2, clk, reset, state0, otfzero, enable, Qstar, QMstar); // Correction and generation of Remainder - add36 cpa2 (cout1, rem1, SumN2[35:0], CarryN2[35:0], 1'b0); + adder #(36) cpa2 (SumN2[35:0], CarryN2[35:0], rem1); // Add back +D as correction csa #(36) csa2 (CarryN2[35:0], SumN2[35:0], divi1, SumR, CarryR); - add36 cpa3 (cout2, rem2, SumR, CarryR, 1'b0); + adder #(36) cpa3 (SumR, CarryR, rem2); // Choose remainder (Rem or Rem+D) mux2 #(36) mx6 (rem1, rem2, rem1[35], rem3); // Choose correct Q or QM @@ -349,306 +350,7 @@ module floprc #(parameter WIDTH = 8) endmodule // qst4 -// Ladner-Fischer Prefix Adder - -module add36 (cout, sum, a, b, cin); - - input logic [35:0] a, b; - input logic cin; - output logic [35:0] sum; - output logic cout; - - logic [36:0] p,g; - logic [35:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - - // prefix tree - ladner_fischer36 prefix_tree(c, p[35:0], g[35:0]); - - // post-computation - assign sum=p[36:1]^c; - assign cout=g[36]|(p[36]&c[35]); - -endmodule // add36 - -module ladner_fischer36 (c, p, g); - - input logic [35:0] p; - input logic [35:0] g; - - output logic [36:1] c; - - // parallel-prefix, Ladner-Fischer - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]}); - - black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]}); - black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]}); - black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]}); - black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]}); - black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]}); - black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]}); - black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]}); - black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]}); - - black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]}); - black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12}); - black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16}); - black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20}); - black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24}); - black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28}); - - black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8}); - black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8}); - black b_21_16 (G_21_16, P_21_16, {G_21_20,G_19_16}, {P_21_20,P_19_16}); - black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16}); - black b_29_24 (G_29_24, P_29_24, {G_29_28,G_27_24}, {P_29_28,P_27_24}); - black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24}); - - black b_37_32 (G_37_32, P_37_32, {G_37_36,G_35_32}, {P_37_36,P_35_32}); - black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32}); - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8); - grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8); - black b_25_16 (G_25_16, P_25_16, {G_25_24,G_23_16}, {P_25_24,P_23_16}); - black b_27_16 (G_27_16, P_27_16, {G_27_24,G_23_16}, {P_27_24,P_23_16}); - black b_29_16 (G_29_16, P_29_16, {G_29_24,G_23_16}, {P_29_24,P_23_16}); - black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16}); - - black b_41_32 (G_41_32, P_41_32, {G_41_40,G_39_32}, {P_41_40,P_39_32}); - black b_43_32 (G_43_32, P_43_32, {G_43_40,G_39_32}, {P_43_40,P_39_32}); - black b_45_32 (G_45_32, P_45_32, {G_45_40,G_39_32}, {P_45_40,P_39_32}); - black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32}); - - // Stage 5: Generates G/P pairs that span 16 bits - grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16); - grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16); - grey g_21_0 (G_21_0, {G_21_16,G_15_0}, P_21_16); - grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16); - grey g_25_0 (G_25_0, {G_25_16,G_15_0}, P_25_16); - grey g_27_0 (G_27_0, {G_27_16,G_15_0}, P_27_16); - grey g_29_0 (G_29_0, {G_29_16,G_15_0}, P_29_16); - grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16); - - black b_49_32 (G_49_32, P_49_32, {G_49_48,G_47_32}, {P_49_48,P_47_32}); - black b_51_32 (G_51_32, P_51_32, {G_51_48,G_47_32}, {P_51_48,P_47_32}); - black b_53_32 (G_53_32, P_53_32, {G_53_48,G_47_32}, {P_53_48,P_47_32}); - black b_55_32 (G_55_32, P_55_32, {G_55_48,G_47_32}, {P_55_48,P_47_32}); - black b_57_32 (G_57_32, P_57_32, {G_57_48,G_47_32}, {P_57_48,P_47_32}); - black b_59_32 (G_59_32, P_59_32, {G_59_48,G_47_32}, {P_59_48,P_47_32}); - black b_61_32 (G_61_32, P_61_32, {G_61_48,G_47_32}, {P_61_48,P_47_32}); - black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32}); - - // Stage 6: Generates G/P pairs that span 32 bits - grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32); - grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32); - grey g_37_0 (G_37_0, {G_37_32,G_31_0}, P_37_32); - grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32); - grey g_41_0 (G_41_0, {G_41_32,G_31_0}, P_41_32); - grey g_43_0 (G_43_0, {G_43_32,G_31_0}, P_43_32); - grey g_45_0 (G_45_0, {G_45_32,G_31_0}, P_45_32); - grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32); - - grey g_49_0 (G_49_0, {G_49_32,G_31_0}, P_49_32); - grey g_51_0 (G_51_0, {G_51_32,G_31_0}, P_51_32); - grey g_53_0 (G_53_0, {G_53_32,G_31_0}, P_53_32); - grey g_55_0 (G_55_0, {G_55_32,G_31_0}, P_55_32); - grey g_57_0 (G_57_0, {G_57_32,G_31_0}, P_57_32); - grey g_59_0 (G_59_0, {G_59_32,G_31_0}, P_59_32); - grey g_61_0 (G_61_0, {G_61_32,G_31_0}, P_61_32); - grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32); - - // Extra grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]); - grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]); - grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]); - grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]); - grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]); - grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]); - grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]); - grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]); - grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]); - grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]); - grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - assign c[15]=G_14_0; - assign c[16]=G_15_0; - assign c[17]=G_16_0; - - assign c[18]=G_17_0; - assign c[19]=G_18_0; - assign c[20]=G_19_0; - assign c[21]=G_20_0; - assign c[22]=G_21_0; - assign c[23]=G_22_0; - assign c[24]=G_23_0; - assign c[25]=G_24_0; - - assign c[26]=G_25_0; - assign c[27]=G_26_0; - assign c[28]=G_27_0; - assign c[29]=G_28_0; - assign c[30]=G_29_0; - assign c[31]=G_30_0; - assign c[32]=G_31_0; - assign c[33]=G_32_0; - - assign c[34]=G_33_0; - assign c[35]=G_34_0; - assign c[36]=G_35_0; - -endmodule // ladner_fischer36 - -// Brent-Kung Prefix Adder -module bk6 (cout, sum, a, b, cin); - - input logic [5:0] a, b; - input logic cin; - - output logic [5:0] sum; - output logic cout; - - logic [6:0] p,g; - logic [5:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - - // prefix tree - brent_kung prefix_tree(c, p[5:0], g[5:0]); - - // post-computation - assign sum=p[6:1]^c; - assign cout=g[6]|(p[6]&c[5]); - -endmodule // bk6 - -module brent_kung (c, p, g); - - input logic [5:0] p; - input logic [5:0] g; - - output logic [6:1] c; - - // parallel-prefix, Brent-Kung - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - - // Stage 3: Generates G/P pairs that span 4 bits - - // Stage 4: Generates G/P pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - -endmodule // brent_kung - -// Black cell -module black (gout, pout, gin, pin); - - input logic [1:0] gin, pin; - output logic gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule // black - -// Grey cell -module grey (gout, gin, pin); - - input logic [1:0] gin; - input logic pin; - output logic gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule // grey - -// reduced Black cell -module rblk (hout, iout, gin, pin); - - input logic [1:0] gin, pin; - output logic hout, iout; - - assign iout=pin[1]&pin[0]; - assign hout=gin[1]|gin[0]; - -endmodule - -// reduced Grey cell -module rgry (hout, gin); - - input logic [1:0] gin; - output logic hout; - - assign hout=gin[1]|gin[0]; - -endmodule // rgry - +// LZD module lz2 (P, V, B0, B1); input logic B0; @@ -754,6 +456,8 @@ module lz32 (ZP, ZV, B); endmodule // lz32 +// FSM Control for Integer Divider + module fsm32 (en, state0, done, divdone, otfzero, start, error, NumIter, clk, reset); diff --git a/wally-pipelined/src/muldiv/div/divide4x64.sv b/wally-pipelined/src/muldiv/div/divide4x64.sv index 0cb6b0554..2f56f0eb7 100755 --- a/wally-pipelined/src/muldiv/div/divide4x64.sv +++ b/wally-pipelined/src/muldiv/div/divide4x64.sv @@ -51,8 +51,9 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) // v = 2 since \rho < 1 (add 4 to make sure its a ceil) - bk8 cpa1 (co1, Num, {2'b0, P}, - {5'h0, shiftResult, ~shiftResult, 1'b0}, 1'b0); + adder #(8) cpa1 ({2'b0, P}, + {5'h0, shiftResult, ~shiftResult, 1'b0}, + Num); // Determine whether need to add just Q/Rem assign shiftResult = P[0]; @@ -71,7 +72,7 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); flopr #(1) regc (~clk, reset, otfzerov, otfzero); flopr #(1) regd (~clk, reset, enablev, enable); flopr #(1) rege (~clk, reset, state0v, state0); - + // To obtain a correct remainder the last bit of the // quotient has to be aligned with a radix-r boundary. // Since the quotient is in the range 1/2 < q < 2 (one @@ -161,10 +162,10 @@ module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, otfzero, enable, Qstar, QMstar); // Correction and generation of Remainder - add68 cpa2 (cout1, rem1, SumN2[67:0], CarryN2[67:0], 1'b0); + adder #(68) cpa2 (SumN2[67:0], CarryN2[67:0], rem1); // Add back +D as correction csa #(68) csa2 (CarryN2[67:0], SumN2[67:0], divi1, SumR, CarryR); - add68 cpa3 (cout2, rem2, SumR, CarryR, 1'b0); + adder #(68) cpa3 (SumR, CarryR, rem2); // Choose remainder (Rem or Rem+D) mux2 #(68) mx6 (rem1, rem2, rem1[67], rem3); // Choose correct Q or QM @@ -177,22 +178,25 @@ endmodule // divide4x64 module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); - input logic [3:0] quot; + input logic [3:0] quot; - output logic [1:0] Qin; - output logic [1:0] QMin; - output logic CshiftQ; - output logic CshiftQM; + output logic [1:0] Qin; + output logic [1:0] QMin; + output logic CshiftQ; + output logic CshiftQM; - assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); - assign Qin[0] = (quot[1]) | (quot[2]); - assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign QMin[0] = (quot[3]) | (quot[0]) | - (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign CshiftQ = (quot[1]) | (quot[0]); - assign CshiftQM = (quot[3]) | (quot[2]); + // Load/Store Control for OTF + assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); + assign Qin[0] = (quot[1]) | (quot[2]); + assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign QMin[0] = (quot[3]) | (quot[0]) | + (!quot[3]&!quot[2]&!quot[1]&!quot[0]); + assign CshiftQ = (quot[1]) | (quot[0]); + assign CshiftQM = (quot[3]) | (quot[2]); - endmodule +endmodule + +// On-the-fly Conversion per Ercegovac/Lang module otf #(parameter WIDTH=8) (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); @@ -219,44 +223,44 @@ module otf #(parameter WIDTH=8) assign Qstar = R2Q; assign QMstar = R1Q; - endmodule // otf8 +endmodule // otf8 - module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); +module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); - assign y = a + b; + assign y = a + b; - endmodule // adder +endmodule // adder - module fa (input logic a, b, c, output logic sum, carry); +module fa (input logic a, b, c, output logic sum, carry); - assign sum = a^b^c; - assign carry = a&b|a&c|b&c; + assign sum = a^b^c; + assign carry = a&b|a&c|b&c; - endmodule // fa +endmodule // fa - module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); +module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, + output logic [WIDTH-1:0] sum, carry); - logic [WIDTH:0] carry_temp; - genvar i; - generate - for (i=0;i