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Ross Thompson 2023-01-20 13:13:05 -06:00
parent f78bfc4940
commit b1f3bd566c
2 changed files with 17 additions and 9 deletions
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7
pipelined/src/cache/cacheway.sv vendored
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/////////////////////////////////////////// ///////////////////////////////////////////
// cacheway // cacheway
// //
// Written: ross1728@gmail.com July 07, 2021 // Written: Ross Thompson ross1728@gmail.com
// Implements the data, tag, valid, dirty, and replacement bits. // Created: 7 July 2021
// Modified: 20 January 2023
// //
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
// //
// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.12)
//
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University

19
pipelined/src/cache/subcachelineread.sv vendored
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@ -1,11 +1,14 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subcachelineread // subcachelineread
// //
// Written: Ross Thompson ross1728@gmail.com February 04, 2022 // Written: Ross Thompson ross1728@gmail.com
// Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. // Created: 4 February 2022
// Modified: 20 January 2023
// //
// Purpose: Controller for the dcache fsm // Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes.
// //
// Documentation: RISC-V System on Chip Design Chapter 7
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@ -26,10 +29,12 @@
`include "wally-config.vh" `include "wally-config.vh"
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( module subcachelineread #(parameter LINELEN, WORDLEN,
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, parameter MUXINTERVAL // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
input logic [LINELEN-1:0] ReadDataLine, )(
output logic [WORDLEN-1:0] ReadDataWord input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
); );
localparam WORDSPERLINE = LINELEN/MUXINTERVAL; localparam WORDSPERLINE = LINELEN/MUXINTERVAL;