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https://github.com/openhwgroup/cvw
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Removed ZForwardEnE and replaced with ZEnE.
Similar for YForwardEnE.
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@ -49,7 +49,6 @@ module fctrl (
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output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format
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output logic FDivStartE, IDivStartE, // Start division or squareroot
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output logic FDivStartE, IDivStartE, // Start division or squareroot
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output logic XEnE, YEnE, ZEnE,
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output logic XEnE, YEnE, ZEnE,
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output logic YEnForwardE, ZEnForwardE,
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output logic FWriteIntE, FCvtIntE, FWriteIntM, // Write to integer register
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output logic FWriteIntE, FCvtIntE, FWriteIntM, // Write to integer register
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output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
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output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
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output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
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output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
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@ -206,9 +205,9 @@ module fctrl (
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assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2]));
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assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2]));
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// load/class mv cvt
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// load/class mv cvt
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assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0]))));
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assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0]))));
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assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]);
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assign YEnForwardE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0]))));
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assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]);
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assign ZEnForwardE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&~OpCtrlE[2];
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// Final Res Sel:
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// Final Res Sel:
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// fp int
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// fp int
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@ -77,7 +77,6 @@ module fpu (
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input
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logic XEnE, YEnE, ZEnE;
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logic XEnE, YEnE, ZEnE;
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logic YEnForwardE, ZEnForwardE;
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// regfile signals
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// regfile signals
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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@ -168,7 +167,7 @@ module fpu (
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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.Funct3E, .MDUE, .InstrD,
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.Funct3E, .MDUE, .InstrD,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE,
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.reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
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.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
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.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
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.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E);
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.FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E);
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@ -198,7 +197,7 @@ module fpu (
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// Hazard unit for FPU
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// Hazard unit for FPU
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// - determines if any forwarding or stalls are needed
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// - determines if any forwarding or stalls are needed
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fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM,
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fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM,
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.XEnE, .YEnE(YEnForwardE), .ZEnE(ZEnForwardE), .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
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.XEnE, .YEnE, .ZEnE, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
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// forwarding muxs
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// forwarding muxs
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mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE);
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mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE);
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