diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 8efa454d9..cb70605c0 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -86,7 +86,7 @@ module hazard ( assign StallFCause = '0; assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; - assign StallMCause = WFIStallM & ~FlushMCause; + assign StallMCause = WFIStallM & ~FlushMCause; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 4cdce4989..b25c3b905 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -202,7 +202,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// assign CSRAdrM = InstrM[31:20]; - assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM; + assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM; assign NextEPCM = P.C_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index a0195f366..eb17b8d04 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -29,7 +29,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, - input logic StallM, + input logic StallM, StallW, FlushW, input logic [31:15] InstrM, // privileged instruction function field input logic PrivilegedM, // is this a privileged instruction (from IEU controller) input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction @@ -39,7 +39,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( output logic IllegalInstrFaultM, // Illegal instruction output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs output logic sretM, mretM, // return instructions - output logic wfiM, sfencevmaM // wfi / sfence.vma / sinval.vma instructions + output logic wfiM, wfiW, sfencevmaM // wfi / sfence.vma / sinval.vma instructions ); logic rs1zeroM; // rs1 field = 0 @@ -86,6 +86,8 @@ module privdec import cvw::*; #(parameter cvw_t P) ( // coverage on end else assign WFITimeoutM = 0; + flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); + /////////////////////////////////////////// // Extract exceptions by name and handle them /////////////////////////////////////////// diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index fff4af8b8..d777e0bf9 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -115,15 +115,17 @@ module privileged import cvw::*; #(parameter cvw_t P) ( logic ExceptionM; // Memory stage instruction caused a fault logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE + logic wfiW; + // track the current privilege level privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); // decode privileged instructions - privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:15]), + privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]), .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, - .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM); + .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM); // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, @@ -156,5 +158,5 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .mretM, .sretM, .PrivilegeModeW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, .CommittedF, - .TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM); + .TrapM, .RetM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM); endmodule diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index bcde634de..bfbbeb65f 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -33,7 +33,7 @@ module trap import cvw::*; #(parameter cvw_t P) ( input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources input logic mretM, sretM, // return instructions - input logic wfiM, // wait for interrupt instruction + input logic wfiM, wfiW, // wait for interrupt instruction input logic [1:0] PrivilegeModeW, // current privilege mode input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs input logic [15:0] MEDELEG_REGW, // exception delegation SR @@ -68,7 +68,8 @@ module trap import cvw::*; #(parameter cvw_t P) ( assign Committed = CommittedM | CommittedF; assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); assign ValidIntsM = {12{~Committed}} & EnabledIntsM; - assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. + assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. + // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage. assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);