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https://github.com/openhwgroup/cvw
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Merge pull request #350 from stineje/main
Minor tweak to fix vectors not working for fadd.
This commit is contained in:
Ross Thompson
GitHub
commit
b1203b5460
@ -2,7 +2,7 @@
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//
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// Written: me@KatherineParry.com, james.stine@okstate.edu
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//
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// Purpose: Testbench for Testfloat
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// Purpose: Testbench for UCB Testfloat on Wally
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -21,18 +21,21 @@
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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//`include "wally-config.vh"
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`include "config.vh"
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`include "tests-fp.vh"
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import cvw::*;
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module testbenchfp;
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// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
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// to run specific precisions (e.g., quad or all)
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parameter TEST="none";
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parameter TEST_SIZE="none";
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`include "parameter-defs.vh"
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// FIXME: needs cleaning of unused variables (jes)
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string Tests[]; // list of tests to be run
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logic [2:0] OpCtrl[]; // list of op controls
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logic [2:0] Unit[]; // list of units being tested
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@ -61,7 +64,8 @@ module testbenchfp;
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logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
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logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
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logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
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logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
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logic [4:0] CmpFlg; // Outputed flags
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logic AnsNaN, ResNaN, NaNGood;
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logic Xs, Ys, Zs; // sign of the inputs
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logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
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@ -114,8 +118,8 @@ module testbenchfp;
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logic [P.NE+1:0] QeM;
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logic [P.DIVb:0] QmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic ResMatch; // Check if result matches
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logic FlagMatch; // Check if flag matches
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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///////////////////////////////////////////////////////////////////////////////////////////////
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@ -139,6 +143,7 @@ module testbenchfp;
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// all - test all of the above
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initial begin
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// Information displayed for user on what is simulating
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$display("\nThe start of simulation...");
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$display("This simulation for TEST is %s", TEST);
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$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
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@ -618,7 +623,6 @@ module testbenchfp;
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end
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end
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end
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// check if nothing is being tested
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if (Tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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@ -644,7 +648,7 @@ module testbenchfp;
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string tt0;
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tt0 = $psprintf("%s", Tests[TestNum]);
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testname = {p, tt0};
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//$display("Here you are %s", testname);
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$display("Here you are %s", testname);
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$display("\n\nRunning %s vectors ", Tests[TestNum]);
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$readmemh(testname, TestVectors);
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// set the test index to 0
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@ -722,6 +726,7 @@ module testbenchfp;
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.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
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.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
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end
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if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
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fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
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.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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@ -836,13 +841,35 @@ module testbenchfp;
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OldFDivBusyE = FDivDoneE;
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// For FP division this adds extra clock cycles to make sure the
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// computation completes. 18 clocks cycles are utilize to handle
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// Quad, but this can be changed for each precision to go faster.
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// computation completes.
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always @(posedge clk) begin
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// Add extra clock cycles in beginning for fdivsqrt to adequate reset state
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if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
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// This allows specific number of clocks to allow each vector
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// to complete for division or square root. It is an
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// arbitrary value and can be changed, if needed.
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case (FmtVal)
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// QP
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4'b11: begin
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repeat (20)
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@(posedge clk);
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end
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// HP
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4'b10: begin
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repeat (14)
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@(posedge clk);
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end
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// DP
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4'b01: begin
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repeat (18)
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@(posedge clk);
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end
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// SP
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4'b00: begin
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repeat (16)
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@(posedge clk);
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end
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endcase // case (FmtVal)
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if (reset != 1'b1)
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VectorNum += 1; // increment the vector
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end
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@ -850,7 +877,6 @@ module testbenchfp;
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// check results on falling edge of clk
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always @(negedge clk) begin
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// check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
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// - the sign of the NaN does not matter for the opperations being tested
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// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
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@ -935,7 +961,8 @@ module testbenchfp;
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// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
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// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
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else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
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else if ((UnitVal === `CVTINTUNIT) &
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~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) |
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(WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) |
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(~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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@ -959,13 +986,11 @@ module testbenchfp;
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// increment the rounding mode or loop back to rne
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if (FrmNum < 4) FrmNum += 1;
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else FrmNum = 0;
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// if no more Tests - finish
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if (Tests[TestNum] === "") begin
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$display("\nAll Tests completed with %d errors\n", errors);
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$stop;
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end
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$display("Running %s vectors", Tests[TestNum]);
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end
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end
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@ -1000,18 +1025,17 @@ module readvectors (
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localparam Q_LEN = 32'd128;
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`include "parameter-defs.vh"
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logic XEn, YEn, ZEn;
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logic XEn;
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logic YEn;
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logic ZEn;
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logic FPUActive;
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// apply test vectors on rising edge of clk
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// Format of vectors Inputs(1/2/3)_AnsFlg
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always @(VectorNum) begin
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// Initial delay is given to allow vector to work for fdiv
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// otherwise it will fail on first vector - fix needed (jes)
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DivStart = 1'b0;
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#20;
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#1;
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AnsFlg = TestVector[4:0];
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DivStart = 1'b0;
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case (Unit)
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`FMAUNIT:
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case (Fmt)
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@ -1078,6 +1102,7 @@ module readvectors (
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if (OpCtrl[0])
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case (Fmt)
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2'b11: begin // quad
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#20;
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X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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if (~clk) #5;
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@ -1085,6 +1110,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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#20;
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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if (~clk) #5;
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@ -1092,6 +1118,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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#20;
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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if (~clk) #5;
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@ -1099,6 +1126,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b10: begin // half
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#20;
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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if (~clk) #5;
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@ -1109,6 +1137,7 @@ module readvectors (
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else
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case (Fmt)
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2'b11: begin // quad
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#20;
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X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
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Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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@ -1117,6 +1146,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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#20;
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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@ -1125,6 +1155,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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#20;
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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@ -1133,6 +1164,7 @@ module readvectors (
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DivStart = 1'b0;
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end
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2'b10: begin // half
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#20;
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
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Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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@ -1247,7 +1279,6 @@ module readvectors (
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endcase
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end
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endcase
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`CVTINTUNIT:
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case (Fmt)
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2'b11: begin // quad
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