mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
commit
b108e0a594
82
pipelined/src/cache/cachereplacementpolicy.sv
vendored
82
pipelined/src/cache/cachereplacementpolicy.sv
vendored
@ -56,9 +56,8 @@ module cachereplacementpolicy
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logic [NUMWAYS-2:0] cEn;
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logic [NUMWAYS-2:0] cEn;
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/* -----\/----- EXCLUDED -----\/-----
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// proposed generic solution
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// proposed generic solution
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/* -----\/----- EXCLUDED -----\/-----
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binencoder #(NUMWAYS) encoder(HitWay, HitWayEnc);
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binencoder #(NUMWAYS) encoder(HitWay, HitWayEnc);
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// bit duplication
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// bit duplication
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@ -70,11 +69,7 @@ module cachereplacementpolicy
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assign HitWayExpand[StartIndex : EndIndex] = {{DuplicationFactor}{HitWayEnc[row]}};
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assign HitWayExpand[StartIndex : EndIndex] = {{DuplicationFactor}{HitWayEnc[row]}};
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end
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end
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genvar r, a,s;
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genvar r, a,s;
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//localparam s = NUMWAYS-2;
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assign cEn[NUMWAYS-2] = '1;
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assign cEn[NUMWAYS-2] = '1;
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for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
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for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
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localparam p = NUMWAYS - s;
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localparam p = NUMWAYS - s;
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@ -86,75 +81,44 @@ module cachereplacementpolicy
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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end
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end
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, HitWayExpand, cEn, NewReplacement);
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mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, ~HitWayExpand, cEn, NewReplacement);
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always_ff @(posedge clk) begin
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if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
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if(ce) begin
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if (LRUWriteEn) begin
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ReplacementBits[RAdr] <= NewReplacement;
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LineReplacementBits <= #1 NewReplacement;
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end else begin
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LineReplacementBits <= #1 ReplacementBits[RAdr];
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end
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end
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end
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localparam HalfPoint = (2**$clog2(NUMWAYS)) / 2;
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logic [NUMWAYS-2:0] ivec;
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assign ivec[HalfPoint-1:0] = LineReplacementBits[HalfPoint-1:0];
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for(r = NUMWAYS-2; r >= HalfPoint; r--) begin
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end
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assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
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assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
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assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
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assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
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assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
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assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
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assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
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assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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// logic [NUMWAYS/2-1:0] rawEn [LOGNUMWAYS-1:0];
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for(r = LOGNUMWAYS-1; r >= 0; r--) begin
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localparam integer g = 2**(LOGNUMWAYS-r-1);
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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localparam s = s - 1;
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assign cEn[t0] = cEn[s] & ~HitWayEnc[r];
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assign cEn[t1] = cEn[s] & HitWayEnc[r];
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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s = s - 1;
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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always_comb begin
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for(r = LOGNUMWAYS-1; r > 0; r--) begin
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localparam g = 2**(LOGNUMWAYS-r-1);
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for(a = g-1; a > 0; a--) begin
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localparam t0 = s - 2**(g-1);
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localparam t1 = t0 - 1;
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s = s - 1;
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end
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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/* -----\/----- EXCLUDED -----\/-----
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genvar row2;
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logic [LOGNUMWAYS-1:0] indices [LOGNUMWAYS-1:0];
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integer jindex;
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always_comb begin
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rawEn[LOGNUMWAYS-1] = 1;
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for(jindex = 0; jindex < LOGNUMWAYS-1; jindex++) begin
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rawEn[jindex] = 0;
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rawEn[jindex][~(HitWayEnc>>(jindex+1))] = 1;
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//cEn[2**(LOGNUMWAYS-jindex)-1+jindex:0] = rawEn[jindex][2**(LOGNUMWAYS-jindex)-1:0];
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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// *** high priority to clean up
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// *** high priority to clean up
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/* -----\/----- EXCLUDED -----\/-----
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initial begin
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initial begin
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assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
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assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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// Replacement Bits: Register file
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// Replacement Bits: Register file
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// Needs to be resettable for simulation, but could omit reset for synthesis ***
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// Needs to be resettable for simulation, but could omit reset for synthesis ***
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@ -221,7 +221,7 @@ module ifu (
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy,
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icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy,
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.FetchBuffer, .CacheBusAck(ICacheBusAck),
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.FetchBuffer, .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusRW,
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.CacheBusRW,
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@ -238,7 +238,7 @@ module ifu (
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ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.HRDATA,
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.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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.Flush(TrapM), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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@ -257,7 +257,7 @@ module ifu (
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// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
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// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
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assign IFUHSIZE = 3'b010;
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assign IFUHSIZE = 3'b010;
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ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushW), .HRESETn(~reset), .HREADY(IFUHREADY),
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ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY),
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.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
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.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
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.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
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.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
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.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
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.CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
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@ -246,7 +246,7 @@ module wallypipelinedcore (
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lsu lsu(
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lsu lsu(
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.clk, .reset, .StallM, .FlushM, .StallW,
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.clk, .reset, .StallM, .FlushM, .StallW,
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.FlushW,
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.FlushW(TrapM),
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// CPU interface
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// CPU interface
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.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
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.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
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.AtomicM,
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.AtomicM,
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