From b06fda88ff2b9dbb36a2ab5b97c877e72c5e0d15 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 24 May 2021 12:37:16 -0500 Subject: [PATCH] Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). --- wally-pipelined/src/ifu/ifu.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 25fc478de..4272ea9a2 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -210,9 +210,10 @@ module ifu ( // the branch predictor needs a compact decoding of the instruction class. // *** consider adding in the alternate return address x5 for returns. assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5 - assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must link to ra or r5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // jump register, but not return - assign InstrClassD[1] = InstrD[6:0] == 7'h6F; // jump + + assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01; // return must return to ra or r5 + assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 4'h01 && (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return + assign InstrClassD[1] = InstrD[6:0] == 7'h6F && (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5 assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch // Misaligned PC logic