Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

pipelined/config/buildroot/wally-config.vh

@@ -129,6 +129,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 1

pipelined/config/fpga/wally-config.vh

@@ -137,6 +137,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 1
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 1

pipelined/config/rv32e/wally-config.vh

@@ -134,6 +134,7 @@
 `define BPRED_ENABLED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv32gc/wally-config.vh

@@ -132,6 +132,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv32ia/wally-config.vh

@@ -134,6 +134,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv32ic/wally-config.vh

@@ -132,6 +132,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64BP/wally-config.vh

@@ -135,6 +135,8 @@
 //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL"  or BPLOCALPAg or BPGSHARE
 `define TESTSBP 1
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64fp/wally-config.vh

@@ -133,6 +133,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64gc/wally-config.vh

@@ -135,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64ia/wally-config.vh

@@ -135,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64ic/wally-config.vh

@@ -135,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0

pipelined/src/ifu/gsharePredictor.sv

@@ -31,10 +31,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
-
 module gsharePredictor
-  #(parameter int k = 10
-    )
   (input logic             clk,
    input logic             reset,
    input logic             StallF, StallE,
@@ -52,8 +49,8 @@ module gsharePredictor
    input logic [1:0]       UpdateBPPredE
   
    );
-  logic [k+1:0]            GHR, GHRNext;
+  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
-  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
   logic                    PHTUpdateEN;
   logic                    BPClassWrongNonCFI;
   logic                    BPClassWrongCFI;
@@ -63,7 +60,7 @@ module gsharePredictor
 
   logic [6:0]              GHRMuxSel;
   logic                    GHRUpdateEN;
-  logic [k-1:0]            GHRLookup;
+  logic [`BPRED_SIZE-1:0]            GHRLookup;
 
   assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
   assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@@ -85,18 +82,18 @@ module gsharePredictor
   // hoping this created a AND-OR mux.
   always_comb begin
     case (GHRMuxSel) 
-      7'b000_0001: GHRNext = GHR[k-1+2:0];  // no change
+      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
-      7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
+      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
-      7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
+      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
-      7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
+      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
-      7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
+      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
-      7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
+      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
-      7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
+      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], BPPredF[1]}; // speculative update
-      default: GHRNext = GHR[k-1+2:0];
+      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
     endcase
   end
 
-  flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
+  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
            .reset(reset),
            .en((GHRUpdateEN)),
            .d(GHRNext),
@@ -105,21 +102,21 @@ module gsharePredictor
   // if actively updating the GHR at the time of prediction we want to us
   // GHRNext as the lookup rather than GHR.
 
-  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
+  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
-  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];  
+  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
   assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
   assign PHTUpdateEN = InstrClassE[0] & ~StallE;
 
-  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
+  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
   
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  SRAM2P1R1W #(k, 2) PHT(.clk(clk),
+  SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk),
     .reset(reset),
-    //.RA1(GHR[k-1:0]),
+    //.RA1(GHR[`BPRED_SIZE-1:0]),
-    .RA1(GHRLookup ^ PCNextF[k:1]),
+    .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
     .RD1(BPPredF),
     .REN1(~StallF),
-    .WA1(PHTUpdateAdr ^ PCE[k:1]),
+    .WA1(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
     .WD1(UpdateBPPredE),
     .WEN1(PHTUpdateEN),
     .BitWEN1(2'b11));

pipelined/src/uncore/gpio.sv

@@ -146,7 +146,7 @@ module gpio (
 
   // chip i/o
   // connect OUT to IN for loopback testing
-  if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
+  if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & output_en | (GPIOPinsIn  & input_en);
   else                     assign input0d = GPIOPinsIn  & input_en;
   flop #(32) sync1(HCLK,input0d,input1d);
   flop #(32) sync2(HCLK,input1d,input2d);

pipelined/testbench/tests.vh

@@ -1471,7 +1471,7 @@ string imperas32f[] = '{
 //    "rv64i_m/privilege/WALLY-SCAUSE", "002090",
 //    "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
 //    "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
-//    "rv64i_m/privilege/WALLY-trap-01", "0050a0",
+    "rv64i_m/privilege/WALLY-trap-01", "0050a0",
     "rv64i_m/privilege/WALLY-MIE-01", "0050a0",
     "rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
     "rv64i_m/privilege/WALLY-stvec-01", "0050a0",

synthDC/Makefile

@@ -24,9 +24,11 @@ export SAIFPOWER ?= 0
 CONFIGDIR ?= ${WALLY}/pipelined/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
+FREQS = 25 50 100 150 200 250 300 350 400
+k = 3 6 
 print:
+	echo $(k)
 	echo $(CONFIGFILESTRIM)
-	echo $(DIRS)
 
 default:
 	@echo "Basic synthesis procedure for Wally:"
@@ -39,24 +41,25 @@ rv%.log: rv%
 	echo $<
 
 
-DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic
+DIRS = rv32e rv32gc rv64ic rv32ic rv64gc
 # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
 # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig
-
+bpred:
+	@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+	@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
+	@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
 copy: 
 	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
 	@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
 	@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
 	@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
 	@$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
+	@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
+
 
 del:
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
+	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_*;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;)
 
 configs: $(DIRS)
 $(DIRS): 
@@ -76,21 +79,23 @@ $(DIRS):
 	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
 	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
 	
-	# No Virtual Memory 
-	rm -rf $(CONFIGDIR)/$@_noVirtMem
-	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem
-	sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh
-
 	#no muldiv
 	rm -rf $(CONFIGDIR)/$@_noMulDiv
-	cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv
+	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
 
+	#no priv
+	rm -rf $(CONFIGDIR)/$@_noPriv
+	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
+
+freqs: 
+	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky130 FREQ=$(freq) MAXCORES=1;)
 
 allsynth: $(CONFIGFILESTRIM)
 
 $(CONFIGFILESTRIM):
-	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1
+	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky130 FREQ=1000 MAXCORES=1
 
 
 synth:

synthDC/runSynth.sh

@@ -0,0 +1,4 @@
+rm -r runs/*
+make clean
+make freqs TECH=sky130
+python3 scripts/extractSummary.py

synthDC/scripts/extractSummary.py

@@ -0,0 +1,50 @@
+#!/usr/bin/python3
+# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
+import glob 
+import re
+import csv
+import linecache
+import os 
+
+
+def main():
+    data = []
+    curr_dir = os.path.dirname(os.path.abspath(__file__))
+    output_file = os.path.join(curr_dir,"..","Summary.csv")
+    runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep")
+    search_strings = [
+        "Critical Path Length:", "Cell Area:", "Overall Compile Time:",
+        "Critical Path Clk Period:", "Critical Path Slack:"
+    ]
+
+    for name in glob.glob(runs_dir):   
+        f = open(name, 'r')
+        trimName = re.search("wallypipelinedcore_(.*?)_2022",name).group(1)
+
+        output = {'Name':trimName}
+        num_lines = len(f.readlines())
+        curr_line_index = 0
+
+        while curr_line_index < num_lines:
+            line = linecache.getline(name, curr_line_index)
+            for search_string in search_strings:
+                if search_string in line:
+                    val = getVal(name,search_string,line,curr_line_index)
+                    output[search_string] = val
+            curr_line_index +=1 
+        data += [output]
+
+    with open(output_file, 'w') as csvfile:
+        writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings)
+        writer.writeheader()
+        writer.writerows(data)
+        
+def getVal(filename, search_string, line, line_index):
+    data = re.search(f"{search_string} *(.*?)\\n", line).group(1)
+    if data == '': #sometimes data is stored in two line
+        data = linecache.getline(filename, line_index+1).strip()
+    return data
+
+if __name__=="__main__":
+    main()
+                

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag

@@ -65,7 +65,7 @@ target_tests_nosim = \
     WALLY-PIE-stack-01 \
     WALLY-PIE-stack-s-01 \
     WALLY-trap-sret-01 \
-    #WALLY-trap-01 \
+    WALLY-trap-01 \
     # Have all 0's in references!
     #WALLY-MEPC \
     #WALLY-SEPC \

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output

@@ -1,5 +1,11 @@
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
 00000000
+00000000 # mcause from instruction addr misaligned fault
+00000000
+800003d2 # mtval of faulting instruction adress (0x800003d3)
+00000000 
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
 00000001 # mcause from an instruction access fault
 00000000
 00000000 # mtval of faulting instruction address (0x0)
@@ -14,13 +20,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003ec # mtval of breakpoint instruction adress (0x800003ec)
+80000404 # mtval of breakpoint instruction adress (0x80000404)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003f5 # mtval of misaligned address (0x800003f5)
+8000040d # mtval of misaligned address (0x8000040d)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -32,7 +38,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000411 # mtval of address with misaligned store instr (0x80000410)
+80000429 # mtval of address with misaligned store instr (0x80000429)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -60,7 +66,31 @@
 00000000
 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec01 # value to indicate successful vectoring on s soft interrupt 
+00000000
+00000001 # mcause value from s soft interrupt
+80000000
+00000000 # mtval for ssoft interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec03 # value to indicate successful vectoring on m soft interrupt 
+00000000
+00000003 # mcause value from m soft interrupt
+80000000
+00000000 # mtval for msoft interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec05 # value to indicate successful vectoring on s time interrupt 
+00000000
+00000005 # mcause value from s time interrupt
+80000000
+00000000 # mtval for stime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec07 # value to indicate successful vectoring on m time interrupt 
 00000000
 00000007 # mcause value from m time interrupt
 80000000
@@ -68,15 +98,15 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec09 # value to indicate successful vectoring on s ext interrupt 
 00000000
-00000001 # mcause value from m soft interrupt
+00000009 # mcause value from s ext interrupt
 80000000
-00000000 # mtval for msoft interrupt (0x0)
+00000000 # mtval for sext interrupt (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec0b # value to indicate successful vectoring on m ext interrupt 
 00000000
 0000000b # mcause value from m ext interrupt
 80000000
@@ -84,11 +114,17 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
-00000000
+ffffffff
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000
-00000001 # Test 5.3.1.4: mcause from an instruction access fault
+00000000 # mcause from instruction addr misaligned fault
+00000000
+800003d2 # mtval of faulting instruction adress (0x800003d3)
+00000000 
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+00000001 # mcause from an instruction access fault
 00000000
 00000000 # mtval of faulting instruction address (0x0)
 00000000
@@ -102,13 +138,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003ec # mtval of breakpoint instruction adress (0x800003ec)
+80000404 # mtval of breakpoint instruction adress (0x80000404)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003f5 # mtval of misaligned address (0x800003f5)
+8000040d # mtval of misaligned address (0x8000040d)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -120,7 +156,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000411 # mtval of address with misaligned store instr (0x80000410)
+80000429 # mtval of address with misaligned store instr (0x80000429)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -136,23 +172,23 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec03 # value to indicate successful vectoring on m soft interrupt 
 00000000
-00000007 # mcause value from  time interrupt
+00000003 # mcause value from m soft interrupt
-80000000
-00000000 # mtval for mtime interrupt (0x0)
-00000000
-00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
-00000000
-000007ec # value to indicate a vectored interrupts
-00000000
-00000001 # mcause value from m soft interrupt
 80000000
 00000000 # mtval for msoft interrupt (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec07 # value to indicate successful vectoring on m time interrupt 
+00000000
+00000007 # mcause value from m time interrupt
+80000000
+00000000 # mtval for mtime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec0b # value to indicate successful vectoring on m ext interrupt 
 00000000
 0000000b # mcause value from m ext interrupt
 80000000
@@ -978,97 +1014,3 @@ deadbeef
 deadbeef
 deadbeef
 deadbeef
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -157,17 +157,17 @@ cause_s_soft_interrupt:
 cause_m_ext_interrupt:
     # ========== Configure PLIC ==========
     # m priority threshold = 0
-    li t0, 0xC200000
+    li x28, 0xC200000
-    li t1, 0
+    li x29, 0
-    sw t1, 0(t0)
+    sw x29, 0(x28)
     # source 3 (GPIO) priority = 1
-    li t0, 0xC000000
+    li x28, 0xC000000
-    li t1, 1
+    li x29, 1
-    sw t1, 0x0C(t0)
+    sw x29, 0x0C(x28)
-    # enable source 3
+    # enable source 3 in M Mode
-    li t0, 0x0C002000
+    li x28, 0x0C002000
-    li t1, 0b1000 
+    li x29, 0b1000 
-    sw t1, 0(t0)
+    sw x29, 0(x28)
 
     li x28, 0x10060000 // load base GPIO memory location
     li x29, 0x1
@@ -178,7 +178,7 @@ cause_m_ext_interrupt:
     sw x0, 0x2C(x28) // clear high_ip
     sw x0, 0x34(x28) // clear low_ip
 
-    sw x29, 0x28(x28)  // set first to interrupt on a rising value
+    sw x29, 0x28(x28)  // set first pin to interrupt on a rising value
     sw x29, 0x0C(x28)  // write a 1 to the first output pin (cause interrupt)
 m_ext_loop:
     wfi
@@ -189,21 +189,21 @@ m_ext_loop:
 cause_s_ext_interrupt_GPIO:
     # ========== Configure PLIC ==========
     # s priority threshold = 0
-    li t0, 0xC201000
+    li x28, 0xC201000
-    li t1, 0
+    li x29, 0
-    sw t1, 0(t0)
+    sw x29, 0(x28)
     # m priority threshold = 7
-    li t0, 0xC200000
+    li x28, 0xC200000
-    li t1, 7
+    li x29, 7
-    sw t1, 0(t0)
+    sw x29, 0(x28)
     # source 3 (GPIO) priority = 1
-    li t0, 0xC000000
+    li x28, 0xC000000
-    li t1, 1
+    li x29, 1
-    sw t1, 0x0C(t0)
+    sw x29, 0x0C(x28)
-    # enable source 3
+    # enable source 3 in S mode
-    li t0, 0x0C002000
+    li x28, 0x0C002080
-    li t1, 0b1000 
+    li x29, 0b1000 
-    sw t1, 0(t0)
+    sw x29, 0(x28)
 
     li x28, 0x10060000 // load base GPIO memory location
     li x29, 0x1
@@ -214,7 +214,7 @@ cause_s_ext_interrupt_GPIO:
     sw x0, 0x2C(x28) // clear high_ip
     sw x0, 0x34(x28) // clear low_ip
 
-    sw x29, 0x28(x28)  // set first to interrupt on a rising value
+    sw x29, 0x28(x28)  // set first pin to interrupt on a rising value
     sw x29, 0x0C(x28)  // write a 1 to the first output pin (cause interrupt)
 s_ext_loop:
     wfi
@@ -224,7 +224,7 @@ s_ext_loop:
 
 cause_s_ext_interrupt_IP:
     li x28, 0x200
-    csrs mip, x28 // set supervisor external interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
+    csrs mip, x28 // set supervisor external interrupt pending.
     ret
 
 end_trap_triggers:
@@ -521,18 +521,19 @@ soft_interrupt_\MODE\():
     la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
     sw x0, 0(x5)
 
-    csrci sip, 0x2 // clear supervisor software interrupt pending bit 
+    csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit 
     ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
     // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
     //  This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
     j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
 
-
 time_interrupt_\MODE\():
     la x5, 0x02004000    // MTIMECMP register in CLINT
     li x7, 0xFFFFFFFF
     sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
     
+    li x5, 0x20
+    csrc \MODE\()ip, x5
     ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
     j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
 
@@ -543,18 +544,26 @@ ext_interrupt_\MODE\():
 
     # reset PLIC to turn off external interrupts
     # priority threshold = 7
-    li t0, 0xC200000
+    li x28, 0xC200000
-    li t1, 0x7
+    li x5, 0x7
-    sw t1, 0(t0)
+    sw x5, 0(x28)
     # source 3 (GPIO) priority = 0
-    li t0, 0xC000000
+    li x28, 0xC000000
-    li t1, 0
+    li x5, 0
-    sw t1, 0x0C(t0)
+    sw x5, 0x0C(x28)
     # disable source 3
-    li t0, 0x0C002000
+    li x28, 0x0C002000
-    li t1, 0b0000 
+    li x5, 0b0000
-    sw t1, 0(t0)
+    sw x5, 0(x28)
-    j trapreturn_\MODE\()
+
+    li x5, 0x200
+    csrc \MODE\()ip, x5
+
+    ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
+    j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
+
+
+
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S

@@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
 
 // test 5.3.1.4 Basic trap tests 
 
-// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_addr_misaligned
 jal cause_instr_access
 jal cause_illegal_instr
 jal cause_breakpnt
@@ -47,16 +47,23 @@ GOTO_U_MODE // Causes M mode ecall
 GOTO_S_MODE // Causes U mode ecall
 GOTO_M_MODE // Causes S mode ecall
 
-jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+
-jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_s_soft_interrupt 
-jal cause_ext_interrupt
+jal cause_m_soft_interrupt
+jal cause_s_time_interrupt
+jal cause_m_time_interrupt
+//jal cause_s_ext_interrupt_GPIO
+jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
+jal cause_m_ext_interrupt
+
+
 
 // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
 
 WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
 WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 
-// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_addr_misaligned
 jal cause_instr_access
 jal cause_illegal_instr
 jal cause_breakpnt
@@ -66,9 +73,14 @@ jal cause_store_addr_misaligned
 jal cause_store_acc
 jal cause_ecall // M mode ecall
 
-jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
-jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_m_soft_interrupt
-jal cause_ext_interrupt
+jal cause_s_time_interrupt
+jal cause_m_time_interrupt
+//jal cause_s_ext_interrupt_GPIO
+jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
+jal cause_m_ext_interrupt
+
 
 END_TESTS