From b04e00d1969e823e51acf18cb9319ea86b4fde40 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 9 Sep 2021 15:08:10 -0500
Subject: [PATCH] Third attempt at fixing the write enables for the icache
cacheway.
---
wally-pipelined/src/cache/icache.sv | 2 +-
wally-pipelined/src/uncore/uncore.sv | 14 ++-
.../src/wally/wallypipelinedsoc.sv | 38 ++++---
.../src/wally/wallypipelinedsocwrapper.v | 101 ++++++++++++++++++
4 files changed, 133 insertions(+), 22 deletions(-)
create mode 100644 wally-pipelined/src/wally/wallypipelinedsocwrapper.v
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 10f077c7a..4123475ab 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -142,7 +142,7 @@ module icache
.RAdr(RAdr),
.PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable),
- .WriteWordEnable({NUMWAYS{1'b1}}),
+ .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
.TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable),
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index 78a89b02d..e6f5d15c5 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -43,6 +43,7 @@ module uncore (
input logic HREADYEXT, HRESPEXT,
output logic [`AHBW-1:0] HRDATA,
output logic HREADY, HRESP,
+ output logic HSELEXT,
// delayed signals
input logic [2:0] HADDRD,
input logic [3:0] HSIZED,
@@ -81,12 +82,14 @@ module uncore (
// unswizzle HSEL signals
assign {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC} = HSELRegions[5:0];
+ assign HSELEXT = HSELRegions[4];
+
// subword accesses: converts HWDATAIN to HWDATA
subwordwrite sww(.*);
generate
// tightly integrated memory
- dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
+ //dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
if (`BOOTTIM_SUPPORTED) begin : bootdtim
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
end
@@ -119,19 +122,22 @@ module uncore (
// mux could also include external memory
// AHB Read Multiplexer
- assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) |
+ //assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) |
+ assign HRDATA = ({`XLEN{HSELTimD}} & HRDATAEXT) |
({`XLEN{HSELCLINTD}} & HREADCLINT) |
({`XLEN{HSELPLICD}} & HREADPLIC) |
({`XLEN{HSELGPIOD}} & HREADGPIO) |
({`XLEN{HSELBootTimD}} & HREADBootTim) |
({`XLEN{HSELUARTD}} & HREADUART);
- assign HRESP = HSELTimD & HRESPTim |
+ //assign HRESP = HSELTimD & HRESPTim |
+ assign HRESP = HSELTimD & HRESPEXT |
HSELCLINTD & HRESPCLINT |
HSELPLICD & HRESPPLIC |
HSELGPIOD & HRESPGPIO |
HSELBootTimD & HRESPBootTim |
HSELUARTD & HRESPUART;
- assign HREADY = HSELTimD & HREADYTim |
+ //assign HREADY = HSELTimD & HREADYTim |
+ assign HREADY = HSELTimD & HREADYEXT |
HSELCLINTD & HREADYCLINT |
HSELPLICD & HREADYPLIC |
HSELGPIOD & HREADYGPIO |
diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index c85f5d4f4..c1ae3c02e 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -32,26 +32,28 @@
`include "wally-config.vh"
module wallypipelinedsoc (
- input logic clk, reset,
+ input logic clk, reset,
// AHB Lite Interface
// inputs from external memory
- input logic [`AHBW-1:0] HRDATAEXT,
- input logic HREADYEXT, HRESPEXT,
+ input logic [`AHBW-1:0] HRDATAEXT,
+ input logic HREADYEXT, HRESPEXT,
+ output logic HSELEXT,
// outputs to external memory, shared with uncore memory
- output logic HCLK, HRESETn,
- output logic [31:0] HADDR,
+ output logic HCLK, HRESETn,
+ output logic [31:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
- output logic HWRITE,
- output logic [2:0] HSIZE,
- output logic [2:0] HBURST,
- output logic [3:0] HPROT,
- output logic [1:0] HTRANS,
- output logic HMASTLOCK,
+ output logic HWRITE,
+ output logic [2:0] HSIZE,
+ output logic [2:0] HBURST,
+ output logic [3:0] HPROT,
+ output logic [1:0] HTRANS,
+ output logic HMASTLOCK,
+ output logic HREADY,
// I/O Interface
- input logic [31:0] GPIOPinsIn,
- output logic [31:0] GPIOPinsOut, GPIOPinsEn,
- input logic UARTSin,
- output logic UARTSout
+ input logic [31:0] GPIOPinsIn,
+ output logic [31:0] GPIOPinsOut, GPIOPinsEn,
+ input logic UARTSin,
+ output logic UARTSout
);
// to instruction memory *** remove later
@@ -59,7 +61,7 @@ module wallypipelinedsoc (
// Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
- logic HREADY, HRESP;
+ //logic HREADY, HRESP;
logic [5:0] HSELRegions;
logic InstrAccessFaultF, DataAccessFaultM;
logic TimerIntM, SwIntM; // from CLINT
@@ -70,6 +72,8 @@ module wallypipelinedsoc (
logic HWRITED;
logic [15:0] rd2; // bogus, delete when real multicycle fetch works
logic [31:0] InstrF;
+ logic HRESP;
+
// instantiate processor and memories
wallypipelinedhart hart(.*);
@@ -77,4 +81,4 @@ module wallypipelinedsoc (
// instructions now come from uncore memory. This line can be removed at any time.
// imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
uncore uncore(.HWDATAIN(HWDATA), .*);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/wally-pipelined/src/wally/wallypipelinedsocwrapper.v b/wally-pipelined/src/wally/wallypipelinedsocwrapper.v
new file mode 100644
index 000000000..c12dcb8d6
--- /dev/null
+++ b/wally-pipelined/src/wally/wallypipelinedsocwrapper.v
@@ -0,0 +1,101 @@
+///////////////////////////////////////////
+// wally-pipelinedsoc.sv
+//
+// Written: David_Harris@hmc.edu 6 November 2020
+// Modified:
+//
+// Purpose: System on chip including pipelined processor and memories
+// Full RV32/64IC instruction set
+//
+// Note: the CSRs do not support the following features
+//- Disabling portions of the instruction set with bits of the MISA register
+//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+// As of January 2020, virtual memory is not yet supported
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module wallypipelinedsocwrapper (
+ input clk, reset,
+ // AHB Lite Interface
+ // inputs from external memory
+ input [`AHBW-1:0] HRDATAEXT,
+ input HREADYEXT, HRESPEXT,
+ output HSELEXT,
+ // outputs to external memory, shared with uncore memory
+ output HCLK, HRESETn,
+ output [31:0] HADDR,
+ output [`AHBW-1:0] HWDATA,
+ output HWRITE,
+ output [2:0] HSIZE,
+ output [2:0] HBURST,
+ output [3:0] HPROT,
+ output [1:0] HTRANS,
+ output HMASTLOCK,
+ output HREADY,
+ // I/O Interface
+ input [31:0] GPIOPinsIn,
+ output [31:0] GPIOPinsOut, GPIOPinsEn,
+ input UARTSin,
+ output UARTSout
+);
+
+ // to instruction memory *** remove later
+ wire [`XLEN-1:0] PCF;
+
+ // Uncore signals
+ wire [`AHBW-1:0] HRDATA; // from AHB mux in uncore
+ wire HREADY, HRESP;
+ wire [5:0] HSELRegions;
+ wire InstrAccessFaultF, DataAccessFaultM;
+ wire TimerIntM, SwIntM; // from CLINT
+ wire [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs
+ wire ExtIntM; // from PLIC
+ wire [2:0] HADDRD;
+ wire [3:0] HSIZED;
+ wire HWRITED;
+ wire [15:0] rd2; // bogus, delete when real multicycle fetch works
+ wire [31:0] InstrF;
+
+ // wrapper for fpga
+ wallypipelinedsoc wallypipelinedsoc
+ (.clk(clk),
+ .reset(reset),
+ .HRDATAEXT(HRDATAEXT),
+ .HREADYEXT(HREADYEXT),
+ .HRESPEXT(HRESPEXT),
+ .HSELEXT(HSELEXT),
+ .HCLK(HCLK),
+ .HRESETn(HRESETn),
+ .HADDR(HADDR),
+ .HWDATA(HWDATA),
+ .HWRITE(HWRITE),
+ .HSIZE(HSIZE),
+ .HBURST(HBURST),
+ .HPROT(HPROT),
+ .HTRANS(HTRANS),
+ .HMASTLOCK(HMASTLOCK),
+ .HREADY(HREADY),
+ .GPIOPinsIn(GPIOPinsIn),
+ .GPIOPinsOut(GPIOPinsOut),
+ .GPIOPinsEn(GPIOPinsEn),
+ .UARTSin(UARTSin),
+ .UARTSout(UARTSout));
+
+endmodule