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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Rose Thompson 2024-05-10 08:53:00 -05:00
commit b027fa44ef
18 changed files with 69 additions and 42 deletions
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8
bin/regression-wally
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@ -273,6 +273,7 @@ regressionDir = WALLY + '/sim'
os.chdir(regressionDir)
coveragesim = "questa" # Questa is required for code/functional coverage
#defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready
defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
#defaultsim = "verilator" # Default simulator for all other tests
@ -283,7 +284,8 @@ testfloat = '--testfloat' in sys.argv
if (nightly):
nightMode = "--nightly";
sims = [defaultsim]
# sims = [defaultsim]
sims = ["questa", "vcs"]
# sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators
else:
nightMode = ""
@ -323,9 +325,9 @@ else:
addTests(tests_buildrootshort, defaultsim)
# testfloat tests
if (testfloat):
if (testfloat): # for testfloat alone, just run testfloat tests
configs = []
if (testfloat or nightly): # for nightly, run testfloat along with othres
testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
for config in testfloatconfigs:
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]

2
config/rv32e/config.vh
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
localparam SVNAPOT_SUPPORTED = 0;
localparam SVINVAL_SUPPORTED = 0;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

2
config/rv32gc/config.vh
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@ -52,6 +52,8 @@ localparam ZICOND_SUPPORTED = 1;
localparam SVPBMT_SUPPORTED = 0;
localparam SVNAPOT_SUPPORTED = 0;
localparam SVINVAL_SUPPORTED = 1;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

2
config/rv32i/config.vh
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
localparam SVNAPOT_SUPPORTED = 0;
localparam SVINVAL_SUPPORTED = 0;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;

2
config/rv32imc/config.vh
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@ -50,6 +50,8 @@ localparam ZICOND_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
localparam SVNAPOT_SUPPORTED = 0;
localparam SVINVAL_SUPPORTED = 0;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

2
config/rv64gc/config.vh
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 1;
localparam SVPBMT_SUPPORTED = 1;
localparam SVNAPOT_SUPPORTED = 1;
localparam SVINVAL_SUPPORTED = 1;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

4
config/rv64i/config.vh
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@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
localparam SVNAPOT_SUPPORTED = 0;
localparam SVINVAL_SUPPORTED = 0;
localparam ZAAMO_SUPPORTED = 0;
localparam ZALRSC_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;
@ -108,7 +110,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam UNCORE_RAM_SUPPORTED = 1'b0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;

2
config/shared/parameter-defs.vh
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@ -31,6 +31,8 @@ localparam cvw_t P = '{
SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
SVNAPOT_SUPPORTED : SVNAPOT_SUPPORTED,
SVINVAL_SUPPORTED : SVINVAL_SUPPORTED,
ZAAMO_SUPPORTED : ZAAMO_SUPPORTED,
ZALRSC_SUPPORTED : ZALRSC_SUPPORTED,
BUS_SUPPORTED : BUS_SUPPORTED,
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
ICACHE_SUPPORTED : ICACHE_SUPPORTED,

33
docs/testplans/testplan.md
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@ -2,27 +2,22 @@
CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
| Functions | Coverage Method | Status |
| ----------- | ----------- |----|
| Instructions | riscv-arch-test | Pass |
| Privileged Unit | wally-riscv-arch-test | Pass |
| Virtual Memory | wally-riscv-arch-test | Pass |
| PMP | wally-riscv-arch-test | Pass
| Peripherals | wally-riscv-arch-test | Pass |
| Floating-Point | TestFloat | Pass |
| General | Code Coverage | 91% |
| General | Boot Linux in Sim | Pass |
| General | Boot Linux on FPGA | Pass |
| Tests | Section | TRL3 | TRL5 | Coverage Method | Status | Command |
| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- |
| Verilator Lint | 5.3 | All configs | rv64gc | lint-wally | PASS | regression-wally --nightly |
| Instructions | 3.7 | All configs | rv64gc | riscv-arch-test | PASS | regression-wally --nightly |
| Privileged | 3.7 | All configs | rv64gc | wally-riscv-arch-test | PASS | regression-wally --nightly |
| Floating-point | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc | TestFloat | FAIL | regression-wally --nightly |
| CoreMark | 21.1 | Many configs | rv64gc | CoreMark | | regression-wally --nightly |
| Embench | 21.2 | rv32* | n/a | Embench | | regression-wally --nightly |
| Cache PV | 21.3.1 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
| Cache PV | 21.3.2 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
| Linux Boot | 22.3.2 | rv64gc | rv64gc | TBD | TBD | TBD |
| FPGA Linux Boot | 23.2 | | rv64gc | TBD | TBD | TBD |
| Code Coverage | 5.11.10 | | rv64gc | TBD | TBD | TBD |
| Functional Coverage | 5.11.11 | | rv64gc | TBD | TBD | TBD |
The following performance validation is also run:
| Function | Method | Status |
| --- | --- | --- |
| Overall Performance | embench | Pass|
| Overall Performance | coremark | Pass |
| Branch Predictor | *** | Pass |
| Cache Miss Rate | *** | Pass |
* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.

2
sim/questa/wally.do
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@ -19,6 +19,7 @@
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
onerror {quit -f}
set CFG ${1}
set TESTSUITE ${2}
@ -117,6 +118,7 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgsLst} -o testbenchopt ${CoverageVoptArg}
# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg}

2
src/cvw.sv
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@ -66,6 +66,8 @@ typedef struct packed {
logic SVPBMT_SUPPORTED;
logic SVNAPOT_SUPPORTED;
logic SVINVAL_SUPPORTED;
logic ZAAMO_SUPPORTED;
logic ZALRSC_SUPPORTED;
// Microarchitectural Features
logic BUS_SUPPORTED;

6
src/fpu/postproc/shiftcorrection.sv
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@ -61,6 +61,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
// - a one has to propagate all the way through a sum. so we can leave the bottom statement alone
assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1];
// correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range
// condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1));
@ -72,8 +73,8 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
// if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
always_comb
if (FmaOp | DivOp & !DivResSubnorm) Mf = CorrShifted;
else Mf = Shifted[P.NORMSHIFTSZ-1:2];
if (FmaOp | (DivOp & ~DivResSubnorm)) Mf = CorrShifted;
else Mf = Shifted[P.NORMSHIFTSZ-1:2];
// Determine sum's exponent
// main exponent issues:
@ -92,3 +93,4 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
// if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1};
endmodule

8
src/ieu/controller.sv
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@ -265,12 +265,12 @@ module controller import cvw::*; #(parameter cvw_t P) (
ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
7'b0100111: if (FLSFunctD)
ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
7'b0101111: if (AFunctD) begin
if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
else if (InstrD[31:27] == 5'b00011)
else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011)
ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
else if (AMOFunctD)
else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD)
ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
end
7'b0110011: if (RFunctD)

4
src/ieu/datapath.sv
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@ -139,6 +139,6 @@ module datapath import cvw::*; #(parameter cvw_t P) (
mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);
// handle Store Conditional result if atomic extension supported
if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
else assign SCResultW = '0;
if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
else assign SCResultW = '0;
endmodule

19
src/lsu/atomic.sv
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@ -48,11 +48,20 @@ module atomic import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] AMOResultM;
logic MemReadM;
amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
// AMO ALU
if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin
amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
end else
assign IMAWriteDataM = IHWriteDataM;
mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
// LRSC unit
if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
end else begin
assign SquashSCW = 0;
assign LSURWM = PreLSURWM;
end
endmodule

2
src/lsu/lsu.sv
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@ -397,7 +397,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Atomic operations
/////////////////////////////////////////////////////////////////////////////////////////////
if (P.A_SUPPORTED) begin:atomic
if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.IMAWriteDataM, .SquashSCW, .LSURWM);

1
testbench/common/riscvassertions.sv
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@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported");
end
endmodule

4
testbench/testbench.sv
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@ -633,7 +633,7 @@ module testbench;
dut.core.ieu.dp.regf.a3 == 3 &
dut.core.ieu.dp.regf.wd3 == 1)) |
((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" );
end
DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
@ -644,7 +644,7 @@ module testbench;
always @(negedge clk) begin
if (INSTR_LIMIT > 0) begin
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
end
end
end