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This commit is contained in:
Ross Thompson 2023-01-19 15:06:37 -06:00
parent ea96c2375f
commit b027921902
2 changed files with 26 additions and 27 deletions
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16
pipelined/src/ifu/bpred.sv
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@ -1,13 +1,12 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// bpred.sv // bpred.sv
// //
// Written: Ross Thomposn // Written: Ross Thomposn ross1728@gmail.com
// Email: ross1728@gmail.com // Created: 12 February 2021
// Created: February 12, 2021 // Modified: 19 January 2023
// Modified:
// //
// Purpose: Branch prediction unit // Purpose: Branch direction prediction and jump/branch target prediction.
// Produces a branch prediction based on branch history. // Prediction made during the fetch stage and corrected in the execution stage.
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// //
@ -35,7 +34,7 @@ module bpred (
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
// Fetch stage // Fetch stage
// the prediction // the prediction
input logic [31:0] InstrD, // Decompressed decode stage instruction input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4 input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
@ -47,8 +46,7 @@ module bpred (
input logic [`XLEN-1:0] PCE, // Execution stage instruction address. input logic [`XLEN-1:0] PCE, // Execution stage instruction address.
input logic [`XLEN-1:0] PCM, // Memory stage instruction address. input logic [`XLEN-1:0] PCM, // Memory stage instruction address.
// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class. // Branch and jump outcome
// *** the specifics of how this is encode is subject to change.
input logic PCSrcE, // Executation stage branch is taken input logic PCSrcE, // Executation stage branch is taken
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)

5
pipelined/src/ifu/spill.sv
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@ -1,8 +1,9 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// spill.sv // spill.sv
// //
// Written: Ross Thompson ross1728@gmail.com January 28, 2022 // Written: Ross Thompson ross1728@gmail.com
// Modified: // Created: 28 January 2022
// Modified: 19 January 2023
// //
// Purpose: allows the IFU to make extra memory request if instruction address crosses // Purpose: allows the IFU to make extra memory request if instruction address crosses
// cache line boundaries or if instruction address without a cache crosses // cache line boundaries or if instruction address without a cache crosses