Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator

This commit is contained in:
David Harris 2023-12-13 11:33:59 -08:00
parent f64f4c638a
commit aff61ea97a
5 changed files with 41 additions and 18 deletions

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@ -30,7 +30,7 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
.PHONY: all generate disassemble install clean cleanDTB cleanDriver test .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
all: download Image disassemble install all: clean download Image disassemble install
Image: Image:
bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;"
@ -120,4 +120,4 @@ cleanDTB:
rm -f $(IMAGES)/*.dtb rm -f $(IMAGES)/*.dtb
clean: clean:
rm -rf $(DIS) rm -rf $(BUILDROOT)

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@ -110,15 +110,17 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
// *************************************************************************** // ***************************************************************************
integer i; integer i;
initial begin // initialize memory for simulation only
integer j;
for (j=0; j < DEPTH; j++)
mem[j] = '0;
end
// Read // Read
logic [$clog2(DEPTH)-1:0] ra1d; logic [$clog2(DEPTH)-1:0] ra1d;
flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
assign rd1 = mem[ra1d]; assign rd1 = mem[ra1d];
/* // Read
always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// coverage off // coverage off
// when byte write enables are tied high, the last IF is always taken // when byte write enables are tied high, the last IF is always taken

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@ -92,8 +92,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
assign RetM = mretM | sretM; assign RetM = mretM | sretM;
/////////////////////////////////////////// ///////////////////////////////////////////
// Cause priority defined in table 3.7 of 20190608 privileged spec // Cause priority defined in privileged spec
// Exceptions are of lower priority than all interrupts (3.1.9)
/////////////////////////////////////////// ///////////////////////////////////////////
always_comb always_comb

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@ -27,7 +27,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module loggers import cvw::*; #(parameter cvw_t P, module loggers import cvw::*; #(parameter cvw_t P,
parameter TEST, parameter string TEST,
parameter PrintHPMCounters, parameter PrintHPMCounters,
parameter I_CACHE_ADDR_LOGGER, parameter I_CACHE_ADDR_LOGGER,
parameter D_CACHE_ADDR_LOGGER, parameter D_CACHE_ADDR_LOGGER,

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@ -86,6 +86,24 @@ module testbench;
logic Validate; logic Validate;
logic SelectTest; logic SelectTest;
// Nasty hack to get around Verilog simulators being picky about conditionally instantiated signals
initial begin
if (P.DTIM_SUPPORTED) begin
// `define P_DTIM_SUPPORTED=1;
end
if (P.IROM_SUPPORTED) begin
`define P_IROM_SUPPORTED=1;
end
if (P.BUS_SUPPORTED) begin
`define P_BUS_SUPPORTED=1;
end
if (P.SDC_SUPPORTED) begin
`define P_SDC_SUPPORTED=1;
end
if (P.UNCORE_RAM_SUPPORTED) begin
`define P_UNCORE_RAM_SUPPORTED=1;
end
end
// pick tests based on modes supported // pick tests based on modes supported
initial begin initial begin
@ -271,7 +289,7 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
if(TestBenchReset) test = 1; if(TestBenchReset) test = 1;
if (TEST == "coremark") if (TEST == "coremark")
if (dut.core.EcallFaultM) begin if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done."); $display("Benchmark: coremark is done.");
$stop; $stop;
end end
@ -326,7 +344,7 @@ module testbench;
if (P.UNCORE_RAM_SUPPORTED) if (P.UNCORE_RAM_SUPPORTED)
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
if(reset) begin // branch predictor must always be reset /* if(reset) begin // branch predictor must always be reset
if (P.BPRED_SUPPORTED) begin if (P.BPRED_SUPPORTED) begin
// local history only // local history only
if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)
@ -337,7 +355,7 @@ module testbench;
for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end end
end end */
end end
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
@ -345,7 +363,7 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin always @(posedge clk) begin
if (LoadMem) begin if (LoadMem) begin
if (P.SDC_SUPPORTED) begin `ifdef P_SDC_SUPPORTED
string romfilename, sdcfilename; string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
@ -353,10 +371,14 @@ module testbench;
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation // shorten sdc timers for simulation
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1; //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end `elsif P_IROM_SUPPORTED
else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); `else if P_BUS_SUPPORTED
if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
`endif
`ifdef P_DTIM_SUPPORTED
$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
`endif
$display("Read memfile %s", memfilename); $display("Read memfile %s", memfilename);
end end
end end