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Update csrc.sv

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Program clean up
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Harshini Srinath 2023-06-13 21:54:47 -07:00 committed by GitHub
parent fb019a736c
commit aff15a0a46
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1 changed files with 30 additions and 30 deletions
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src/privileged/csrc.sv
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@ -90,9 +90,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[0] = 1'b1; // MCYCLE always increments assign CounterEvent[0] = 1'b1; // MCYCLE always increments
assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired
if(P.QEMU) begin: cevent // No other performance counters in QEMU if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters
assign CounterEvent[P.COUNTERS-1:3] = 0;
end else begin: cevent // User-defined counters
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
@ -119,6 +117,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle
// coverage on // coverage on
assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end else begin: cevent
assign CounterEvent[P.COUNTERS-1:3] = 0;
end end
// Counter update and write logic // Counter update and write logic
@ -163,7 +163,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
IllegalCSRCAccessM = 1; // requested CSR doesn't exist IllegalCSRCAccessM = 1; // requested CSR doesn't exist
end end
end else begin // 32-bit counter reads end else begin // 32-bit counter reads
// Veri lator doesn't realize this only occurs for XLEN=32 // Veril ator doesn't realize this only occurs for XLEN=32
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32]; else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];