diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
index d4029fafa..6e173d59e 100644
--- a/wally-pipelined/src/uncore/uartPC16550D.sv
+++ b/wally-pipelined/src/uncore/uartPC16550D.sv
@@ -377,9 +377,7 @@ module uartPC16550D(
           txhrfull <= #1 1;
         end
         $write("%c",Din); // for testbench
-        //if (Din == 13) $fflush;
-        $fflush;
-      end
+       end
       if (txstate == UART_IDLE) begin // move data into tx shift register if available
         if (fifoenabled) begin 
           if (~txfifoempty) begin