mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
af75140bbc
1
.gitignore
vendored
1
.gitignore
vendored
@ -211,6 +211,7 @@ sim/vcs/sim_out*
|
|||||||
sim/vcs/simprofile_dir
|
sim/vcs/simprofile_dir
|
||||||
sim/vcs/ucli.key
|
sim/vcs/ucli.key
|
||||||
sim/vcs/verdi_config_file
|
sim/vcs/verdi_config_file
|
||||||
|
sim/vcs/vcdplus.vpd
|
||||||
sim/*/testbench.vcd
|
sim/*/testbench.vcd
|
||||||
sim/questa/imperas.log
|
sim/questa/imperas.log
|
||||||
sim/questa/functcov.log
|
sim/questa/functcov.log
|
||||||
|
|||||||
56
README.md
56
README.md
@ -41,19 +41,14 @@ Clone your fork of the repo and run the setup script. Change <yourgithubid> to y
|
|||||||
$ git remote add upstream https://github.com/openhwgroup/cvw
|
$ git remote add upstream https://github.com/openhwgroup/cvw
|
||||||
$ source ./setup.sh
|
$ source ./setup.sh
|
||||||
|
|
||||||
|
If you are installing on a new system without any tools installed please jump to the next section, Toolchain Installation then come back here.
|
||||||
|
|
||||||
Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
|
Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
|
||||||
|
|
||||||
if [ -f ~/cvw/setup.sh ]; then
|
if [ -f ~/cvw/setup.sh ]; then
|
||||||
source ~/cvw/setup.sh
|
source ~/cvw/setup.sh
|
||||||
fi
|
fi
|
||||||
|
|
||||||
Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis.
|
|
||||||
|
|
||||||
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
|
|
||||||
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
|
|
||||||
export QUESTAPATH=.. # Change this for your path to Questa
|
|
||||||
export SNPSPATH=.. # Change this for your path to Design Compiler
|
|
||||||
|
|
||||||
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
|
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
|
||||||
|
|
||||||
Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while.
|
Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while.
|
||||||
@ -73,6 +68,19 @@ Ubuntu users can install the tools by running
|
|||||||
|
|
||||||
$ sudo $WALLY/bin/wally-tool-chain-install.sh
|
$ sudo $WALLY/bin/wally-tool-chain-install.sh
|
||||||
|
|
||||||
|
The default installation directory is /opt/riscv defined by the environment variable RISCV. You must copy and edit ~/cvw/site-setup.sh to $RISCV/site-setup.sh.
|
||||||
|
|
||||||
|
~/cvw/setup.sh sources $RISCV/site-setup.sh.
|
||||||
|
This allows for customization of the site specific information such as commerical licenses and PATH variables.
|
||||||
|
|
||||||
|
Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. If Questa or Design Compiler are already setup on this system then don't set these variables.
|
||||||
|
|
||||||
|
export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server
|
||||||
|
export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server
|
||||||
|
export QUESTAPATH=.. # Change this for your path to Questa
|
||||||
|
export SNPSPATH=.. # Change this for your path to Design Compiler
|
||||||
|
|
||||||
|
|
||||||
See wally-tool-chain-install.sh for a detailed description of each component,
|
See wally-tool-chain-install.sh for a detailed description of each component,
|
||||||
or to issue the commands one at a time to install on the command line.
|
or to issue the commands one at a time to install on the command line.
|
||||||
## Installing EDA Tools
|
## Installing EDA Tools
|
||||||
@ -138,3 +146,37 @@ If you want to add a cronjob you can do the following:
|
|||||||
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
|
30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
|
||||||
```
|
```
|
||||||
|
|
||||||
|
# Example wsim commands
|
||||||
|
|
||||||
|
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
|
||||||
|
The general syntax is
|
||||||
|
wsim <config> <suite or elf file> [--options]
|
||||||
|
|
||||||
|
Parameters and options:
|
||||||
|
|
||||||
|
-h, --help show this help message and exit
|
||||||
|
--elf, -e Elf file
|
||||||
|
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
|
||||||
|
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
|
||||||
|
--gui, -g Simulate with GUI
|
||||||
|
--coverage, -c Code & Functional Coverage
|
||||||
|
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
|
||||||
|
--vcd, -v Generate testbench.vcd
|
||||||
|
--lockstep, -l Run ImperasDV lock, step, and compare.
|
||||||
|
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
|
||||||
|
|
||||||
|
Run basic test with questa
|
||||||
|
|
||||||
|
wsim rv64gc arch64i
|
||||||
|
|
||||||
|
Run Questa with gui
|
||||||
|
|
||||||
|
wsim rv64gc wally64priv --gui
|
||||||
|
|
||||||
|
Run lockstep against ImperasDV with a single elf file in the --gui. Lockstep requires single elf.
|
||||||
|
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep --gui
|
||||||
|
|
||||||
|
Run lockstep against ImperasDV with a single elf file. Compute coverage.
|
||||||
|
|
||||||
|
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep --coverage
|
||||||
|
|||||||
24
bin/wsim
24
bin/wsim
@ -18,14 +18,22 @@ import os
|
|||||||
parser = argparse.ArgumentParser()
|
parser = argparse.ArgumentParser()
|
||||||
parser.add_argument("config", help="Configuration file")
|
parser.add_argument("config", help="Configuration file")
|
||||||
parser.add_argument("testsuite", help="Test suite or ELF file")
|
parser.add_argument("testsuite", help="Test suite or ELF file")
|
||||||
|
parser.add_argument("--elf", "-e", help="Elf file", action="store_true")
|
||||||
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
|
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
|
||||||
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
|
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
|
||||||
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
|
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
|
||||||
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
|
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
|
||||||
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
||||||
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
|
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
|
||||||
|
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
|
||||||
|
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
|
||||||
args = parser.parse_args()
|
args = parser.parse_args()
|
||||||
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
|
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
|
||||||
|
ElfFile=""
|
||||||
|
|
||||||
|
if(args.elf):
|
||||||
|
ElfFile = "+ElfFile=" + args.testsuite
|
||||||
|
args.testsuite = "none"
|
||||||
|
|
||||||
# Validate arguments
|
# Validate arguments
|
||||||
if (args.gui):
|
if (args.gui):
|
||||||
@ -50,21 +58,29 @@ for d in ["logs", "wkdir", "cov"]:
|
|||||||
except:
|
except:
|
||||||
pass
|
pass
|
||||||
|
|
||||||
|
|
||||||
# Launch selected simulator
|
# Launch selected simulator
|
||||||
cd = "cd $WALLY/sim/" +args.sim
|
cd = "cd $WALLY/sim/" +args.sim
|
||||||
if (args.sim == "questa"):
|
if (args.sim == "questa"):
|
||||||
|
if (args.lockstep):
|
||||||
|
Instret = str(args.locksteplog)
|
||||||
|
prefix ="IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic OTHERFLAGS=\"+IDV_TRACE2LOG=" + Instret + " +IDV_TRACE2COV=" + Instret + "\" ";
|
||||||
|
suffix = "--lockstep"
|
||||||
|
else:
|
||||||
|
prefix = ""
|
||||||
|
suffix = ""
|
||||||
if (args.tb == "testbench_fp"):
|
if (args.tb == "testbench_fp"):
|
||||||
args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
|
args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
|
||||||
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
|
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix
|
||||||
if (args.coverage):
|
if (args.coverage):
|
||||||
cmd += " --coverage"
|
cmd += " --coverage"
|
||||||
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
|
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
|
||||||
if(args.tb == "testbench"):
|
if(args.tb == "testbench"):
|
||||||
cmd = cd + "; vsim -do \"" + cmd + " +acc -GDEBUG=1\""
|
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\""
|
||||||
elif(args.tb == "testbench_fp"):
|
elif(args.tb == "testbench_fp"):
|
||||||
cmd = cd + "; vsim -do \"" + cmd + " +acc\""
|
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc\""
|
||||||
else: # launch Questa in batch mode
|
else: # launch Questa in batch mode
|
||||||
cmd = cd + "; vsim -c -do \"" + cmd + "\""
|
cmd = cd + "; " + prefix + " vsim -c -do \"" + cmd + "\""
|
||||||
print("Running Questa with command: " + cmd)
|
print("Running Questa with command: " + cmd)
|
||||||
os.system(cmd)
|
os.system(cmd)
|
||||||
elif (args.sim == "verilator"):
|
elif (args.sim == "verilator"):
|
||||||
|
|||||||
@ -100,19 +100,25 @@ deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0
|
|||||||
ZICSR_SUPPORTED 0
|
ZICSR_SUPPORTED 0
|
||||||
|
|
||||||
deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
|
deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
F_SUPPORTED 0
|
||||||
|
D_SUPPORTED 0
|
||||||
deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
|
deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
F_SUPPORTED 0
|
||||||
|
D_SUPPORTED 0
|
||||||
|
|
||||||
deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
|
deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
|
M_SUPPORTED 0
|
||||||
|
ZMMUL_SUPPORTED 0
|
||||||
deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
|
deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
|
M_SUPPORTED 0
|
||||||
|
ZMMUL_SUPPORTED 0
|
||||||
|
|
||||||
deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
|
deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20)
|
ZAAMO_SUPPORTED 0
|
||||||
|
ZALRSC_SUPPORTED 0
|
||||||
deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
|
deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
|
||||||
MISA (32'h00000104 | 1 << 18 | 1 << 20)
|
ZAAMO_SUPPORTED 0
|
||||||
|
ZALRSC_SUPPORTED 0
|
||||||
|
|
||||||
# Divider variants to check logical correctness
|
# Divider variants to check logical correctness
|
||||||
|
|
||||||
@ -140,7 +146,6 @@ deriv div_4_2_rv32gc rv32gc
|
|||||||
RADIX 32'd4
|
RADIX 32'd4
|
||||||
IDIV_ON_FPU 0
|
IDIV_ON_FPU 0
|
||||||
DIVCOPIES 32'd2
|
DIVCOPIES 32'd2
|
||||||
IDIV_ON_FPU 0
|
|
||||||
|
|
||||||
deriv div_4_4_rv32gc rv32gc
|
deriv div_4_4_rv32gc rv32gc
|
||||||
RADIX 32'd4
|
RADIX 32'd4
|
||||||
@ -407,7 +412,8 @@ ZICBOM_SUPPORTED 0
|
|||||||
ZICBOZ_SUPPORTED 0
|
ZICBOZ_SUPPORTED 0
|
||||||
SVPBMT_SUPPORTED 0
|
SVPBMT_SUPPORTED 0
|
||||||
SVNAPOT_SUPPORTED 0
|
SVNAPOT_SUPPORTED 0
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
|
ZAAMO_SUPPORTED 0
|
||||||
|
ZALRSC_SUPPORTED 0
|
||||||
|
|
||||||
deriv nocache_rv64gc rv64gc
|
deriv nocache_rv64gc rv64gc
|
||||||
ICACHE_SUPPORTED 0
|
ICACHE_SUPPORTED 0
|
||||||
@ -417,7 +423,8 @@ ZICBOM_SUPPORTED 0
|
|||||||
ZICBOZ_SUPPORTED 0
|
ZICBOZ_SUPPORTED 0
|
||||||
SVPBMT_SUPPORTED 0
|
SVPBMT_SUPPORTED 0
|
||||||
SVNAPOT_SUPPORTED 0
|
SVNAPOT_SUPPORTED 0
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
|
ZAAMO_SUPPORTED 0
|
||||||
|
ZALRSC_SUPPORTED 0
|
||||||
|
|
||||||
deriv way_1_4096_512_rv32gc rv32gc
|
deriv way_1_4096_512_rv32gc rv32gc
|
||||||
DCACHE_NUMWAYS 32'd1
|
DCACHE_NUMWAYS 32'd1
|
||||||
@ -512,69 +519,61 @@ deriv nobigendian_rv64gc rv64gc
|
|||||||
BIGENDIAN_SUPPORTED 0
|
BIGENDIAN_SUPPORTED 0
|
||||||
|
|
||||||
deriv zaamo_rv32gc rv32gc
|
deriv zaamo_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
|
ZALRSC_SUPPORTED 0
|
||||||
ZAAMO_SUPPORTED 1
|
|
||||||
|
|
||||||
deriv zalrsc_rv32gc rv32gc
|
deriv zalrsc_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
|
ZAAMO_SUPPORTED 0
|
||||||
ZALRSC_SUPPORTED 1
|
|
||||||
|
|
||||||
deriv zaamo_rv64gc rv64gc
|
deriv zaamo_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
|
ZALRSC_SUPPORTED 0
|
||||||
ZAAMO_SUPPORTED 1
|
|
||||||
|
|
||||||
deriv zalrsc_rv64gc rv64gc
|
deriv zalrsc_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
|
ZAAMO_SUPPORTED 0
|
||||||
ZALRSC_SUPPORTED 1
|
|
||||||
|
|
||||||
# Floating-point modes supported
|
# Floating-point modes supported
|
||||||
|
|
||||||
deriv f_rv32gc rv32gc
|
deriv f_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fh_rv32gc rv32gc
|
deriv fh_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fd_rv32gc rv32gc
|
deriv fd_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdh_rv32gc rv32gc
|
deriv fdh_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdq_rv32gc rv32gc
|
deriv fdq_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdqh_rv32gc rv32gc
|
deriv fdqh_rv32gc rv32gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv f_rv64gc rv64gc
|
deriv f_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fh_rv64gc rv64gc
|
deriv fh_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fd_rv64gc rv64gc
|
deriv fd_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdh_rv64gc rv64gc
|
deriv fdh_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdq_rv64gc rv64gc
|
deriv fdq_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdqh_rv64gc rv64gc
|
deriv fdqh_rv64gc rv64gc
|
||||||
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
# IEEE compatible variants for TestFloat
|
# IEEE compatible variants for TestFloat
|
||||||
@ -619,302 +618,278 @@ IEEE754 1
|
|||||||
|
|
||||||
#### F_only, RK variable
|
#### F_only, RK variable
|
||||||
deriv f_div_2_1_rv32gc div_2_1_rv32gc
|
deriv f_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_2_2_rv32gc div_2_2_rv32gc
|
deriv f_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_2_4_rv32gc div_2_4_rv32gc
|
deriv f_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_1_rv32gc div_4_1_rv32gc
|
deriv f_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_2_rv32gc div_4_2_rv32gc
|
deriv f_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_4_rv32gc div_4_4_rv32gc
|
deriv f_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_2_1_rv64gc div_2_1_rv64gc
|
deriv f_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_2_2_rv64gc div_2_2_rv64gc
|
deriv f_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_2_4_rv64gc div_2_4_rv64gc
|
deriv f_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_1_rv64gc div_4_1_rv64gc
|
deriv f_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_2_rv64gc div_4_2_rv64gc
|
deriv f_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv f_div_4_4_rv64gc div_4_4_rv64gc
|
deriv f_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
|
|
||||||
#### FH_only, RK variable
|
#### FH_only, RK variable
|
||||||
deriv fh_div_2_1_rv32gc div_2_1_rv32gc
|
deriv fh_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_2_2_rv32gc div_2_2_rv32gc
|
deriv fh_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_2_4_rv32gc div_2_4_rv32gc
|
deriv fh_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_1_rv32gc div_4_1_rv32gc
|
deriv fh_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_2_rv32gc div_4_2_rv32gc
|
deriv fh_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_4_rv32gc div_4_4_rv32gc
|
deriv fh_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_2_1_rv64gc div_2_1_rv64gc
|
deriv fh_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_2_2_rv64gc div_2_2_rv64gc
|
deriv fh_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_2_4_rv64gc div_2_4_rv64gc
|
deriv fh_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_1_rv64gc div_4_1_rv64gc
|
deriv fh_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_2_rv64gc div_4_2_rv64gc
|
deriv fh_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fh_div_4_4_rv64gc div_4_4_rv64gc
|
deriv fh_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
D_SUPPORTED 0
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
# FD only , rk variable
|
# FD only , rk variable
|
||||||
|
|
||||||
deriv fd_div_2_1_rv32gc div_2_1_rv32gc
|
deriv fd_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_2_2_rv32gc div_2_2_rv32gc
|
deriv fd_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_2_4_rv32gc div_2_4_rv32gc
|
deriv fd_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_1_rv32gc div_4_1_rv32gc
|
deriv fd_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_2_rv32gc div_4_2_rv32gc
|
deriv fd_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_4_rv32gc div_4_4_rv32gc
|
deriv fd_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_2_1_rv64gc div_2_1_rv64gc
|
deriv fd_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_2_2_rv64gc div_2_2_rv64gc
|
deriv fd_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_2_4_rv64gc div_2_4_rv64gc
|
deriv fd_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_1_rv64gc div_4_1_rv64gc
|
deriv fd_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_2_rv64gc div_4_2_rv64gc
|
deriv fd_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fd_div_4_4_rv64gc div_4_4_rv64gc
|
deriv fd_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
|
|
||||||
# FDH only , rk variable
|
# FDH only , rk variable
|
||||||
|
|
||||||
deriv fdh_div_2_1_rv32gc div_2_1_rv32gc
|
deriv fdh_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_2_2_rv32gc div_2_2_rv32gc
|
deriv fdh_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_2_4_rv32gc div_2_4_rv32gc
|
deriv fdh_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_1_rv32gc div_4_1_rv32gc
|
deriv fdh_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_2_rv32gc div_4_2_rv32gc
|
deriv fdh_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_4_rv32gc div_4_4_rv32gc
|
deriv fdh_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_2_1_rv64gc div_2_1_rv64gc
|
deriv fdh_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_2_2_rv64gc div_2_2_rv64gc
|
deriv fdh_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_2_4_rv64gc div_2_4_rv64gc
|
deriv fdh_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_1_rv64gc div_4_1_rv64gc
|
deriv fdh_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_2_rv64gc div_4_2_rv64gc
|
deriv fdh_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdh_div_4_4_rv64gc div_4_4_rv64gc
|
deriv fdh_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
# FDQ only , rk variable
|
# FDQ only , rk variable
|
||||||
|
|
||||||
deriv fdq_div_2_1_rv32gc div_2_1_rv32gc
|
deriv fdq_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_2_2_rv32gc div_2_2_rv32gc
|
deriv fdq_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_2_4_rv32gc div_2_4_rv32gc
|
deriv fdq_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_1_rv32gc div_4_1_rv32gc
|
deriv fdq_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_2_rv32gc div_4_2_rv32gc
|
deriv fdq_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_4_rv32gc div_4_4_rv32gc
|
deriv fdq_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_2_1_rv64gc div_2_1_rv64gc
|
deriv fdq_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_2_2_rv64gc div_2_2_rv64gc
|
deriv fdq_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_2_4_rv64gc div_2_4_rv64gc
|
deriv fdq_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_1_rv64gc div_4_1_rv64gc
|
deriv fdq_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_2_rv64gc div_4_2_rv64gc
|
deriv fdq_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
deriv fdq_div_4_4_rv64gc div_4_4_rv64gc
|
deriv fdq_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 0
|
ZFH_SUPPORTED 0
|
||||||
|
|
||||||
# FDQH only , rk variable
|
# FDQH only , rk variable
|
||||||
|
|
||||||
deriv fdqh_div_2_1_rv32gc div_2_1_rv32gc
|
deriv fdqh_div_2_1_rv32gc div_2_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_2_2_rv32gc div_2_2_rv32gc
|
deriv fdqh_div_2_2_rv32gc div_2_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_2_4_rv32gc div_2_4_rv32gc
|
deriv fdqh_div_2_4_rv32gc div_2_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_1_rv32gc div_4_1_rv32gc
|
deriv fdqh_div_4_1_rv32gc div_4_1_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc
|
deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_4_rv32gc div_4_4_rv32gc
|
deriv fdqh_div_4_4_rv32gc div_4_4_rv32gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc
|
deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_2_2_rv64gc div_2_2_rv64gc
|
deriv fdqh_div_2_2_rv64gc div_2_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_2_4_rv64gc div_2_4_rv64gc
|
deriv fdqh_div_2_4_rv64gc div_2_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_1_rv64gc div_4_1_rv64gc
|
deriv fdqh_div_4_1_rv64gc div_4_1_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_2_rv64gc div_4_2_rv64gc
|
deriv fdqh_div_4_2_rv64gc div_4_2_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
deriv fdqh_div_4_4_rv64gc div_4_4_rv64gc
|
deriv fdqh_div_4_4_rv64gc div_4_4_rv64gc
|
||||||
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
|
Q_SUPPORTED 1
|
||||||
ZFH_SUPPORTED 1
|
ZFH_SUPPORTED 1
|
||||||
|
|
||||||
#### DIVIDER VARIANTS WITH IEEE
|
#### DIVIDER VARIANTS WITH IEEE
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -33,34 +33,88 @@ localparam XLEN = 32'd32;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// E
|
// RISC-V configuration per specification
|
||||||
localparam MISA = (32'h00000010);
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZICSR_SUPPORTED = 0;
|
localparam logic E_SUPPORTED = 1;
|
||||||
localparam ZIFENCEI_SUPPORTED = 0;
|
|
||||||
|
// Integer instruction set extensions
|
||||||
|
localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
|
||||||
|
localparam logic ZICSR_SUPPORTED = 0; // CSR Instructions
|
||||||
|
localparam logic ZICCLSM_SUPPORTED = 0; // Misaligned loads/stores
|
||||||
|
localparam logic ZICOND_SUPPORTED = 0; // Integer conditional operations
|
||||||
|
|
||||||
|
// Multiplication & division extensions
|
||||||
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
|
localparam logic M_SUPPORTED = 0;
|
||||||
|
localparam logic ZMMUL_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Atomic extensions
|
||||||
|
// A extension is Zaamo + Zalrsc
|
||||||
|
localparam logic ZAAMO_SUPPORTED = 0;
|
||||||
|
localparam logic ZALRSC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 0;
|
||||||
|
localparam logic ZBB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBS_SUPPORTED = 0;
|
||||||
|
localparam logic ZBC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 0;
|
||||||
|
localparam logic ZKND_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 0;
|
||||||
|
localparam logic ZCB_SUPPORTED = 0;
|
||||||
|
localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 0; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 0;
|
||||||
|
localparam logic D_SUPPORTED = 0;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 0;
|
||||||
|
localparam logic ZFA_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 0; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 0; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 0;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 0;
|
||||||
localparam COUNTERS = 12'd0;
|
localparam COUNTERS = 12'd0;
|
||||||
localparam ZICNTR_SUPPORTED = 0;
|
|
||||||
localparam ZIHPM_SUPPORTED = 0;
|
// Cache-management operation extensions
|
||||||
localparam ZFH_SUPPORTED = 0;
|
localparam logic ZICBOM_SUPPORTED = 0;
|
||||||
localparam ZFA_SUPPORTED = 0;
|
localparam logic ZICBOZ_SUPPORTED = 0;
|
||||||
localparam SSTC_SUPPORTED = 0;
|
localparam logic ZICBOP_SUPPORTED = 0;
|
||||||
localparam ZICBOM_SUPPORTED = 0;
|
|
||||||
localparam ZICBOZ_SUPPORTED = 0;
|
// Virtual memory extensions
|
||||||
localparam ZICBOP_SUPPORTED = 0;
|
localparam logic SVPBMT_SUPPORTED = 0;
|
||||||
localparam ZICCLSM_SUPPORTED = 0;
|
localparam logic SVNAPOT_SUPPORTED = 0;
|
||||||
localparam ZICOND_SUPPORTED = 0;
|
localparam logic SVINVAL_SUPPORTED = 0;
|
||||||
localparam SVPBMT_SUPPORTED = 0;
|
localparam logic SVADU_SUPPORTED = 0;
|
||||||
localparam SVNAPOT_SUPPORTED = 0;
|
|
||||||
localparam SVINVAL_SUPPORTED = 0;
|
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 1;
|
localparam logic BUS_SUPPORTED = 1;
|
||||||
localparam DCACHE_SUPPORTED = 0;
|
localparam logic DCACHE_SUPPORTED = 0;
|
||||||
localparam ICACHE_SUPPORTED = 0;
|
localparam logic ICACHE_SUPPORTED = 0;
|
||||||
localparam VIRTMEM_SUPPORTED = 0;
|
localparam logic VIRTMEM_SUPPORTED = 0;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 0;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 0;
|
||||||
localparam BIGENDIAN_SUPPORTED = 0;
|
localparam logic BIGENDIAN_SUPPORTED = 0;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd0;
|
localparam ITLB_ENTRIES = 32'd0;
|
||||||
@ -79,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd1;
|
localparam IDIV_BITSPERCYCLE = 32'd1;
|
||||||
localparam IDIV_ON_FPU = 0;
|
localparam logic IDIV_ON_FPU = 0;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd0;
|
localparam PMP_ENTRIES = 32'd0;
|
||||||
@ -90,63 +144,64 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
|||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
localparam DTIM_SUPPORTED = 1'b0;
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic DTIM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam IROM_SUPPORTED = 1'b0;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic IROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
|
localparam logic BOOTROM_SUPPORTED = 1;
|
||||||
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
localparam logic UNCORE_RAM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b0;
|
localparam logic CLINT_SUPPORTED = 0;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b0;
|
localparam logic GPIO_SUPPORTED = 0;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b0;
|
localparam logic UART_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b0;
|
localparam logic PLIC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b0;
|
localparam logic SPI_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
// Bus Interface width
|
// Bus Interface width
|
||||||
localparam AHBW = 32'd32;
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 0;
|
localparam logic SPI_LOOPBACK_TEST = 0;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
localparam PLIC_NUM_SRC = 32'd10;
|
localparam PLIC_NUM_SRC = 32'd10;
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||||
localparam PLIC_GPIO_ID = 32'd3;
|
localparam PLIC_GPIO_ID = 32'd3;
|
||||||
@ -154,7 +209,8 @@ localparam PLIC_UART_ID = 32'd10;
|
|||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 0;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 0;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
@ -162,36 +218,11 @@ localparam BTB_SIZE = 32'd10;
|
|||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 0;
|
localparam INSTR_CLASS_PRED = 0;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 0;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'd4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'd4;
|
localparam DIVCOPIES = 32'd4;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 0;
|
|
||||||
localparam ZBB_SUPPORTED = 0;
|
|
||||||
localparam ZBC_SUPPORTED = 0;
|
|
||||||
localparam ZBS_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 0;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 0;
|
|
||||||
localparam ZBKC_SUPPORTED = 0;
|
|
||||||
localparam ZBKX_SUPPORTED = 0;
|
|
||||||
localparam ZKNE_SUPPORTED = 0;
|
|
||||||
localparam ZKND_SUPPORTED = 0;
|
|
||||||
localparam ZK_SUPPORTED = 0;
|
|
||||||
localparam ZKNH_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -25,8 +25,6 @@
|
|||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// include shared configuration
|
|
||||||
// `include "wally-shared.vh"
|
|
||||||
`include "BranchPredictorType.vh"
|
`include "BranchPredictorType.vh"
|
||||||
|
|
||||||
// RV32 or RV64: XLEN = 32 or 64
|
// RV32 or RV64: XLEN = 32 or 64
|
||||||
@ -35,33 +33,88 @@ localparam XLEN = 32'd32;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
|
// RISC-V configuration per specification
|
||||||
localparam ZICSR_SUPPORTED = 1;
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZIFENCEI_SUPPORTED = 1;
|
localparam logic E_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Integer instruction set extensions
|
||||||
|
localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
|
||||||
|
localparam logic ZICSR_SUPPORTED = 1; // CSR Instructions
|
||||||
|
localparam logic ZICCLSM_SUPPORTED = 0; // Misaligned loads/stores
|
||||||
|
localparam logic ZICOND_SUPPORTED = 1; // Integer conditional operations
|
||||||
|
|
||||||
|
// Multiplication & division extensions
|
||||||
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
|
localparam logic M_SUPPORTED = 1;
|
||||||
|
localparam logic ZMMUL_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Atomic extensions
|
||||||
|
// A extension is Zaamo + Zalrsc
|
||||||
|
localparam logic ZAAMO_SUPPORTED = 1;
|
||||||
|
localparam logic ZALRSC_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 1;
|
||||||
|
localparam logic ZBB_SUPPORTED = 1;
|
||||||
|
localparam logic ZBS_SUPPORTED = 1;
|
||||||
|
localparam logic ZBC_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 1;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 1;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 1;
|
||||||
|
localparam logic ZKND_SUPPORTED = 1;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 1;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 1;
|
||||||
|
localparam logic ZCB_SUPPORTED = 1;
|
||||||
|
localparam logic ZCF_SUPPORTED = 1; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 1; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 1;
|
||||||
|
localparam logic D_SUPPORTED = 1;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 1;
|
||||||
|
localparam logic ZFA_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 1; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 1; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 1;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 1;
|
||||||
localparam COUNTERS = 12'd32;
|
localparam COUNTERS = 12'd32;
|
||||||
localparam ZICNTR_SUPPORTED = 1;
|
|
||||||
localparam ZIHPM_SUPPORTED = 1;
|
// Cache-management operation extensions
|
||||||
localparam ZFH_SUPPORTED = 1;
|
localparam logic ZICBOM_SUPPORTED = 1;
|
||||||
localparam ZFA_SUPPORTED = 1;
|
localparam logic ZICBOZ_SUPPORTED = 1;
|
||||||
localparam SSTC_SUPPORTED = 1;
|
localparam logic ZICBOP_SUPPORTED = 1;
|
||||||
localparam ZICBOM_SUPPORTED = 1;
|
|
||||||
localparam ZICBOZ_SUPPORTED = 1;
|
// Virtual memory extensions
|
||||||
localparam ZICBOP_SUPPORTED = 1;
|
localparam logic SVPBMT_SUPPORTED = 0;
|
||||||
localparam ZICCLSM_SUPPORTED = 0;
|
localparam logic SVNAPOT_SUPPORTED = 0;
|
||||||
localparam ZICOND_SUPPORTED = 1;
|
localparam logic SVINVAL_SUPPORTED = 1;
|
||||||
localparam SVPBMT_SUPPORTED = 0;
|
localparam logic SVADU_SUPPORTED = 1;
|
||||||
localparam SVNAPOT_SUPPORTED = 0;
|
|
||||||
localparam SVINVAL_SUPPORTED = 1;
|
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 1;
|
localparam logic BUS_SUPPORTED = 1;
|
||||||
localparam DCACHE_SUPPORTED = 1;
|
localparam logic DCACHE_SUPPORTED = 1;
|
||||||
localparam ICACHE_SUPPORTED = 1;
|
localparam logic ICACHE_SUPPORTED = 1;
|
||||||
localparam VIRTMEM_SUPPORTED = 1;
|
localparam logic VIRTMEM_SUPPORTED = 1;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||||
localparam BIGENDIAN_SUPPORTED = 1;
|
localparam logic BIGENDIAN_SUPPORTED = 1;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd32;
|
localparam ITLB_ENTRIES = 32'd32;
|
||||||
@ -80,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd2;
|
localparam IDIV_BITSPERCYCLE = 32'd2;
|
||||||
localparam IDIV_ON_FPU = 0;
|
localparam logic IDIV_ON_FPU = 0;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd16;
|
localparam PMP_ENTRIES = 32'd16;
|
||||||
@ -91,57 +144,58 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
|||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
localparam DTIM_SUPPORTED = 1'b0;
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic DTIM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam IROM_SUPPORTED = 1'b0;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic IROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
localparam logic BOOTROM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
localparam logic UNCORE_RAM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b1;
|
localparam logic CLINT_SUPPORTED = 1;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b1;
|
localparam logic GPIO_SUPPORTED = 1;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b1;
|
localparam logic UART_SUPPORTED = 1;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b1;
|
localparam logic PLIC_SUPPORTED = 1;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b1;
|
localparam logic SPI_SUPPORTED = 1;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
// Bus Interface width
|
// Bus Interface width
|
||||||
localparam AHBW = 32'd32;
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 1;
|
localparam logic SPI_LOOPBACK_TEST = 1;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
@ -155,7 +209,8 @@ localparam PLIC_UART_ID = 32'd10;
|
|||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 1;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 1;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
@ -163,35 +218,11 @@ localparam BTB_SIZE = 32'd10;
|
|||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 1;
|
localparam INSTR_CLASS_PRED = 1;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 1;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'd4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'd2;
|
localparam DIVCOPIES = 32'd2;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 1;
|
|
||||||
localparam ZBB_SUPPORTED = 1;
|
|
||||||
localparam ZBC_SUPPORTED = 1;
|
|
||||||
localparam ZBS_SUPPORTED = 1;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 1;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 1;
|
|
||||||
localparam ZBKC_SUPPORTED = 1;
|
|
||||||
localparam ZBKX_SUPPORTED = 1;
|
|
||||||
localparam ZKND_SUPPORTED = 1;
|
|
||||||
localparam ZKNE_SUPPORTED = 1;
|
|
||||||
localparam ZKNH_SUPPORTED = 1;
|
|
||||||
localparam ZK_SUPPORTED = 1;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -33,34 +33,88 @@ localparam XLEN = 32'd32;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// I
|
// RISC-V configuration per specification
|
||||||
localparam MISA = (32'h00000100);
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZICSR_SUPPORTED = 0;
|
localparam logic E_SUPPORTED = 0;
|
||||||
localparam ZIFENCEI_SUPPORTED = 0;
|
|
||||||
localparam COUNTERS = 0;
|
// Integer instruction set extensions
|
||||||
localparam ZICNTR_SUPPORTED = 0;
|
localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
|
||||||
localparam ZIHPM_SUPPORTED = 0;
|
localparam logic ZICSR_SUPPORTED = 0; // CSR Instructions
|
||||||
localparam ZFH_SUPPORTED = 0;
|
localparam logic ZICCLSM_SUPPORTED = 0; // Misaligned loads/stores
|
||||||
localparam ZFA_SUPPORTED = 0;
|
localparam logic ZICOND_SUPPORTED = 0; // Integer conditional operations
|
||||||
localparam SSTC_SUPPORTED = 0;
|
|
||||||
localparam ZICBOM_SUPPORTED = 0;
|
// Multiplication & division extensions
|
||||||
localparam ZICBOZ_SUPPORTED = 0;
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
localparam ZICBOP_SUPPORTED = 0;
|
localparam logic M_SUPPORTED = 0;
|
||||||
localparam ZICCLSM_SUPPORTED = 0;
|
localparam logic ZMMUL_SUPPORTED = 0;
|
||||||
localparam ZICOND_SUPPORTED = 0;
|
|
||||||
localparam SVPBMT_SUPPORTED = 0;
|
// Atomic extensions
|
||||||
localparam SVNAPOT_SUPPORTED = 0;
|
// A extension is Zaamo + Zalrsc
|
||||||
localparam SVINVAL_SUPPORTED = 0;
|
localparam logic ZAAMO_SUPPORTED = 0;
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
localparam logic ZALRSC_SUPPORTED = 0;
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 0;
|
||||||
|
localparam logic ZBB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBS_SUPPORTED = 0;
|
||||||
|
localparam logic ZBC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 0;
|
||||||
|
localparam logic ZKND_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 0;
|
||||||
|
localparam logic ZCB_SUPPORTED = 0;
|
||||||
|
localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 0; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 0;
|
||||||
|
localparam logic D_SUPPORTED = 0;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 0;
|
||||||
|
localparam logic ZFA_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 0; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 0; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 0;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 0;
|
||||||
|
localparam COUNTERS = 12'd0;
|
||||||
|
|
||||||
|
// Cache-management operation extensions
|
||||||
|
localparam logic ZICBOM_SUPPORTED = 0;
|
||||||
|
localparam logic ZICBOZ_SUPPORTED = 0;
|
||||||
|
localparam logic ZICBOP_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Virtual memory extensions
|
||||||
|
localparam logic SVPBMT_SUPPORTED = 0;
|
||||||
|
localparam logic SVNAPOT_SUPPORTED = 0;
|
||||||
|
localparam logic SVINVAL_SUPPORTED = 0;
|
||||||
|
localparam logic SVADU_SUPPORTED = 0;
|
||||||
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 0;
|
localparam logic BUS_SUPPORTED = 0;
|
||||||
localparam DCACHE_SUPPORTED = 0;
|
localparam logic DCACHE_SUPPORTED = 0;
|
||||||
localparam ICACHE_SUPPORTED = 0;
|
localparam logic ICACHE_SUPPORTED = 0;
|
||||||
localparam VIRTMEM_SUPPORTED = 0;
|
localparam logic VIRTMEM_SUPPORTED = 0;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||||
localparam BIGENDIAN_SUPPORTED = 0;
|
localparam logic BIGENDIAN_SUPPORTED = 0;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd32;
|
localparam ITLB_ENTRIES = 32'd32;
|
||||||
@ -79,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||||
localparam IDIV_ON_FPU = 0;
|
localparam logic IDIV_ON_FPU = 0;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd0;
|
localparam PMP_ENTRIES = 32'd0;
|
||||||
@ -90,57 +144,58 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
|||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
localparam DTIM_SUPPORTED = 1'b1;
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic DTIM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam IROM_SUPPORTED = 1'b1;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic IROM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
localparam logic BOOTROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
localparam logic UNCORE_RAM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b0;
|
localparam logic CLINT_SUPPORTED = 0;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b0;
|
localparam logic GPIO_SUPPORTED = 0;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b0;
|
localparam logic UART_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b0;
|
localparam logic PLIC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b0;
|
localparam logic SPI_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
// Bus Interface width
|
// Bus Interface width
|
||||||
localparam AHBW = 32'd32;
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 1;
|
localparam logic SPI_LOOPBACK_TEST = 1;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
@ -152,10 +207,10 @@ localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
|||||||
localparam PLIC_GPIO_ID = 32'd3;
|
localparam PLIC_GPIO_ID = 32'd3;
|
||||||
localparam PLIC_UART_ID = 32'd10;
|
localparam PLIC_UART_ID = 32'd10;
|
||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
|
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 0;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 0;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
@ -163,35 +218,11 @@ localparam BTB_SIZE = 32'd10;
|
|||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 0;
|
localparam INSTR_CLASS_PRED = 0;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 0;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'h4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'h4;
|
localparam DIVCOPIES = 32'd4;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 0;
|
|
||||||
localparam ZBB_SUPPORTED = 0;
|
|
||||||
localparam ZBC_SUPPORTED = 0;
|
|
||||||
localparam ZBS_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 0;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 0;
|
|
||||||
localparam ZBKC_SUPPORTED = 0;
|
|
||||||
localparam ZBKX_SUPPORTED = 0;
|
|
||||||
localparam ZKNE_SUPPORTED = 0;
|
|
||||||
localparam ZKND_SUPPORTED = 0;
|
|
||||||
localparam ZK_SUPPORTED = 0;
|
|
||||||
localparam ZKNH_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -33,33 +33,88 @@ localparam XLEN = 32'd32;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
|
// RISC-V configuration per specification
|
||||||
localparam ZICSR_SUPPORTED = 1;
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZIFENCEI_SUPPORTED = 1;
|
localparam logic E_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Integer instruction set extensions
|
||||||
|
localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
|
||||||
|
localparam logic ZICSR_SUPPORTED = 1; // CSR Instructions
|
||||||
|
localparam logic ZICCLSM_SUPPORTED = 0; // Misaligned loads/stores
|
||||||
|
localparam logic ZICOND_SUPPORTED = 0; // Integer conditional operations
|
||||||
|
|
||||||
|
// Multiplication & division extensions
|
||||||
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
|
localparam logic M_SUPPORTED = 1;
|
||||||
|
localparam logic ZMMUL_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Atomic extensions
|
||||||
|
// A extension is Zaamo + Zalrsc
|
||||||
|
localparam logic ZAAMO_SUPPORTED = 0;
|
||||||
|
localparam logic ZALRSC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 0;
|
||||||
|
localparam logic ZBB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBS_SUPPORTED = 0;
|
||||||
|
localparam logic ZBC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 0;
|
||||||
|
localparam logic ZKND_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 1;
|
||||||
|
localparam logic ZCB_SUPPORTED = 0;
|
||||||
|
localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 0; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 0;
|
||||||
|
localparam logic D_SUPPORTED = 0;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 0;
|
||||||
|
localparam logic ZFA_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 1; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 1; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 1;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 1;
|
||||||
localparam COUNTERS = 12'd32;
|
localparam COUNTERS = 12'd32;
|
||||||
localparam ZICNTR_SUPPORTED = 1;
|
|
||||||
localparam ZIHPM_SUPPORTED = 1;
|
// Cache-management operation extensions
|
||||||
localparam ZFH_SUPPORTED = 0;
|
localparam logic ZICBOM_SUPPORTED = 0;
|
||||||
localparam ZFA_SUPPORTED = 0;
|
localparam logic ZICBOZ_SUPPORTED = 0;
|
||||||
localparam SSTC_SUPPORTED = 0;
|
localparam logic ZICBOP_SUPPORTED = 0;
|
||||||
localparam ZICBOM_SUPPORTED = 0;
|
|
||||||
localparam ZICBOZ_SUPPORTED = 0;
|
// Virtual memory extensions
|
||||||
localparam ZICBOP_SUPPORTED = 0;
|
localparam logic SVPBMT_SUPPORTED = 0;
|
||||||
localparam ZICCLSM_SUPPORTED = 0;
|
localparam logic SVNAPOT_SUPPORTED = 0;
|
||||||
localparam ZICOND_SUPPORTED = 0;
|
localparam logic SVINVAL_SUPPORTED = 0;
|
||||||
localparam SVPBMT_SUPPORTED = 0;
|
localparam logic SVADU_SUPPORTED = 0;
|
||||||
localparam SVNAPOT_SUPPORTED = 0;
|
|
||||||
localparam SVINVAL_SUPPORTED = 0;
|
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 1;
|
localparam logic BUS_SUPPORTED = 1;
|
||||||
localparam DCACHE_SUPPORTED = 0;
|
localparam logic DCACHE_SUPPORTED = 0;
|
||||||
localparam ICACHE_SUPPORTED = 0;
|
localparam logic ICACHE_SUPPORTED = 0;
|
||||||
localparam VIRTMEM_SUPPORTED = 0;
|
localparam logic VIRTMEM_SUPPORTED = 0;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||||
localparam BIGENDIAN_SUPPORTED = 0;
|
localparam logic BIGENDIAN_SUPPORTED = 0;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd0;
|
localparam ITLB_ENTRIES = 32'd0;
|
||||||
@ -78,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd2;
|
localparam IDIV_BITSPERCYCLE = 32'd2;
|
||||||
localparam IDIV_ON_FPU = 0;
|
localparam logic IDIV_ON_FPU = 0;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd0;
|
localparam PMP_ENTRIES = 32'd0;
|
||||||
@ -89,57 +144,58 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
|||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
localparam DTIM_SUPPORTED = 1'b1;
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic DTIM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam IROM_SUPPORTED = 1'b1;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic IROM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
localparam logic BOOTROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
localparam logic UNCORE_RAM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b1;
|
localparam logic CLINT_SUPPORTED = 1;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b1;
|
localparam logic GPIO_SUPPORTED = 1;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b1;
|
localparam logic UART_SUPPORTED = 1;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b1;
|
localparam logic PLIC_SUPPORTED = 1;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b1;
|
localparam logic SPI_SUPPORTED = 1;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
// Bus Interface width
|
// Bus Interface width
|
||||||
localparam AHBW = 32'd32;
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 1;
|
localparam logic SPI_LOOPBACK_TEST = 1;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
@ -153,7 +209,8 @@ localparam PLIC_UART_ID = 32'd10;
|
|||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 0;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 0;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
@ -161,35 +218,11 @@ localparam BTB_SIZE = 32'd10;
|
|||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 0;
|
localparam INSTR_CLASS_PRED = 0;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 0;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'h4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'h4;
|
localparam DIVCOPIES = 32'd4;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 0;
|
|
||||||
localparam ZBB_SUPPORTED = 0;
|
|
||||||
localparam ZBC_SUPPORTED = 0;
|
|
||||||
localparam ZBS_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 0;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 0;
|
|
||||||
localparam ZBKC_SUPPORTED = 0;
|
|
||||||
localparam ZBKX_SUPPORTED = 0;
|
|
||||||
localparam ZKNE_SUPPORTED = 0;
|
|
||||||
localparam ZKND_SUPPORTED = 0;
|
|
||||||
localparam ZK_SUPPORTED = 0;
|
|
||||||
localparam ZKNH_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -33,34 +33,88 @@ localparam XLEN = 32'd64;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// MISA RISC-V configuration per specification
|
// RISC-V configuration per specification
|
||||||
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZICSR_SUPPORTED = 1;
|
localparam logic E_SUPPORTED = 0;
|
||||||
localparam ZIFENCEI_SUPPORTED = 1;
|
|
||||||
|
// Integer instruction set extensions
|
||||||
|
localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
|
||||||
|
localparam logic ZICSR_SUPPORTED = 1; // CSR Instructions
|
||||||
|
localparam logic ZICCLSM_SUPPORTED = 1; // Misaligned loads/stores
|
||||||
|
localparam logic ZICOND_SUPPORTED = 1; // Integer conditional operations
|
||||||
|
|
||||||
|
// Multiplication & division extensions
|
||||||
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
|
localparam logic M_SUPPORTED = 1;
|
||||||
|
localparam logic ZMMUL_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Atomic extensions
|
||||||
|
// A extension is Zaamo + Zalrsc
|
||||||
|
localparam logic ZAAMO_SUPPORTED = 1;
|
||||||
|
localparam logic ZALRSC_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 1;
|
||||||
|
localparam logic ZBB_SUPPORTED = 1;
|
||||||
|
localparam logic ZBS_SUPPORTED = 1;
|
||||||
|
localparam logic ZBC_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 1;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 1;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 1;
|
||||||
|
localparam logic ZKND_SUPPORTED = 1;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 1;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 1;
|
||||||
|
localparam logic ZCB_SUPPORTED = 1;
|
||||||
|
localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 1; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 1;
|
||||||
|
localparam logic D_SUPPORTED = 1;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 1;
|
||||||
|
localparam logic ZFA_SUPPORTED = 1;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 1; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 1; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 1;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 1;
|
||||||
localparam COUNTERS = 12'd32;
|
localparam COUNTERS = 12'd32;
|
||||||
localparam ZICNTR_SUPPORTED = 1;
|
|
||||||
localparam ZIHPM_SUPPORTED = 1;
|
// Cache-management operation extensions
|
||||||
localparam ZFH_SUPPORTED = 1;
|
localparam logic ZICBOM_SUPPORTED = 1;
|
||||||
localparam ZFA_SUPPORTED = 1;
|
localparam logic ZICBOZ_SUPPORTED = 1;
|
||||||
localparam SSTC_SUPPORTED = 1;
|
localparam logic ZICBOP_SUPPORTED = 1;
|
||||||
localparam ZICBOM_SUPPORTED = 1;
|
|
||||||
localparam ZICBOZ_SUPPORTED = 1;
|
// Virtual memory extensions
|
||||||
localparam ZICBOP_SUPPORTED = 1;
|
localparam logic SVPBMT_SUPPORTED = 1;
|
||||||
localparam ZICCLSM_SUPPORTED = 1;
|
localparam logic SVNAPOT_SUPPORTED = 1;
|
||||||
localparam ZICOND_SUPPORTED = 1;
|
localparam logic SVINVAL_SUPPORTED = 1;
|
||||||
localparam SVPBMT_SUPPORTED = 1;
|
localparam logic SVADU_SUPPORTED = 1;
|
||||||
localparam SVNAPOT_SUPPORTED = 1;
|
|
||||||
localparam SVINVAL_SUPPORTED = 1;
|
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 1;
|
localparam logic BUS_SUPPORTED = 1;
|
||||||
localparam DCACHE_SUPPORTED = 1;
|
localparam logic DCACHE_SUPPORTED = 1;
|
||||||
localparam ICACHE_SUPPORTED = 1;
|
localparam logic ICACHE_SUPPORTED = 1;
|
||||||
localparam VIRTMEM_SUPPORTED = 1;
|
localparam logic VIRTMEM_SUPPORTED = 1;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||||
localparam BIGENDIAN_SUPPORTED = 1;
|
localparam logic BIGENDIAN_SUPPORTED = 1;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd32;
|
localparam ITLB_ENTRIES = 32'd32;
|
||||||
@ -79,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||||
localparam IDIV_ON_FPU = 1;
|
localparam logic IDIV_ON_FPU = 1;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd16;
|
localparam PMP_ENTRIES = 32'd16;
|
||||||
@ -87,62 +141,61 @@ localparam PMP_ENTRIES = 32'd16;
|
|||||||
// Address space
|
// Address space
|
||||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
||||||
|
|
||||||
// Bus Interface width
|
|
||||||
localparam AHBW = 32'd64;
|
|
||||||
|
|
||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Physical Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
|
|
||||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam DTIM_SUPPORTED = 1'b0;
|
localparam logic DTIM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam IROM_SUPPORTED = 1'b0;
|
localparam logic IROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
localparam logic BOOTROM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
localparam logic UNCORE_RAM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b1;
|
localparam logic CLINT_SUPPORTED = 1;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b1;
|
localparam logic GPIO_SUPPORTED = 1;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b1;
|
localparam logic UART_SUPPORTED = 1;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b1;
|
localparam logic PLIC_SUPPORTED = 1;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b1;
|
localparam logic SPI_SUPPORTED = 1;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
|
// Bus Interface width
|
||||||
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 1;
|
localparam logic SPI_LOOPBACK_TEST = 1;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
@ -156,44 +209,20 @@ localparam PLIC_UART_ID = 32'd10;
|
|||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 1;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 1;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
localparam BTB_SIZE = 32'd10;
|
localparam BTB_SIZE = 32'd10;
|
||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 1;
|
localparam INSTR_CLASS_PRED = 1;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 1;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'h4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'h4;
|
localparam DIVCOPIES = 32'd4;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 1;
|
|
||||||
localparam ZBB_SUPPORTED = 1;
|
|
||||||
localparam ZBC_SUPPORTED = 1;
|
|
||||||
localparam ZBS_SUPPORTED = 1;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 1;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 1;
|
|
||||||
localparam ZBKC_SUPPORTED = 1;
|
|
||||||
localparam ZBKX_SUPPORTED = 1;
|
|
||||||
localparam ZKND_SUPPORTED = 1;
|
|
||||||
localparam ZKNE_SUPPORTED = 1;
|
|
||||||
localparam ZKNH_SUPPORTED = 1;
|
|
||||||
localparam ZK_SUPPORTED = 1;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|
||||||
|
|||||||
@ -2,10 +2,10 @@
|
|||||||
// config.vh
|
// config.vh
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 4 January 2021
|
// Written: David_Harris@hmc.edu 4 January 2021
|
||||||
// Modified:
|
// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
|
||||||
//
|
//
|
||||||
// Purpose: Specify which features are configured
|
// Purpose: Specify which features of Wally are enabled and set
|
||||||
// Macros to determine which modes are supported based on MISA
|
// configuration parameters
|
||||||
//
|
//
|
||||||
// A component of the Wally configurable RISC-V project.
|
// A component of the Wally configurable RISC-V project.
|
||||||
//
|
//
|
||||||
@ -33,34 +33,88 @@ localparam XLEN = 32'd64;
|
|||||||
// IEEE 754 compliance
|
// IEEE 754 compliance
|
||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// MISA RISC-V configuration per specification
|
// RISC-V configuration per specification
|
||||||
localparam MISA = (32'h00000100);
|
// Base instruction set (defaults to I if E is not supported)
|
||||||
localparam ZICSR_SUPPORTED = 0;
|
localparam logic E_SUPPORTED = 0;
|
||||||
localparam ZIFENCEI_SUPPORTED = 0;
|
|
||||||
localparam COUNTERS = 0;
|
// Integer instruction set extensions
|
||||||
localparam ZICNTR_SUPPORTED = 0;
|
localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
|
||||||
localparam ZIHPM_SUPPORTED = 0;
|
localparam logic ZICSR_SUPPORTED = 0; // CSR Instructions
|
||||||
localparam ZFH_SUPPORTED = 0;
|
localparam logic ZICCLSM_SUPPORTED = 0; // Misaligned loads/stores
|
||||||
localparam ZFA_SUPPORTED = 0;
|
localparam logic ZICOND_SUPPORTED = 0; // Integer conditional operations
|
||||||
localparam SSTC_SUPPORTED = 0;
|
|
||||||
localparam ZICBOM_SUPPORTED = 0;
|
// Multiplication & division extensions
|
||||||
localparam ZICBOZ_SUPPORTED = 0;
|
// M implies (and in the configuration file requires) Zmmul
|
||||||
localparam ZICBOP_SUPPORTED = 0;
|
localparam logic M_SUPPORTED = 0;
|
||||||
localparam ZICCLSM_SUPPORTED = 0;
|
localparam logic ZMMUL_SUPPORTED = 0;
|
||||||
localparam ZICOND_SUPPORTED = 0;
|
|
||||||
localparam SVPBMT_SUPPORTED = 0;
|
// Atomic extensions
|
||||||
localparam SVNAPOT_SUPPORTED = 0;
|
// A extension is Zaamo + Zalrsc
|
||||||
localparam SVINVAL_SUPPORTED = 0;
|
localparam logic ZAAMO_SUPPORTED = 0;
|
||||||
localparam ZAAMO_SUPPORTED = 0;
|
localparam logic ZALRSC_SUPPORTED = 0;
|
||||||
localparam ZALRSC_SUPPORTED = 0;
|
|
||||||
|
// Bit manipulation extensions
|
||||||
|
// B extension is Zba + Zbb + Zbs
|
||||||
|
localparam logic ZBA_SUPPORTED = 0;
|
||||||
|
localparam logic ZBB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBS_SUPPORTED = 0;
|
||||||
|
localparam logic ZBC_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Scalar crypto extensions
|
||||||
|
// Zkn is all 6 of these
|
||||||
|
localparam logic ZBKB_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKC_SUPPORTED = 0;
|
||||||
|
localparam logic ZBKX_SUPPORTED = 0;
|
||||||
|
localparam logic ZKND_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNE_SUPPORTED = 0;
|
||||||
|
localparam logic ZKNH_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Compressed extensions
|
||||||
|
// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
|
||||||
|
// All compressed extensions require Zca
|
||||||
|
localparam logic ZCA_SUPPORTED = 0;
|
||||||
|
localparam logic ZCB_SUPPORTED = 0;
|
||||||
|
localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
|
||||||
|
localparam logic ZCD_SUPPORTED = 0; // requires D
|
||||||
|
|
||||||
|
// Floating point extensions
|
||||||
|
localparam logic F_SUPPORTED = 0;
|
||||||
|
localparam logic D_SUPPORTED = 0;
|
||||||
|
localparam logic Q_SUPPORTED = 0;
|
||||||
|
localparam logic ZFH_SUPPORTED = 0;
|
||||||
|
localparam logic ZFA_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// privilege modes
|
||||||
|
localparam logic S_SUPPORTED = 0; // Supervisor mode
|
||||||
|
localparam logic U_SUPPORTED = 0; // User mode
|
||||||
|
|
||||||
|
// Supervisor level extensions
|
||||||
|
localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
|
||||||
|
|
||||||
|
// Hardware performance counters
|
||||||
|
localparam logic ZICNTR_SUPPORTED = 0;
|
||||||
|
localparam logic ZIHPM_SUPPORTED = 0;
|
||||||
|
localparam COUNTERS = 12'd0;
|
||||||
|
|
||||||
|
// Cache-management operation extensions
|
||||||
|
localparam logic ZICBOM_SUPPORTED = 0;
|
||||||
|
localparam logic ZICBOZ_SUPPORTED = 0;
|
||||||
|
localparam logic ZICBOP_SUPPORTED = 0;
|
||||||
|
|
||||||
|
// Virtual memory extensions
|
||||||
|
localparam logic SVPBMT_SUPPORTED = 0;
|
||||||
|
localparam logic SVNAPOT_SUPPORTED = 0;
|
||||||
|
localparam logic SVINVAL_SUPPORTED = 0;
|
||||||
|
localparam logic SVADU_SUPPORTED = 0;
|
||||||
|
|
||||||
|
|
||||||
// LSU microarchitectural Features
|
// LSU microarchitectural Features
|
||||||
localparam BUS_SUPPORTED = 0;
|
localparam logic BUS_SUPPORTED = 0;
|
||||||
localparam DCACHE_SUPPORTED = 0;
|
localparam logic DCACHE_SUPPORTED = 0;
|
||||||
localparam ICACHE_SUPPORTED = 0;
|
localparam logic ICACHE_SUPPORTED = 0;
|
||||||
localparam VIRTMEM_SUPPORTED = 0;
|
localparam logic VIRTMEM_SUPPORTED = 0;
|
||||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||||
localparam BIGENDIAN_SUPPORTED = 0;
|
localparam logic BIGENDIAN_SUPPORTED = 0;
|
||||||
|
|
||||||
// TLB configuration. Entries should be a power of 2
|
// TLB configuration. Entries should be a power of 2
|
||||||
localparam ITLB_ENTRIES = 32'd0;
|
localparam ITLB_ENTRIES = 32'd0;
|
||||||
@ -79,7 +133,7 @@ localparam CACHE_SRAMLEN = 32'd128;
|
|||||||
// Integer Divider Configuration
|
// Integer Divider Configuration
|
||||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||||
localparam IDIV_ON_FPU = 0;
|
localparam logic IDIV_ON_FPU = 0;
|
||||||
|
|
||||||
// Legal number of PMP entries are 0, 16, or 64
|
// Legal number of PMP entries are 0, 16, or 64
|
||||||
localparam PMP_ENTRIES = 32'd0;
|
localparam PMP_ENTRIES = 32'd0;
|
||||||
@ -87,62 +141,61 @@ localparam PMP_ENTRIES = 32'd0;
|
|||||||
// Address space
|
// Address space
|
||||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
||||||
|
|
||||||
// Bus Interface width
|
|
||||||
localparam AHBW = (XLEN);
|
|
||||||
|
|
||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||||
|
|
||||||
// Peripheral Physiccal Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
|
|
||||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||||
localparam DTIM_SUPPORTED = 1'b1;
|
localparam logic DTIM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||||
localparam IROM_SUPPORTED = 1'b1;
|
localparam logic IROM_SUPPORTED = 1;
|
||||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
localparam logic BOOTROM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||||
localparam BOOTROM_PRELOAD = 1'b0;
|
localparam BOOTROM_PRELOAD = 1'b0;
|
||||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
localparam logic UNCORE_RAM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||||
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
localparam UNCORE_RAM_PRELOAD = 1'b0;
|
||||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
localparam logic EXT_MEM_SUPPORTED = 0;
|
||||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||||
localparam CLINT_SUPPORTED = 1'b0;
|
localparam logic CLINT_SUPPORTED = 0;
|
||||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||||
localparam GPIO_SUPPORTED = 1'b0;
|
localparam logic GPIO_SUPPORTED = 0;
|
||||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||||
localparam UART_SUPPORTED = 1'b0;
|
localparam logic UART_SUPPORTED = 0;
|
||||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||||
localparam PLIC_SUPPORTED = 1'b0;
|
localparam logic PLIC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||||
localparam SDC_SUPPORTED = 1'b0;
|
localparam logic SDC_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
localparam logic [63:0] SDC_BASE = 64'h00013000;
|
||||||
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
|
||||||
localparam SPI_SUPPORTED = 1'b0;
|
localparam logic SPI_SUPPORTED = 0;
|
||||||
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
localparam logic [63:0] SPI_BASE = 64'h10040000;
|
||||||
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
|
||||||
|
|
||||||
|
// Bus Interface width
|
||||||
|
localparam AHBW = (XLEN);
|
||||||
|
|
||||||
// Test modes
|
// Test modes
|
||||||
|
|
||||||
// AHB
|
// AHB
|
||||||
localparam RAM_LATENCY = 32'b0;
|
localparam RAM_LATENCY = 32'b0;
|
||||||
localparam BURST_EN = 1;
|
localparam logic BURST_EN = 1;
|
||||||
|
|
||||||
// Tie GPIO outputs back to inputs
|
// Tie GPIO outputs back to inputs
|
||||||
localparam GPIO_LOOPBACK_TEST = 1;
|
localparam logic GPIO_LOOPBACK_TEST = 1;
|
||||||
localparam SPI_LOOPBACK_TEST = 1;
|
localparam logic SPI_LOOPBACK_TEST = 1;
|
||||||
|
|
||||||
// Hardware configuration
|
// Hardware configuration
|
||||||
localparam UART_PRESCALE = 32'd1;
|
localparam UART_PRESCALE = 32'd1;
|
||||||
@ -156,7 +209,8 @@ localparam PLIC_UART_ID = 32'd10;
|
|||||||
localparam PLIC_SPI_ID = 32'd6;
|
localparam PLIC_SPI_ID = 32'd6;
|
||||||
localparam PLIC_SDC_ID = 32'd9;
|
localparam PLIC_SDC_ID = 32'd9;
|
||||||
|
|
||||||
localparam BPRED_SUPPORTED = 0;
|
// Branch prediction
|
||||||
|
localparam logic BPRED_SUPPORTED = 0;
|
||||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||||
localparam BPRED_SIZE = 32'd10;
|
localparam BPRED_SIZE = 32'd10;
|
||||||
localparam BPRED_NUM_LHR = 32'd6;
|
localparam BPRED_NUM_LHR = 32'd6;
|
||||||
@ -164,35 +218,11 @@ localparam BTB_SIZE = 32'd10;
|
|||||||
localparam RAS_SIZE = 32'd16;
|
localparam RAS_SIZE = 32'd16;
|
||||||
localparam INSTR_CLASS_PRED = 0;
|
localparam INSTR_CLASS_PRED = 0;
|
||||||
|
|
||||||
localparam SVADU_SUPPORTED = 0;
|
|
||||||
localparam ZMMUL_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// FPU division architecture
|
// FPU division architecture
|
||||||
localparam RADIX = 32'h4;
|
localparam RADIX = 32'd4;
|
||||||
localparam DIVCOPIES = 32'h4;
|
localparam DIVCOPIES = 32'd4;
|
||||||
|
|
||||||
// bit manipulation
|
|
||||||
localparam ZBA_SUPPORTED = 0;
|
|
||||||
localparam ZBB_SUPPORTED = 0;
|
|
||||||
localparam ZBC_SUPPORTED = 0;
|
|
||||||
localparam ZBS_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// New compressed instructions
|
|
||||||
localparam ZCB_SUPPORTED = 0;
|
|
||||||
localparam ZCA_SUPPORTED = 0;
|
|
||||||
localparam ZCF_SUPPORTED = 0;
|
|
||||||
localparam ZCD_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// K extension instructions
|
|
||||||
localparam ZBKB_SUPPORTED = 0;
|
|
||||||
localparam ZBKC_SUPPORTED = 0;
|
|
||||||
localparam ZBKX_SUPPORTED = 0;
|
|
||||||
localparam ZKNE_SUPPORTED = 0;
|
|
||||||
localparam ZKND_SUPPORTED = 0;
|
|
||||||
localparam ZK_SUPPORTED = 0;
|
|
||||||
localparam ZKNH_SUPPORTED = 0;
|
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
localparam USE_SRAM = 0;
|
localparam logic USE_SRAM = 0;
|
||||||
|
|
||||||
`include "config-shared.vh"
|
`include "config-shared.vh"
|
||||||
|
|||||||
@ -24,20 +24,15 @@ localparam SV39 = 4'd8;
|
|||||||
localparam SV48 = 4'd9;
|
localparam SV48 = 4'd9;
|
||||||
|
|
||||||
// macros to define supported modes
|
// macros to define supported modes
|
||||||
localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
|
localparam logic I_SUPPORTED = (!E_SUPPORTED);
|
||||||
localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
|
localparam logic A_SUPPORTED = (ZAAMO_SUPPORTED & ZALRSC_SUPPORTED);
|
||||||
localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
|
localparam logic B_SUPPORTED = ((ZBA_SUPPORTED & ZBB_SUPPORTED & ZBS_SUPPORTED));
|
||||||
localparam COMPRESSED_SUPPORTED = C_SUPPORTED | ZCA_SUPPORTED;
|
localparam logic C_SUPPORTED = ZCA_SUPPORTED & (D_SUPPORTED ? ZCD_SUPPORTED : 1) & (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
|
||||||
localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
|
localparam logic ZKN_SUPPORTED = (ZBKB_SUPPORTED & ZBKC_SUPPORTED & ZBKX_SUPPORTED & ZKND_SUPPORTED & ZKNE_SUPPORTED & ZKNH_SUPPORTED);
|
||||||
localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
|
|
||||||
localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
|
// Configure MISA based on supported extensions
|
||||||
localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
|
localparam MISA = {6'b0, 5'b0, U_SUPPORTED, 1'b0, S_SUPPORTED, 1'b0, Q_SUPPORTED, 3'b0, M_SUPPORTED, 3'b0, I_SUPPORTED, 2'b0,
|
||||||
localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED));
|
F_SUPPORTED, E_SUPPORTED, D_SUPPORTED, C_SUPPORTED, B_SUPPORTED, A_SUPPORTED};
|
||||||
localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
|
|
||||||
localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
|
|
||||||
localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
|
|
||||||
localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
|
|
||||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
|
||||||
|
|
||||||
// logarithm of XLEN, used for number of index bits to select
|
// logarithm of XLEN, used for number of index bits to select
|
||||||
localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
|
localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
|
||||||
|
|||||||
@ -121,7 +121,7 @@ localparam cvw_t P = '{
|
|||||||
ZKND_SUPPORTED: ZKND_SUPPORTED,
|
ZKND_SUPPORTED: ZKND_SUPPORTED,
|
||||||
ZKNE_SUPPORTED: ZKNE_SUPPORTED,
|
ZKNE_SUPPORTED: ZKNE_SUPPORTED,
|
||||||
ZKNH_SUPPORTED: ZKNH_SUPPORTED,
|
ZKNH_SUPPORTED: ZKNH_SUPPORTED,
|
||||||
ZK_SUPPORTED : ZK_SUPPORTED,
|
ZKN_SUPPORTED : ZKN_SUPPORTED,
|
||||||
USE_SRAM : USE_SRAM,
|
USE_SRAM : USE_SRAM,
|
||||||
M_MODE : M_MODE,
|
M_MODE : M_MODE,
|
||||||
S_MODE : S_MODE,
|
S_MODE : S_MODE,
|
||||||
@ -140,12 +140,10 @@ localparam cvw_t P = '{
|
|||||||
A_SUPPORTED : A_SUPPORTED,
|
A_SUPPORTED : A_SUPPORTED,
|
||||||
B_SUPPORTED : B_SUPPORTED,
|
B_SUPPORTED : B_SUPPORTED,
|
||||||
C_SUPPORTED : C_SUPPORTED,
|
C_SUPPORTED : C_SUPPORTED,
|
||||||
COMPRESSED_SUPPORTED : COMPRESSED_SUPPORTED,
|
|
||||||
D_SUPPORTED : D_SUPPORTED,
|
D_SUPPORTED : D_SUPPORTED,
|
||||||
E_SUPPORTED : E_SUPPORTED,
|
E_SUPPORTED : E_SUPPORTED,
|
||||||
F_SUPPORTED : F_SUPPORTED,
|
F_SUPPORTED : F_SUPPORTED,
|
||||||
I_SUPPORTED : I_SUPPORTED,
|
I_SUPPORTED : I_SUPPORTED,
|
||||||
K_SUPPORTED : K_SUPPORTED,
|
|
||||||
M_SUPPORTED : M_SUPPORTED,
|
M_SUPPORTED : M_SUPPORTED,
|
||||||
Q_SUPPORTED : Q_SUPPORTED,
|
Q_SUPPORTED : Q_SUPPORTED,
|
||||||
S_SUPPORTED : S_SUPPORTED,
|
S_SUPPORTED : S_SUPPORTED,
|
||||||
|
|||||||
@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
|
|||||||
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
|
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
|
||||||
#export OTHERFLAGS=""
|
#export OTHERFLAGS=""
|
||||||
|
|
||||||
vsim -c -do "do wally.do buildroot buildroot testbench --lockstep"
|
vsim -do "do wally.do buildroot buildroot testbench --lockstep +acc -GDEBUG=1"
|
||||||
|
|||||||
@ -143,7 +143,7 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CF
|
|||||||
|
|
||||||
# start and run simulation
|
# start and run simulation
|
||||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||||
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${lst} -o testbenchopt ${CoverageVoptArg}
|
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} -o testbenchopt ${CoverageVoptArg}
|
||||||
|
|
||||||
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} -suppress 3829 ${CoverageVsimArg}
|
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} -suppress 3829 ${CoverageVsimArg}
|
||||||
|
|
||||||
|
|||||||
@ -189,7 +189,7 @@ typedef struct packed {
|
|||||||
logic ZKND_SUPPORTED;
|
logic ZKND_SUPPORTED;
|
||||||
logic ZKNE_SUPPORTED;
|
logic ZKNE_SUPPORTED;
|
||||||
logic ZKNH_SUPPORTED;
|
logic ZKNH_SUPPORTED;
|
||||||
logic ZK_SUPPORTED;
|
logic ZKN_SUPPORTED;
|
||||||
|
|
||||||
// Memory synthesis configuration
|
// Memory synthesis configuration
|
||||||
logic USE_SRAM;
|
logic USE_SRAM;
|
||||||
@ -220,12 +220,10 @@ typedef struct packed {
|
|||||||
logic A_SUPPORTED;
|
logic A_SUPPORTED;
|
||||||
logic B_SUPPORTED;
|
logic B_SUPPORTED;
|
||||||
logic C_SUPPORTED;
|
logic C_SUPPORTED;
|
||||||
logic COMPRESSED_SUPPORTED; // C or ZCA
|
|
||||||
logic D_SUPPORTED;
|
logic D_SUPPORTED;
|
||||||
logic E_SUPPORTED;
|
logic E_SUPPORTED;
|
||||||
logic F_SUPPORTED;
|
logic F_SUPPORTED;
|
||||||
logic I_SUPPORTED;
|
logic I_SUPPORTED;
|
||||||
logic K_SUPPORTED;
|
|
||||||
logic M_SUPPORTED;
|
logic M_SUPPORTED;
|
||||||
logic Q_SUPPORTED;
|
logic Q_SUPPORTED;
|
||||||
logic S_SUPPORTED;
|
logic S_SUPPORTED;
|
||||||
|
|||||||
@ -55,7 +55,7 @@ module icpred import cvw::*; #(parameter cvw_t P,
|
|||||||
logic cjal, cj, cjr, cjalr, CJumpF, CBranchF;
|
logic cjal, cj, cjr, cjalr, CJumpF, CBranchF;
|
||||||
logic NCJumpF, NCBranchF;
|
logic NCJumpF, NCBranchF;
|
||||||
|
|
||||||
if(P.COMPRESSED_SUPPORTED) begin
|
if(P.ZCA_SUPPORTED) begin
|
||||||
logic [4:0] CompressedOpcF;
|
logic [4:0] CompressedOpcF;
|
||||||
assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
|
assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
|
||||||
assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
|
assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
|
||||||
@ -71,13 +71,13 @@ module icpred import cvw::*; #(parameter cvw_t P,
|
|||||||
assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
|
assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
|
||||||
assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
|
assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
|
||||||
|
|
||||||
assign BPBranchF = NCBranchF | (P.COMPRESSED_SUPPORTED & CBranchF);
|
assign BPBranchF = NCBranchF | (P.ZCA_SUPPORTED & CBranchF);
|
||||||
assign BPJumpF = NCJumpF | (P.COMPRESSED_SUPPORTED & (CJumpF));
|
assign BPJumpF = NCJumpF | (P.ZCA_SUPPORTED & (CJumpF));
|
||||||
assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
|
assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
|
||||||
(P.COMPRESSED_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
|
(P.ZCA_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
|
||||||
|
|
||||||
assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
|
assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
|
||||||
(P.COMPRESSED_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
|
(P.ZCA_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
|
||||||
|
|
||||||
end else begin
|
end else begin
|
||||||
// This section connects the BTB's instruction class prediction.
|
// This section connects the BTB's instruction class prediction.
|
||||||
|
|||||||
@ -89,7 +89,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||||
end
|
end
|
||||||
5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
5'b00001: if (P.ZCD_SUPPORTED)
|
||||||
InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
|
InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
|
||||||
else begin // unsupported instruction
|
else begin // unsupported instruction
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -97,7 +97,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
|
5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
|
||||||
5'b00011: if (P.XLEN==32)
|
5'b00011: if (P.XLEN==32)
|
||||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
if (P.ZCF_SUPPORTED)
|
||||||
InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
|
InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
|
||||||
else begin
|
else begin
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -125,7 +125,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||||
end
|
end
|
||||||
5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
5'b00101: if (P.ZCD_SUPPORTED)
|
||||||
InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
|
InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
|
||||||
else begin // unsupported instruction
|
else begin // unsupported instruction
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -133,7 +133,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
|
5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
|
||||||
5'b00111: if (P.XLEN==32)
|
5'b00111: if (P.XLEN==32)
|
||||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
if (P.ZCF_SUPPORTED)
|
||||||
InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
|
InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
|
||||||
else begin
|
else begin
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -173,17 +173,17 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
|
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
|
||||||
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
|
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
|
||||||
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
|
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
|
||||||
else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED)
|
else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||||
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
|
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
|
||||||
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
|
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
|
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
|
||||||
else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED)
|
else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||||
InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
|
InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
|
||||||
else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
|
else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
|
||||||
InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
|
InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
|
||||||
else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32)
|
else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32)
|
||||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
|
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
|
||||||
else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED)
|
else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED)
|
||||||
InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
|
InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
|
||||||
else begin // reserved
|
else begin // reserved
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -197,7 +197,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
||||||
5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
||||||
5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
||||||
5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
5'b10001: if (P.ZCD_SUPPORTED)
|
||||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||||
else begin // unsupported instruction
|
else begin // unsupported instruction
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -205,7 +205,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||||
5'b10011: if (P.XLEN == 32)
|
5'b10011: if (P.XLEN == 32)
|
||||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
if (P.ZCF_SUPPORTED)
|
||||||
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||||
else begin
|
else begin
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -226,7 +226,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
|
InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
|
||||||
else
|
else
|
||||||
InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
||||||
5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
5'b10101: if (P.ZCD_SUPPORTED)
|
||||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||||
else begin // unsupported instruction
|
else begin // unsupported instruction
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
@ -234,7 +234,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
||||||
5'b10111: if (P.XLEN==32)
|
5'b10111: if (P.XLEN==32)
|
||||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
if (P.ZCF_SUPPORTED)
|
||||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||||
else begin
|
else begin
|
||||||
IllegalCompInstrD = 1'b1;
|
IllegalCompInstrD = 1'b1;
|
||||||
|
|||||||
@ -147,7 +147,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// Spill Support
|
// Spill Support
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
if(P.COMPRESSED_SUPPORTED) begin : Spill
|
if(P.ZCA_SUPPORTED) begin : Spill
|
||||||
spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF,
|
spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF,
|
||||||
.IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
|
.IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
|
||||||
end else begin : NoSpill
|
end else begin : NoSpill
|
||||||
@ -321,7 +321,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
|
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
|
||||||
assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
|
assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
|
||||||
|
|
||||||
if (P.COMPRESSED_SUPPORTED) begin: pcadd
|
if (P.ZCA_SUPPORTED) begin: pcadd
|
||||||
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
|
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
|
||||||
// Speeds up critical path as compared to selecting adder input based on CompressedF
|
// Speeds up critical path as compared to selecting adder input based on CompressedF
|
||||||
always_comb
|
always_comb
|
||||||
@ -373,7 +373,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
||||||
|
|
||||||
// expand 16-bit compressed instructions to 32 bits
|
// expand 16-bit compressed instructions to 32 bits
|
||||||
if (P.COMPRESSED_SUPPORTED) begin: decomp
|
if (P.ZCA_SUPPORTED) begin: decomp
|
||||||
logic IllegalCompInstrD;
|
logic IllegalCompInstrD;
|
||||||
decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||||
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||||
@ -393,7 +393,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
|
// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
|
||||||
// Spec 3.1.14
|
// Spec 3.1.14
|
||||||
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
|
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
|
||||||
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
|
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.ZCA_SUPPORTED) & PCSrcE;
|
||||||
flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
|
flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
|
||||||
|
|
||||||
// Instruction and PC pipeline registers flush to NOP, not zero
|
// Instruction and PC pipeline registers flush to NOP, not zero
|
||||||
@ -412,7 +412,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
else assign PCM = '0;
|
else assign PCM = '0;
|
||||||
|
|
||||||
// If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4
|
// If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4
|
||||||
if (P.COMPRESSED_SUPPORTED) begin
|
if (P.ZCA_SUPPORTED) begin
|
||||||
logic CompressedD; // instruction is compressed
|
logic CompressedD; // instruction is compressed
|
||||||
flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
|
flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
|
||||||
flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
|
flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
|
||||||
@ -423,7 +423,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
|
|
||||||
// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
|
// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
|
||||||
if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED | 1) begin
|
if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
|
||||||
logic CompressedM; // instruction is compressed
|
logic CompressedM; // instruction is compressed
|
||||||
flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
|
flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
|
||||||
flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
||||||
|
|||||||
@ -52,7 +52,7 @@ module irom import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
// If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
|
// If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
|
||||||
// The spill logic will handle merging the two together.
|
// The spill logic will handle merging the two together.
|
||||||
if (P.COMPRESSED_SUPPORTED) begin
|
if (P.ZCA_SUPPORTED) begin
|
||||||
flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
|
flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
|
||||||
assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
|
assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
|
||||||
end else
|
end else
|
||||||
|
|||||||
@ -58,7 +58,7 @@ module mdu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
|
// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
|
||||||
// When IDIV_ON_FPU is set, use the FPU divider instead
|
// When IDIV_ON_FPU is set, use the FPU divider instead
|
||||||
// In ZMMUL, with M_SUPPORTED = 0, omit the divider
|
// In ZMMUL, with M_SUPPORTED = 0, omit the divider
|
||||||
if ((P.IDIV_ON_FPU & P.F_SUPPORTED) || (!P.M_SUPPORTED)) begin:nodiv
|
if ((P.IDIV_ON_FPU & P.F_SUPPORTED) | (!P.M_SUPPORTED)) begin:nodiv
|
||||||
assign QuotM = '0;
|
assign QuotM = '0;
|
||||||
assign RemM = '0;
|
assign RemM = '0;
|
||||||
assign DivBusyE = 1'b0;
|
assign DivBusyE = 1'b0;
|
||||||
|
|||||||
@ -200,7 +200,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||||||
|
|
||||||
assign CSRAdrM = InstrM[31:20];
|
assign CSRAdrM = InstrM[31:20];
|
||||||
assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
|
assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
|
||||||
assign NextEPCM = P.COMPRESSED_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
|
assign NextEPCM = P.ZCA_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
|
||||||
assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
|
assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
|
||||||
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
||||||
assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);
|
assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);
|
||||||
|
|||||||
@ -96,7 +96,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||||||
// Constants
|
// Constants
|
||||||
localparam ZERO = {(P.XLEN){1'b0}};
|
localparam ZERO = {(P.XLEN){1'b0}};
|
||||||
// when compressed instructions are supported, there can't be misaligned instructions
|
// when compressed instructions are supported, there can't be misaligned instructions
|
||||||
localparam MEDELEG_MASK = P.COMPRESSED_SUPPORTED ? 16'hB3FE : 16'hB3FF;
|
localparam MEDELEG_MASK = P.ZCA_SUPPORTED ? 16'hB3FE : 16'hB3FF;
|
||||||
localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable
|
localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable
|
||||||
|
|
||||||
// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
|
// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
|
||||||
|
|||||||
@ -314,7 +314,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
|
|
||||||
// multiply/divide unit
|
// multiply/divide unit
|
||||||
if (P.M_SUPPORTED | P.ZMMUL_SUPPORTED) begin:mdu
|
if (P.ZMMUL_SUPPORTED) begin:mdu
|
||||||
mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||||
.Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
|
.Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
|
||||||
|
|||||||
@ -58,17 +58,17 @@ module instrNameDecTB(
|
|||||||
else if (funct7[6:1] == 6'b010010) name = "BCLRI";
|
else if (funct7[6:1] == 6'b010010) name = "BCLRI";
|
||||||
else if (funct7[6:1] == 6'b011010) name = "BINVI";
|
else if (funct7[6:1] == 6'b011010) name = "BINVI";
|
||||||
else if (funct7[6:1] == 6'b001010) name = "BSETI";
|
else if (funct7[6:1] == 6'b001010) name = "BSETI";
|
||||||
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP";
|
else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "ZIP";
|
||||||
else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM";
|
else if (funct7 == 7'b0011000 & rs2 == 5'b00000) name = "AES64IM";
|
||||||
else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I";
|
else if (funct7 == 7'b0011000 & rs2[4] == 1'b1) name = "AES64KS1I";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00010) name = "SHA256SIG0";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00011) name = "SHA256SIG1";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00000) name = "SHA256SUM0";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00001) name = "SHA256SUM1";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00110) name = "SHA512SIG0";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00111) name = "SHA512SIG1";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00100) name = "SHA512SUM0";
|
||||||
else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1";
|
else if (funct7 == 7'b0001000 & rs2 == 5'b00101) name = "SHA512SUM1";
|
||||||
else if (funct7 == 7'b0110000) begin
|
else if (funct7 == 7'b0110000) begin
|
||||||
case (rs2)
|
case (rs2)
|
||||||
5'b00000: name = "CLZ";
|
5'b00000: name = "CLZ";
|
||||||
@ -89,7 +89,7 @@ module instrNameDecTB(
|
|||||||
else if (funct7[6:1] == 6'b010010) name = "BEXTI";
|
else if (funct7[6:1] == 6'b010010) name = "BEXTI";
|
||||||
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
|
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
|
||||||
else if (imm == 12'b011010000111) name = "BREV8";
|
else if (imm == 12'b011010000111) name = "BREV8";
|
||||||
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP";
|
else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "UNZIP";
|
||||||
else name = "ILLEGAL";
|
else name = "ILLEGAL";
|
||||||
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
|
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
|
||||||
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
|
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
|
||||||
@ -181,9 +181,9 @@ module instrNameDecTB(
|
|||||||
else if (funct7 == 7'b0010000) name = "SH2ADD";
|
else if (funct7 == 7'b0010000) name = "SH2ADD";
|
||||||
else if (funct7 == 7'b0000101) name = "MIN";
|
else if (funct7 == 7'b0000101) name = "MIN";
|
||||||
else if (funct7 == 7'b0100000) name = "ORN";
|
else if (funct7 == 7'b0100000) name = "ORN";
|
||||||
else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H";
|
else if (funct7 == 7'b0000100 & rs2 == 5'b00000) name = "ZEXT.H";
|
||||||
else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK";
|
else if (funct7 == 7'b0000100 & op == 7'b0110011) name = "PACK";
|
||||||
else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW";
|
else if (funct7 == 7'b0000100 & op == 7'b0111011) name = "PACKW";
|
||||||
else name = "ILLEGAL";
|
else name = "ILLEGAL";
|
||||||
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
|
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
|
||||||
else if (funct7 == 7'b0000001) name = "DIVU";
|
else if (funct7 == 7'b0000001) name = "DIVU";
|
||||||
|
|||||||
@ -153,7 +153,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
|
if (P.ICACHE_SUPPORTED & I_CACHE_ADDR_LOGGER) begin : ICacheLogger
|
||||||
int file;
|
int file;
|
||||||
string LogFile;
|
string LogFile;
|
||||||
logic resetD, resetEdge;
|
logic resetD, resetEdge;
|
||||||
@ -193,7 +193,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
|
if (P.DCACHE_SUPPORTED & D_CACHE_ADDR_LOGGER) begin : DCacheLogger
|
||||||
int file;
|
int file;
|
||||||
string LogFile;
|
string LogFile;
|
||||||
logic resetD, resetEdge;
|
logic resetD, resetEdge;
|
||||||
|
|||||||
@ -21,53 +21,50 @@
|
|||||||
|
|
||||||
module riscvassertions import cvw::*; #(parameter cvw_t P);
|
module riscvassertions import cvw::*; #(parameter cvw_t P);
|
||||||
initial begin
|
initial begin
|
||||||
assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||||
assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
|
assert (P.S_SUPPORTED | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
|
||||||
assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
assert (P.IDIV_BITSPERCYCLE == 1 | P.IDIV_BITSPERCYCLE==2 | P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||||
assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
|
assert (P.F_SUPPORTED | ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
|
||||||
assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
|
assert (P.D_SUPPORTED | ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
|
||||||
assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
|
assert (P.F_SUPPORTED | ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||||
assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
|
assert (P.DCACHE_SUPPORTED | ~P.F_SUPPORTED | P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
|
||||||
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
|
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
|
||||||
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||||
assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
assert (P.DCACHE_LINELENINBITS >= 128 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||||
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
|
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
|
||||||
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||||
assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
assert (P.ICACHE_LINELENINBITS >= 32 | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||||
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
|
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
|
||||||
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
|
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
|
||||||
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
|
assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||||
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
|
assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
|
||||||
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
|
assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||||
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
|
assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
|
||||||
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
|
assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
|
||||||
assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
|
assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
|
||||||
assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
assert (P.ZICSR_SUPPORTED == 1 | (P.PMP_ENTRIES == 0 & P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
|
||||||
assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
|
assert (P.ZICSR_SUPPORTED == 1 | (P.S_SUPPORTED == 0 & P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
|
||||||
assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
assert (P.U_SUPPORTED | (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||||
assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
assert (P.VIRTMEM_SUPPORTED == 0 | (P.DTIM_SUPPORTED == 0 & P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||||
assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
|
assert (P.DCACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
|
||||||
assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
|
assert (P.ICACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
|
||||||
assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
|
assert ((P.DCACHE_SUPPORTED == 0 & P.ICACHE_SUPPORTED == 0) | P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
|
||||||
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
|
assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
|
||||||
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||||
assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
|
assert (P.DCACHE_SUPPORTED | (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
|
||||||
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
|
assert (P.IDIV_ON_FPU == 0 | P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
|
||||||
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
|
assert (P.SSTC_SUPPORTED == 0 | (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
|
||||||
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
|
assert ((P.M_SUPPORTED == 0) | (P.ZMMUL_SUPPORTED == 1)) else $fatal(1, "M requires ZMMUL");
|
||||||
assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
|
assert ((P.ZICNTR_SUPPORTED == 0) | (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
|
||||||
assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
|
assert ((P.ZIHPM_SUPPORTED == 0) | (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
|
||||||
assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
|
assert ((P.ZICBOM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
|
||||||
assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
|
assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
|
||||||
assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
|
assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
|
||||||
assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
|
assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
|
||||||
assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
|
assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA");
|
||||||
assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported");
|
assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
|
||||||
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
|
assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
|
||||||
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
|
assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
|
||||||
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
|
|
||||||
assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
|
|
||||||
assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported");
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -68,7 +68,7 @@ module testbench;
|
|||||||
logic ResetMem;
|
logic ResetMem;
|
||||||
|
|
||||||
// Variables that can be overwritten with $value$plusargs at start of simulation
|
// Variables that can be overwritten with $value$plusargs at start of simulation
|
||||||
string TEST;
|
string TEST, ElfFile;
|
||||||
integer INSTR_LIMIT;
|
integer INSTR_LIMIT;
|
||||||
|
|
||||||
// DUT signals
|
// DUT signals
|
||||||
@ -115,6 +115,10 @@ module testbench;
|
|||||||
// look for arguments passed to simulation, or use defaults
|
// look for arguments passed to simulation, or use defaults
|
||||||
if (!$value$plusargs("TEST=%s", TEST))
|
if (!$value$plusargs("TEST=%s", TEST))
|
||||||
TEST = "none";
|
TEST = "none";
|
||||||
|
if (!$value$plusargs("ElfFile=%s", ElfFile))
|
||||||
|
ElfFile = "none";
|
||||||
|
else begin
|
||||||
|
end
|
||||||
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
|
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
|
||||||
INSTR_LIMIT = 0;
|
INSTR_LIMIT = 0;
|
||||||
|
|
||||||
@ -221,8 +225,12 @@ module testbench;
|
|||||||
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
|
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
if (tests.size() == 0) begin
|
if (tests.size() == 0 & ElfFile == "none") begin
|
||||||
$display("TEST %s not supported in this configuration", TEST);
|
if (tests.size() == 0) begin
|
||||||
|
$display("TEST %s not supported in this configuration", TEST);
|
||||||
|
end else if(ElfFile == "none") begin
|
||||||
|
$display("ElfFile %s not found", ElfFile);
|
||||||
|
end
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
`ifdef MAKEVCD
|
`ifdef MAKEVCD
|
||||||
@ -257,7 +265,7 @@ module testbench;
|
|||||||
logic ResetCntRst;
|
logic ResetCntRst;
|
||||||
logic CopyRAM;
|
logic CopyRAM;
|
||||||
|
|
||||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
|
string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
|
||||||
integer begin_signature_addr, end_signature_addr, signature_size;
|
integer begin_signature_addr, end_signature_addr, signature_size;
|
||||||
integer uartoutfile;
|
integer uartoutfile;
|
||||||
|
|
||||||
@ -356,21 +364,27 @@ module testbench;
|
|||||||
//end // added
|
//end // added
|
||||||
//always @(posedge SelectTest) // added
|
//always @(posedge SelectTest) // added
|
||||||
if(SelectTest) begin
|
if(SelectTest) begin
|
||||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
if (riscofTest) begin
|
||||||
else if(TEST == "buildroot") begin
|
memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
||||||
|
elffilename = {pathname, tests[test], "ref/ref.elf"};
|
||||||
|
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
|
||||||
|
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
|
||||||
|
end else if(TEST == "buildroot") begin
|
||||||
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||||
|
elffilename = "buildroot";
|
||||||
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||||
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
||||||
uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
|
uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
|
||||||
end
|
|
||||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
|
||||||
if (riscofTest) begin
|
|
||||||
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
|
|
||||||
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
|
|
||||||
end else if (TEST == "buildroot") begin
|
|
||||||
ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
|
ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
|
||||||
ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
|
ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
|
||||||
|
end else if(ElfFile != "none") begin
|
||||||
|
elffilename = ElfFile;
|
||||||
|
memfilename = {ElfFile, ".memfile"};
|
||||||
|
ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
|
||||||
|
ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
|
||||||
end else begin
|
end else begin
|
||||||
|
elffilename = {pathname, tests[test], ".elf"};
|
||||||
|
memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||||
end
|
end
|
||||||
@ -410,6 +424,15 @@ module testbench;
|
|||||||
$display("Embench Benchmark: created output file: %s", outputfile);
|
$display("Embench Benchmark: created output file: %s", outputfile);
|
||||||
end else if (TEST == "coverage64gc") begin
|
end else if (TEST == "coverage64gc") begin
|
||||||
$display("Coverage tests don't get checked");
|
$display("Coverage tests don't get checked");
|
||||||
|
end else if (ElfFile != "none") begin
|
||||||
|
$display("Single Elf file tests are not signatured verified.");
|
||||||
|
`ifdef VERILATOR // this macro is defined when verilator is used
|
||||||
|
$finish; // Simulator Verilator needs $finish to terminate simulation.
|
||||||
|
`elsif SIM_VCS // this macro is defined when vcs is used
|
||||||
|
$finish; // Simulator VCS needs $finish to terminate simulation.
|
||||||
|
`else
|
||||||
|
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
|
||||||
|
`endif
|
||||||
end else begin
|
end else begin
|
||||||
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
||||||
// clear signature to prevent contamination from previous tests
|
// clear signature to prevent contamination from previous tests
|
||||||
@ -643,7 +666,7 @@ module testbench;
|
|||||||
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||||
always @(negedge clk) begin
|
always @(negedge clk) begin
|
||||||
if (INSTR_LIMIT > 0) begin
|
if (INSTR_LIMIT > 0) begin
|
||||||
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
|
if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
|
||||||
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
|
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -669,10 +692,17 @@ end
|
|||||||
.CMP_CSR (1)
|
.CMP_CSR (1)
|
||||||
) idv_trace2api(rvvi);
|
) idv_trace2api(rvvi);
|
||||||
|
|
||||||
|
string filename;
|
||||||
initial begin
|
initial begin
|
||||||
|
// imperasDV requires the elffile be defined at the begining of the simulation.
|
||||||
int iter;
|
int iter;
|
||||||
|
longint x64;
|
||||||
|
int x32[2];
|
||||||
|
longint index;
|
||||||
|
string memfilenameImperasDV, bootmemfilenameImperasDV;
|
||||||
#1;
|
#1;
|
||||||
IDV_MAX_ERRORS = 3;
|
IDV_MAX_ERRORS = 3;
|
||||||
|
elffilename = ElfFile;
|
||||||
|
|
||||||
// Initialize REF (do this before initializing the DUT)
|
// Initialize REF (do this before initializing the DUT)
|
||||||
if (!rvviVersionCheck(RVVI_API_VERSION)) begin
|
if (!rvviVersionCheck(RVVI_API_VERSION)) begin
|
||||||
@ -686,9 +716,57 @@ end
|
|||||||
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
|
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56));
|
||||||
void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
|
void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
|
||||||
|
|
||||||
if (!rvviRefInit("")) begin
|
if(elffilename == "buildroot") filename = "";
|
||||||
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
|
else filename = elffilename;
|
||||||
$fatal;
|
|
||||||
|
// use the ImperasDV rvviRefInit to load the reference model with an elf file
|
||||||
|
if(elffilename != "none") begin
|
||||||
|
if (!rvviRefInit(filename)) begin
|
||||||
|
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
|
||||||
|
$fatal;
|
||||||
|
end
|
||||||
|
end else begin // for buildroot use the binary instead to load teh reference model.
|
||||||
|
if (!rvviRefInit("")) begin // still have to call with nothing
|
||||||
|
$display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
|
||||||
|
$fatal;
|
||||||
|
end
|
||||||
|
|
||||||
|
memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||||
|
bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||||
|
|
||||||
|
$display("RVVI Loading bootmem.bin");
|
||||||
|
memFile = $fopen(bootmemfilenameImperasDV, "rb");
|
||||||
|
index = 'h1000 - 8;
|
||||||
|
while(!$feof(memFile)) begin
|
||||||
|
index+=8;
|
||||||
|
readResult = $fread(x64, memFile);
|
||||||
|
if (x64 == 0) continue;
|
||||||
|
x32[0] = x64 & 'hffffffff;
|
||||||
|
x32[1] = x64 >> 32;
|
||||||
|
rvviRefMemoryWrite(0, index+0, x32[0], 4);
|
||||||
|
rvviRefMemoryWrite(0, index+4, x32[1], 4);
|
||||||
|
//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
||||||
|
end
|
||||||
|
$fclose(memFile);
|
||||||
|
|
||||||
|
$display("RVVI Loading ram.bin");
|
||||||
|
memFile = $fopen(memfilenameImperasDV, "rb");
|
||||||
|
index = 'h80000000 - 8;
|
||||||
|
while(!$feof(memFile)) begin
|
||||||
|
index+=8;
|
||||||
|
readResult = $fread(x64, memFile);
|
||||||
|
if (x64 == 0) continue;
|
||||||
|
x32[0] = x64 & 'hffffffff;
|
||||||
|
x32[1] = x64 >> 32;
|
||||||
|
rvviRefMemoryWrite(0, index+0, x32[0], 4);
|
||||||
|
rvviRefMemoryWrite(0, index+4, x32[1], 4);
|
||||||
|
//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
||||||
|
end
|
||||||
|
$fclose(memFile);
|
||||||
|
|
||||||
|
$display("RVVI Loading Complete");
|
||||||
|
|
||||||
|
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
|
||||||
end
|
end
|
||||||
|
|
||||||
// Volatile CSRs
|
// Volatile CSRs
|
||||||
@ -744,53 +822,6 @@ end
|
|||||||
|
|
||||||
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
|
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
|
||||||
|
|
||||||
// Load memory
|
|
||||||
// *** RT: This section can probably be moved into the same chunk of code which
|
|
||||||
// loads the memories. However I'm not sure that ImperasDV supports reloading
|
|
||||||
// the memories without relaunching the simulator.
|
|
||||||
begin
|
|
||||||
longint x64;
|
|
||||||
int x32[2];
|
|
||||||
longint index;
|
|
||||||
string memfilenameImperasDV, bootmemfilenameImperasDV;
|
|
||||||
|
|
||||||
memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
|
||||||
bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
|
||||||
|
|
||||||
$display("RVVI Loading bootmem.bin");
|
|
||||||
memFile = $fopen(bootmemfilenameImperasDV, "rb");
|
|
||||||
index = 'h1000 - 8;
|
|
||||||
while(!$feof(memFile)) begin
|
|
||||||
index+=8;
|
|
||||||
readResult = $fread(x64, memFile);
|
|
||||||
if (x64 == 0) continue;
|
|
||||||
x32[0] = x64 & 'hffffffff;
|
|
||||||
x32[1] = x64 >> 32;
|
|
||||||
rvviRefMemoryWrite(0, index+0, x32[0], 4);
|
|
||||||
rvviRefMemoryWrite(0, index+4, x32[1], 4);
|
|
||||||
//$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
|
||||||
end
|
|
||||||
$fclose(memFile);
|
|
||||||
|
|
||||||
$display("RVVI Loading ram.bin");
|
|
||||||
memFile = $fopen(memfilenameImperasDV, "rb");
|
|
||||||
index = 'h80000000 - 8;
|
|
||||||
while(!$feof(memFile)) begin
|
|
||||||
index+=8;
|
|
||||||
readResult = $fread(x64, memFile);
|
|
||||||
if (x64 == 0) continue;
|
|
||||||
x32[0] = x64 & 'hffffffff;
|
|
||||||
x32[1] = x64 >> 32;
|
|
||||||
rvviRefMemoryWrite(0, index+0, x32[0], 4);
|
|
||||||
rvviRefMemoryWrite(0, index+4, x32[1], 4);
|
|
||||||
//$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
|
|
||||||
end
|
|
||||||
$fclose(memFile);
|
|
||||||
|
|
||||||
$display("RVVI Loading Complete");
|
|
||||||
|
|
||||||
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
|
always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7]));
|
||||||
|
|||||||
@ -38,8 +38,8 @@ main:
|
|||||||
csrrw t1, menvcfg, t0
|
csrrw t1, menvcfg, t0
|
||||||
csrrw t2, senvcfg, t0
|
csrrw t2, senvcfg, t0
|
||||||
|
|
||||||
# testing FIOM with different privelege modes
|
# testing FIOM with different privilege modes
|
||||||
# setting environment config (to both 1 and 0) in each privelege mode
|
# setting environment config (to both 1 and 0) in each privilege mode
|
||||||
csrsi menvcfg, 1
|
csrsi menvcfg, 1
|
||||||
li a0, 1
|
li a0, 1
|
||||||
ecall # enter supervisor mode
|
ecall # enter supervisor mode
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user