diff --git a/wally-pipelined/src/datapath.sv b/wally-pipelined/src/datapath.sv
index bb9a17fe0..0c27e7a62 100644
--- a/wally-pipelined/src/datapath.sv
+++ b/wally-pipelined/src/datapath.sv
@@ -61,7 +61,7 @@ module datapath (
   input  logic        FlushW,
   input  logic        RegWriteW, 
   input  logic [1:0]  ResultSrcW,
-  input  logic [`XLEN-1:0] PCW,
+  input  logic [`XLEN-1:0] PCLinkW,
 
   // Hazard Unit signals 
   output logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E,
@@ -125,5 +125,5 @@ module datapath (
   floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW);
   floprc #(5)    RdWEg(clk, reset, FlushW, RdM, RdW);
 
-  mux4  #(`XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW);	
+  mux4  #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRValW, ResultSrcW, ResultW);	
 endmodule
diff --git a/wally-pipelined/src/instrDecompress.sv b/wally-pipelined/src/decompress.sv
similarity index 99%
rename from wally-pipelined/src/instrDecompress.sv
rename to wally-pipelined/src/decompress.sv
index c2e4c7bc8..bb12db097 100644
--- a/wally-pipelined/src/instrDecompress.sv
+++ b/wally-pipelined/src/decompress.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// instrDecompress.sv
+// decompress.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module instrDecompress (
+module decompress (
   input  logic [31:0]     InstrRawD,
   output logic [31:0]     InstrD,
   output logic            IllegalCompInstrD);
diff --git a/wally-pipelined/src/ieu.sv b/wally-pipelined/src/ieu.sv
index 163e38dd1..0f3d22f17 100644
--- a/wally-pipelined/src/ieu.sv
+++ b/wally-pipelined/src/ieu.sv
@@ -43,7 +43,7 @@ module ieu (
   output logic [`XLEN-1:0] SrcAM,
   output logic [`XLEN-1:0] PCTargetE,
   input  logic [31:0] InstrD,
-  input  logic [`XLEN-1:0] PCE, PCW,
+  input  logic [`XLEN-1:0] PCE, PCLinkW,
   input  logic [`XLEN-1:0] CSRReadValM,
   input   logic [`XLEN-1:0] PrivilegedNextPCM, // *** eventually move to ifu
   output logic LoadMisalignedFaultM, LoadAccessFaultM, // *** eventually move these to the memory interface, along with memdp
diff --git a/wally-pipelined/src/ifu.sv b/wally-pipelined/src/ifu.sv
index c8c5d8490..30f864ae9 100644
--- a/wally-pipelined/src/ifu.sv
+++ b/wally-pipelined/src/ifu.sv
@@ -35,7 +35,8 @@ module ifu (
   input  logic            RetM, TrapM, 
   input  logic [`XLEN-1:0] PrivilegedNextPCM, 
   output logic [31:0]     InstrD, InstrM,
-  output logic [`XLEN-1:0] PCF, PCE, PCM, PCW, 
+  output logic [`XLEN-1:0] PCF, PCE, PCM, 
+  output logic [`XLEN-1:0] PCLinkW,
   input  logic            IllegalBaseInstrFaultD,
   output logic            IllegalIEUInstrFaultD,
   output logic            InstrMisalignedFaultM,
@@ -46,7 +47,7 @@ module ifu (
   logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic StallExceptResolveBranchesF, PrivilegedChangePCM;
   logic IllegalCompInstrD;
-  logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD;
+  logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
   logic        CompressedF;
   logic [31:0]     InstrRawD, InstrE;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
@@ -61,7 +62,6 @@ module ifu (
   assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
   flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
 
-
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   assign CompressedF = (InstrF[1:0] != 2'b11); // is it a 16-bit compressed instruction?
@@ -79,7 +79,8 @@ module ifu (
   flopenl #(32)    InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD);
   flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
-  instrDecompress decomp(.*);
+  // expand 16-bit compressed instructions to 32 bits
+  decompress decomp(.*);
   assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   // *** combine these with others in better way, including M, F
 
@@ -101,9 +102,16 @@ module ifu (
   
   flopr  #(32)   InstrEReg(clk, reset, FlushE ? nop : InstrD, InstrE);
   flopr  #(32)   InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM);
-  floprc #(`XLEN) PCEReg(clk, reset, FlushE, PCD, PCE);
-  floprc #(`XLEN) PCMReg(clk, reset, FlushM, PCE, PCM);
-  floprc #(`XLEN) PCWReg(clk, reset, FlushW, PCM, PCW);
+  flopr #(`XLEN) PCEReg(clk, reset, PCD, PCE);
+  flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM);
+  flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later
+
+  // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.  Maybe a way to draw on PC
+  // or just put an adder at the start of the writeback stage.
+  flopr #(`XLEN) PCPDReg(clk, reset, PCPlus2or4F, PCLinkD);
+  flopr #(`XLEN) PCPEReg(clk, reset, PCLinkD, PCLinkE);
+  flopr #(`XLEN) PCPMReg(clk, reset, PCLinkE, PCLinkM);
+  flopr #(`XLEN) PCPWReg(clk, reset, PCLinkM, PCLinkW);
 
 endmodule
 
diff --git a/wally-pipelined/src/wallypipelinedhart.sv b/wally-pipelined/src/wallypipelinedhart.sv
index 1bcae36fb..fcab384d8 100644
--- a/wally-pipelined/src/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wallypipelinedhart.sv
@@ -46,7 +46,7 @@ module wallypipelinedhart (
   logic        CSRWriteM, PrivilegedM;
   logic [`XLEN-1:0] SrcAM;
   logic [31:0] InstrD, InstrM;
-  logic [`XLEN-1:0] PCE, PCM, PCW;
+  logic [`XLEN-1:0] PCE, PCM, PCLinkW;
   logic [`XLEN-1:0] PCTargetE;
   logic [`XLEN-1:0] CSRReadValM;
   logic [`XLEN-1:0] PrivilegedNextPCM;