From aef408af58f1c87243638fde586cfdb97ea7ef79 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 21 Jun 2021 01:17:08 -0400 Subject: [PATCH] Reversed [0:...] with [...:0] in bus widths across the project --- wally-pipelined/src/dmem/dmem.sv | 2 +- wally-pipelined/src/generic/lzd.sv | 2 +- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/mmu/mmu.sv | 2 +- wally-pipelined/src/mmu/pmpchecker.sv | 4 ++-- wally-pipelined/src/mmu/tlbcam.sv | 2 +- wally-pipelined/src/mmu/tlbram.sv | 2 +- wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrm.sv | 4 ++-- wally-pipelined/src/privileged/privileged.sv | 2 +- wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +- wally-pipelined/testbench/testbench-coremark.sv | 4 ++-- wally-pipelined/testbench/testbench-coremark_bare.sv | 4 ++-- wally-pipelined/testbench/testbench-linux.sv | 2 +- wally-pipelined/testbench/testbench-privileged.sv | 4 ++-- 15 files changed, 20 insertions(+), 20 deletions(-) diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index ba3617d05..e8739cb2f 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -71,7 +71,7 @@ module dmem ( input logic HWRITE, input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage. input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. diff --git a/wally-pipelined/src/generic/lzd.sv b/wally-pipelined/src/generic/lzd.sv index 2637934fd..475829e3b 100755 --- a/wally-pipelined/src/generic/lzd.sv +++ b/wally-pipelined/src/generic/lzd.sv @@ -81,7 +81,7 @@ module lzd4 (ZP, ZV, B); lzd2 l1(ZPa, ZVa, B[1:0]); lzd2 l2(ZPb, ZVb, B[3:2]); - assign ZP[0:0] = ZVb ? ZPb : ZPa; + assign ZP[0] = ZVb ? ZPb : ZPa; assign ZP[1] = ~ZVb; assign ZV = ZVa | ZVb; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ca0071b11..8538d7fb6 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -80,7 +80,7 @@ module ifu ( input logic HWRITE, input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage. input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF, output logic ISquashBusAccessF, diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 04deb694c..ce1d8b0ba 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -70,7 +70,7 @@ module mmu #(parameter ENTRY_BITS = 3, input logic HWRITE, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic SquashBusAccess, // *** send to privileged unit output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM, diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index f9b15a1cb..8b33ccf3a 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -48,7 +48,7 @@ module pmpchecker ( // boundary. It would be better to store the PMP address registers in a module // somewhere in the CSR hierarchy and do PMP checking _within_ that module, so // we don't have to pass around 16 whole registers. - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input logic ExecuteAccessF, WriteAccessM, ReadAccessM, @@ -64,7 +64,7 @@ module pmpchecker ( logic [3:0] MatchedRegion; logic Match, EnforcePMP; - logic [7:0] PMPCFG [0:15]; + logic [7:0] PMPCFG [15:0]; // Bit i is high when the address is greater than or equal to PMPADR[i] // Used for determining whether TOR PMP regions match diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index cf66951f7..bd64afea9 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -47,7 +47,7 @@ module tlbcam #(parameter ENTRY_BITS = 3, localparam NENTRIES = 2**ENTRY_BITS; - logic [1:0] PageTypeList [0:NENTRIES-1]; + logic [1:0] PageTypeList [NENTRIES-1:0]; logic [NENTRIES-1:0] Matches; // Create NENTRIES CAM lines, each of which will independently consider diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index 9879ce660..2012ed829 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -41,7 +41,7 @@ module tlbram #(parameter ENTRY_BITS = 3) ( localparam NENTRIES = 2**ENTRY_BITS; - logic [`XLEN-1:0] ram [0:NENTRIES-1]; + logic [`XLEN-1:0] ram [NENTRIES-1:0]; logic [`XLEN-1:0] PageTableEntry; // Generate a flop for every entry in the RAM diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index d29104fc7..213bcde33 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -61,7 +61,7 @@ module csr #(parameter output logic STATUS_MXR, STATUS_SUM, output logic STATUS_MPRV, output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 611280743..33b903a83 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -91,7 +91,7 @@ module csrm #(parameter output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, // 64-bit registers in RV64, or two 32-bit registers in RV32 output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteMSTATUSM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM @@ -104,7 +104,7 @@ module csrm #(parameter logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; logic WritePMPCFG0M, WritePMPCFG2M; - logic WritePMPADDRM [0:15]; + logic WritePMPADDRM [15:0]; localparam MISA_26 = (`MISA) & 32'h03ffffff; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 061b6a37c..1275cd4b8 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -69,7 +69,7 @@ module privileged ( output logic [`XLEN-1:0] SATP_REGW, output logic STATUS_MXR, STATUS_SUM, output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], + output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic [2:0] FRM_REGW ); diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index c2dfd4371..8d02978a5 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -121,7 +121,7 @@ module wallypipelinedhart ( logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM; logic DSquashBusAccessM, ISquashBusAccessF; logic [5:0] DHSELRegionsM, IHSELRegionsF; - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1]; + var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu. assign HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this? diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index 3c4f5e57a..6c0f81934 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -28,8 +28,8 @@ module testbench(); logic clk; logic reset; int test, i, errors, totalerrors; - logic [31:0] sig32[0:10000]; - logic [`XLEN-1:0] signature[0:10000]; + logic [31:0] sig32[10000:0]; + logic [`XLEN-1:0] signature[10000:0]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [`XLEN-1:0] meminit; diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index c0441eb24..9c9a4f252 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -28,8 +28,8 @@ module testbench(); logic clk; logic reset; int test, i, errors, totalerrors; - logic [31:0] sig32[0:10000]; - logic [`XLEN-1:0] signature[0:10000]; + logic [31:0] sig32[10000:0]; + logic [`XLEN-1:0] signature[10000:0]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [`XLEN-1:0] meminit; diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 3fc4ba99b..df8fad8cd 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -70,7 +70,7 @@ module testbench(); logic SvMode, PTE_R, PTE_X; logic [`XLEN-1:0] SATP, PTE; logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [0:2]; + logic [8:0] VPN [2:0]; logic [11:0] Offset; int i; diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index c3e8e20f1..c8ba0abea 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -34,8 +34,8 @@ module testbench(); logic reset; int test, i, errors, totalerrors; - logic [31:0] sig32[0:10000]; - logic [`XLEN-1:0] signature[0:10000]; + logic [31:0] sig32[10000:0]; + logic [`XLEN-1:0] signature[10000:0]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; //logic [31:0] InstrW;