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	Merge branch 'openhwgroup:main' into priv-tests
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						aec27965af
					
				@ -47,8 +47,9 @@ string tvpaths[] = '{
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    "ieu",
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    "ebu",
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    "csrwrites",
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    "fpu",
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    "priv"
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    "priv",
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    "ifu",
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    "fpu"
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  };
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  string coremark[] = '{
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										40
									
								
								tests/coverage/ifu.S
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										40
									
								
								tests/coverage/ifu.S
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,40 @@
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///////////////////////////////////////////
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// ifu.S
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//
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// Written: sriley@g.hmc.edu 28 March 2023
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//
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// Purpose: Test coverage for IFU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// 
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the 
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
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// either express or implied. See the License for the specific language governing permissions 
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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    # turn floating point on
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    li t0, 0x2000
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    csrs mstatus, t0
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    # calling compressed floating point load double instruction
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    //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
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                        // binary version 0000 0000 0000 0000 0010 0000 0000 0000
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    mv s0, sp
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    c.fld fs0, 0(s0)
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    j done
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