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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies

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This commit is contained in:
David Harris 2021-12-15 12:10:45 -08:00
parent 4e35736e90
commit aebd746e71
9 changed files with 31 additions and 34 deletions
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4
wally-pipelined/src/cache/dcache.sv vendored
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@ -36,7 +36,7 @@ module dcache
input logic [6:0] Funct7M, input logic [6:0] Funct7M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic FlushDCacheM, input logic FlushDCacheM,
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [11:0] IEUAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`PA_BITS-1:0] MemPAdrM, // physical address
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
@ -147,7 +147,7 @@ module dcache
// Read Path CPU (IEU) side // Read Path CPU (IEU) side
mux4 #(INDEXLEN) mux4 #(INDEXLEN)
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d3(FlushAdr), .d3(FlushAdr),

10
wally-pipelined/src/ieu/datapath.sv
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@ -43,14 +43,14 @@ module datapath (
input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCE,
input logic [`XLEN-1:0] PCLinkE, input logic [`XLEN-1:0] PCLinkE,
output logic [2:0] FlagsE, output logic [2:0] FlagsE,
output logic [`XLEN-1:0] PCTargetE, output logic [`XLEN-1:0] IEUAdrE,
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
// Memory stage signals // Memory stage signals
input logic StallM, FlushM, input logic StallM, FlushM,
input logic FWriteIntM, input logic FWriteIntM,
input logic [`XLEN-1:0] FIntResM, input logic [`XLEN-1:0] FIntResM,
output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] SrcAM,
output logic [`XLEN-1:0] WriteDataM, MemAdrM, MemAdrE, output logic [`XLEN-1:0] WriteDataM,
// Writeback stage signals // Writeback stage signals
input logic StallW, FlushW, input logic StallW, FlushW,
input logic FWriteIntW, input logic FWriteIntW,
@ -80,7 +80,6 @@ module datapath (
logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
logic [`XLEN-1:0] WriteDataE; logic [`XLEN-1:0] WriteDataE;
logic [`XLEN-1:0] AddressE;
// Memory stage signals // Memory stage signals
logic [`XLEN-1:0] IEUResultM; logic [`XLEN-1:0] IEUResultM;
logic [`XLEN-1:0] ResultM; logic [`XLEN-1:0] ResultM;
@ -111,16 +110,13 @@ module datapath (
comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, AddressE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
assign MemAdrE = AddressE; // *** clean up this naming
assign PCTargetE = AddressE; // *** clean up this naming
// Memory stage pipeline register // Memory stage pipeline register
flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);

8
wally-pipelined/src/ieu/ieu.sv
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@ -37,7 +37,7 @@ module ieu (
input logic FWriteIntE, input logic FWriteIntE,
input logic IllegalFPUInstrE, input logic IllegalFPUInstrE,
input logic [`XLEN-1:0] FWriteDataE, input logic [`XLEN-1:0] FWriteDataE,
output logic [`XLEN-1:0] PCTargetE, output logic [`XLEN-1:0] IEUAdrE,
output logic MulDivE, W64E, output logic MulDivE, W64E,
output logic [2:0] Funct3E, output logic [2:0] Funct3E,
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
@ -49,7 +49,7 @@ module ieu (
output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] MemRWM, // read/write control goes to LSU
output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicE, // atomic control goes to LSU
output logic [1:0] AtomicM, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU
output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU
output logic [2:0] Funct3M, // size and signedness to LSU output logic [2:0] Funct3M, // size and signedness to LSU
output logic [`XLEN-1:0] SrcAM, // to privilege and fpu output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
@ -127,11 +127,11 @@ module ieu (
.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE,
.ALUResultSrcE, .JumpE, .IllegalFPUInstrE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
.FWriteDataE, .PCE, .PCLinkE, .FlagsE, .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
.PCTargetE, .IEUAdrE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
// Memory stage signals // Memory stage signals
.StallM, .FlushM, .FWriteIntM, .FIntResM, .StallM, .FlushM, .FWriteIntM, .FIntResM,
.SrcAM, .WriteDataM, .MemAdrM, .MemAdrE, .SrcAM, .WriteDataM,
// Writeback stage signals // Writeback stage signals
.StallW, .FlushW, .FWriteIntW, .RegWriteW, .StallW, .FlushW, .FWriteIntW, .RegWriteW,
.SquashSCW, .ResultSrcW, .ReadDataW, .SquashSCW, .ResultSrcW, .ReadDataW,

6
wally-pipelined/src/ifu/bpred.sv
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@ -45,7 +45,7 @@ module bpred
// *** the specifics of how this is encode is subject to change. // *** the specifics of how this is encode is subject to change.
input logic PCSrcE, // AKA Branch Taken input logic PCSrcE, // AKA Branch Taken
// Signals required to check the branch prediction accuracy. // Signals required to check the branch prediction accuracy.
input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken. input logic [`XLEN-1:0] IEUAdrE, // The branch destination if the branch is taken.
input logic [`XLEN-1:0] PCD, // The address the branch predictor took. input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
input logic [4:0] InstrClassE, input logic [4:0] InstrClassE,
@ -165,7 +165,7 @@ module bpred
// update // update
.UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
.UpdatePC(PCE), .UpdatePC(PCE),
.UpdateTarget(PCTargetE), .UpdateTarget(IEUAdrE),
.UpdateInvalid(PredictionInstrClassWrongE), .UpdateInvalid(PredictionInstrClassWrongE),
.UpdateInstrClass(InstrClassE)); .UpdateInstrClass(InstrClassE));
@ -218,7 +218,7 @@ module bpred
// Check the prediction makes execution. // Check the prediction makes execution.
// first check if the target or fallthrough address matches what was predicted. // first check if the target or fallthrough address matches what was predicted.
assign TargetWrongE = PCTargetE != PCD; assign TargetWrongE = IEUAdrE != PCD;
assign FallThroughWrongE = PCLinkE != PCD; assign FallThroughWrongE = PCLinkE != PCD;
// If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected // If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected
// Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi

8
wally-pipelined/src/ifu/ifu.sv
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@ -40,7 +40,7 @@ module ifu (
// Execute // Execute
output logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCLinkE,
input logic PCSrcE, input logic PCSrcE,
input logic [`XLEN-1:0] PCTargetE, input logic [`XLEN-1:0] IEUAdrE,
output logic [`XLEN-1:0] PCE, output logic [`XLEN-1:0] PCE,
output logic BPPredWrongE, output logic BPPredWrongE,
// Mem // Mem
@ -223,7 +223,7 @@ module ifu (
.SelBPPredF(SelBPPredF), .SelBPPredF(SelBPPredF),
.PCE(PCE), .PCE(PCE),
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.PCTargetE(PCTargetE), .IEUAdrE(IEUAdrE),
.PCD(PCD), .PCD(PCD),
.PCLinkE(PCLinkE), .PCLinkE(PCLinkE),
.InstrClassE(InstrClassE), .InstrClassE(InstrClassE),
@ -242,8 +242,8 @@ module ifu (
assign BPPredClassNonCFIWrongE = 1'b0; assign BPPredClassNonCFIWrongE = 1'b0;
end end
endgenerate endgenerate
// The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE. // The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
assign PCCorrectE = PCSrcE ? PCTargetE : PCLinkE; assign PCCorrectE = PCSrcE ? IEUAdrE : PCLinkE;
// pcadder // pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32

12
wally-pipelined/src/lsu/lsu.sv
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@ -49,9 +49,9 @@ module lsu
output logic DCacheAccess, output logic DCacheAccess,
// address and write data // address and write data
input logic [`XLEN-1:0] MemAdrM, input logic [`XLEN-1:0] IEUAdrE,
input logic [`XLEN-1:0] MemAdrE, output logic [`XLEN-1:0] MemAdrM,
input logic [`XLEN-1:0] WriteDataM, input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataM, output logic [`XLEN-1:0] ReadDataM,
// cpu privilege // cpu privilege
@ -129,6 +129,8 @@ module lsu
assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
// *** add generate to conditionally create hptw, lsuArb, and mmu // *** add generate to conditionally create hptw, lsuArb, and mmu
// based on `MEM_VIRTMEM // based on `MEM_VIRTMEM
hptw hptw(.clk(clk), hptw hptw(.clk(clk),
@ -169,7 +171,7 @@ module lsu
.Funct3M(Funct3M), .Funct3M(Funct3M),
.AtomicM(AtomicM), .AtomicM(AtomicM),
.MemAdrM(MemAdrM), .MemAdrM(MemAdrM),
.MemAdrE(MemAdrE[11:0]), .IEUAdrE(IEUAdrE[11:0]),
.CommittedM(CommittedM), .CommittedM(CommittedM),
.PendingInterruptM(PendingInterruptM), .PendingInterruptM(PendingInterruptM),
.StallW(StallW), .StallW(StallW),
@ -251,7 +253,7 @@ module lsu
.Funct7M(Funct7M), .Funct7M(Funct7M),
.FlushDCacheM, .FlushDCacheM,
.AtomicM(AtomicMtoDCache), .AtomicM(AtomicMtoDCache),
.MemAdrE(MemAdrEtoDCache), .IEUAdrE(MemAdrEtoDCache),
.MemPAdrM(MemPAdrM), .MemPAdrM(MemPAdrM),
.VAdr(MemAdrM[11:0]), .VAdr(MemAdrM[11:0]),
.WriteDataM(WriteDataM), .WriteDataM(WriteDataM),

4
wally-pipelined/src/lsu/lsuArb.sv
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@ -40,7 +40,7 @@ module lsuArb
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrM, input logic [`XLEN-1:0] MemAdrM,
input logic [11:0] MemAdrE, input logic [11:0] IEUAdrE,
input logic StallW, input logic StallW,
input logic PendingInterruptM, input logic PendingInterruptM,
// to CPU // to CPU
@ -85,7 +85,7 @@ module lsuArb
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign MemAdrMExt = {2'b00, MemAdrM}; assign MemAdrMExt = {2'b00, MemAdrM};
assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0]; assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0];
assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : MemAdrE[11:0]; assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
assign StallWtoDCache = SelPTW ? 1'b0 : StallW; assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;

11
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -68,7 +68,6 @@ module wallypipelinedhart (
(* mark_debug = "true" *) logic [31:0] InstrM; (* mark_debug = "true" *) logic [31:0] InstrM;
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM; logic [`XLEN-1:0] PrivilegedNextPCM;
(* mark_debug = "true" *) logic [1:0] MemRWM; (* mark_debug = "true" *) logic [1:0] MemRWM;
@ -122,7 +121,7 @@ module wallypipelinedhart (
// cpu lsu interface // cpu lsu interface
logic [2:0] Funct3M; logic [2:0] Funct3M;
logic [`XLEN-1:0] MemAdrE; logic [`XLEN-1:0] IEUAdrE;
(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
(* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM; (* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM;
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
@ -170,7 +169,7 @@ module wallypipelinedhart (
.InstrReadF, .ICacheStallF, .InstrReadF, .ICacheStallF,
// Execute // Execute
.PCLinkE, .PCSrcE, .PCTargetE, .PCE, .PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
.BPPredWrongE, .BPPredWrongE,
// Mem // Mem
@ -209,7 +208,7 @@ module wallypipelinedhart (
// Execute Stage interface // Execute Stage interface
.PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE, .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
.FWriteDataE, .PCTargetE, .MulDivE, .W64E, .FWriteDataE, .IEUAdrE, .MulDivE, .W64E,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
//.SrcAE, .SrcBE, //.SrcAE, .SrcBE,
.FWriteIntM, .FWriteIntM,
@ -219,7 +218,7 @@ module wallypipelinedhart (
.MemRWM, // read/write control goes to LSU .MemRWM, // read/write control goes to LSU
.AtomicE, // atomic control goes to LSU .AtomicE, // atomic control goes to LSU
.AtomicM, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU
.MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU .WriteDataM, // Write data to LSU
.Funct3M, // size and signedness to LSU .Funct3M, // size and signedness to LSU
.SrcAM, // to privilege and fpu .SrcAM, // to privilege and fpu
.RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
@ -248,7 +247,7 @@ module wallypipelinedhart (
.CommittedM, .DCacheMiss, .DCacheAccess, .CommittedM, .DCacheMiss, .DCacheAccess,
.SquashSCW, .SquashSCW,
//.DataMisalignedM(DataMisalignedM), //.DataMisalignedM(DataMisalignedM),
.MemAdrE, .MemAdrM, .WriteDataM, .IEUAdrE, .MemAdrM, .WriteDataM,
.ReadDataM, .FlushDCacheM, .ReadDataM, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck, .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,

2
wally-pipelined/testbench/testbench-linux.sv
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@ -100,7 +100,7 @@ module testbench();
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW); flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW); flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW); flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW); flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.MemAdrM, MemAdrW);
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW); flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW); flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);