From ae8d581f4ea081bc4bc615072a7e17f00136ca2c Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 3 Apr 2024 17:09:19 -0700 Subject: [PATCH] Started implementing Verilator for testfloat --- sim/sim-testfloat-verilator | 27 +++++++++++++++++++++++++++ testbench/testbench-fp.sv | 34 +++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 15 deletions(-) create mode 100755 sim/sim-testfloat-verilator diff --git a/sim/sim-testfloat-verilator b/sim/sim-testfloat-verilator new file mode 100755 index 000000000..c08484275 --- /dev/null +++ b/sim/sim-testfloat-verilator @@ -0,0 +1,27 @@ +#!/usr/bin/bash + +# sim-testfloat-verilator +# David_Harris@hmc.edu 3 April 2024 +# Run Testfloat simulations with Verilator +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# cvtint - test integer conversion unit (fcvtint) +# cvtfp - test floating-point conversion unit (fcvtfp) +# cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +# add - test addition +# fma - test fma +# mul - test mult with fma +# sub - test subtraction +# div - test division +# sqrt - test square root +# all - test everything + +#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" + +verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv --relative-includes + +#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 + +# Change TEST_SIZE to only test certain FP width +# values are QP, DP, SP, HP or all for all tests +#vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 626e73bb4..ce4fd19e1 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -30,8 +30,8 @@ import cvw::*; module testbenchfp; // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir // to run specific precisions (e.g., quad or all) - parameter TEST="none"; - parameter TEST_SIZE="none"; + parameter string TEST="none"; + parameter string TEST_SIZE="none"; `include "parameter-defs.vh" @@ -85,7 +85,7 @@ module testbenchfp; logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; - logic DivStart=0; + logic DivStart; logic FDivBusyE; logic OldFDivBusyE; logic reset = 1'b0; @@ -653,7 +653,7 @@ module testbenchfp; static string pp = `PATH; string testname; string tt0; - tt0 = $psprintf("%s", Tests[TestNum]); + tt0 = $sformatf("%s", Tests[TestNum]); testname = {pp, tt0}; //$display("Here you are %s", testname); $display("\n\nRunning %s vectors ", Tests[TestNum]); @@ -673,7 +673,7 @@ module testbenchfp; // - 1 for the larger precision // - 0 for the smaller precision always_comb begin - if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT; + if (P.FMTBITS == 1) ModFmt = {1'b0, FmtVal == P.FMT}; else ModFmt = FmtVal; end @@ -819,8 +819,8 @@ module testbenchfp; case (UnitVal) `FMAUNIT: Res = FpRes; `DIVUNIT: Res = FpRes; - `CMPUNIT: Res = CmpRes; - `CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes; + `CMPUNIT: Res = {{(FLEN-XLEN){1'b0}}, CmpRes}; + `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN-XLEN){1'b0}}, IntRes}; else Res = FpRes; `CVTFPUNIT: Res = FpRes; endcase @@ -859,6 +859,10 @@ module testbenchfp; DivStart = 1'b0; nextstate = S0; end + default: begin + DivStart = 1'b0; + nextstate = S0; + end endcase // case (state) end @@ -1149,22 +1153,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b11: begin // quad X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)]; Y = TestVector[12+(P.Q_LEN)-1:12]; - Ans = TestVector[8]; + Ans = {{P.FLEN{1'b0}}, TestVector[8]}; end 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN{1'b0}}, TestVector[8]}; end 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN{1'b0}}, TestVector[8]}; end 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]}; - Ans = TestVector[8]; + Ans = {{P.FLEN{1'b0}}, TestVector[8]}; end endcase `CVTFPUNIT: @@ -1254,7 +1258,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( case (Fmt) 2'b11: begin // quad // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> quad X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; @@ -1280,7 +1284,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end 2'b01: if (P.D_SUPPORTED) begin // double // {Int->Fp?, is the integer a long} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> double X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; @@ -1306,7 +1310,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end 2'b00: if (P.S_SUPPORTED) begin // single // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; @@ -1332,7 +1336,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end 2'b10: begin // half // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) + casez ({OpCtrl[2:1]}) 2'b11: begin // long -> half X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];