From ae64b859c3ce941ef4cfc1e83a059de27c02d136 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 6 Jan 2022 23:03:29 +0000
Subject: [PATCH] Fixed multiplier nan boxing bug

---
 pipelined/src/fpu/fpu.sv                  | 8 +++++---
 pipelined/src/fpu/unpacking.sv            | 3 +--
 pipelined/src/wally/wallypipelinedhart.sv | 4 ++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index c09d81a17..f0730d98d 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -125,7 +125,8 @@ module fpu (
    logic [63:0] 	  DivInput1E, DivInput2E;             // inputs to divide/squareroot unit
    logic 		  load_preload;                       // enable for FF on fpdivsqrt     
    logic [63:0] 	  AlignedSrcAE;                       // align SrcA to the floating point format
-
+   logic [63:0]     BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
+   
    // DECODE STAGE
 
    // calculate FP control signals
@@ -163,8 +164,9 @@ module fpu (
             {2'b0, {10{1'b1}}, 52'b0}, 
             {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, 
             FSrcYE); // Force Z to be 0 for multiply instructions
-   // Force Z to be 0 for multiply instructions     
-   mux3  #(64)  fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
+   // Force Z to be 0 for multiply instructions 
+   mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
+   mux3  #(64)  fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
       
    // unpacking unit
    //    - splits FP inputs into their various parts
diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv
index b61dd8315..78a4d7446 100644
--- a/pipelined/src/fpu/unpacking.sv
+++ b/pipelined/src/fpu/unpacking.sv
@@ -22,11 +22,10 @@ module unpacking (
     logic           XFracZero, YFracZero, ZFracZero; // input fraction zero
     logic           XExpZero, YExpZero, ZExpZero; // input exponent zero
     logic           YExpMaxE, ZExpMaxE;  // input exponent all 1s
-    logic           XDoubleNaN, YDoubleNaN, ZDoubleNaN;
     logic  [31:0]   XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed
 
     // Determine if number is NaN as double precision to check single precision NaN boxing
-    if (`XLEN==32) begin  // eventually this should change to FLEN when RV32f has FLEN=32
+    if (`F_SUPPORTED & ~`D_SUPPORTED) begin  // eventually this should change to FLEN when FLEN isn't hardwared to 64
         assign XFloat = X[31:0]; 
         assign YFloat = Y[31:0];  
         assign ZFloat = Z[31:0]; 
diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv
index 59ba0aee8..5c931d027 100644
--- a/pipelined/src/wally/wallypipelinedhart.sv
+++ b/pipelined/src/wally/wallypipelinedhart.sv
@@ -68,8 +68,8 @@ module wallypipelinedhart (
   (* mark_debug = "true" *) logic [31:0] 		    InstrM;
   logic [`XLEN-1:0] 	    PCF, PCD, PCE, PCLinkE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    PCM;
-  logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
-  logic [`XLEN-1:0] 	    PrivilegedNextPCM;
+ logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
+   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
   (* mark_debug = "true" *) logic [1:0] 		    MemRWM;
   (* mark_debug = "true" *) logic 		    InstrValidM;
   logic 		    InstrMisalignedFaultM;