From ae5d7844a9acae599b919bc9136f110ec75eafdb Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Thu, 2 Feb 2023 19:49:14 +0000
Subject: [PATCH] clmul finished initial hdl; passes lint

---
 pipelined/src/ieu/clmul.sv | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv
index 2fba79f02..bd2615a91 100644
--- a/pipelined/src/ieu/clmul.sv
+++ b/pipelined/src/ieu/clmul.sv
@@ -32,21 +32,23 @@
 module clmul #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, B,       // Operands
   output logic [WIDTH-1:0] Result);     // ZBS result
-  //output logic [WIDTH-1:0] Sum);       // Sum of operands
 
-  logic [WIDTH-1] pp [WIDTH-1]; //partial AND products
-  logic [WIDTH-1] sop; //sum of partial products
-  genvar i;
-  for (i=0; i<WIDTH;i+=WIDTH) begin:forloop //loop fills partial product array
-    for
-    //fill partials products here
+  logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products
+  logic [WIDTH-1:0] sop; //sum of partial products
+
+  genvar i,j;
+  for (i=1; i<WIDTH;i+=WIDTH) begin:outer //loop fills partial product array
+    for (j=0;j<i;j++) begin: inner
+      assign pp[i][j] = A[i]&B[j];
+    end
   end
 
-  genvar i;
-  for (i=1;x<WIDTH;i++) begin:outer 
-    assign result[x] = ^pp[i][i:0]
+  for (i=1;i<WIDTH;i++) begin:xortree
+    assign result[i] = ^pp[i][i:0];
   end
 
+  assign result[0] = A[0]&B[0];
+
 
 endmodule