From ae0702d129e1423b9595f6b4631b2d978a3229f2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 06:21:22 -0700 Subject: [PATCH] Renamed DCache to Cache in busdp/busfsm signal interface --- pipelined/src/ifu/ifu.sv | 6 +++--- pipelined/src/lsu/busdp.sv | 18 ++++++++++-------- pipelined/src/lsu/busfsm.sv | 28 ++++++++++++++-------------- pipelined/src/lsu/lsu.sv | 4 ++-- 4 files changed, 29 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c1ac1b8f1..c0bce157b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -205,10 +205,10 @@ module ifu ( busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), + .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), .WordCount(), - .DCacheFetchLine(ICacheFetchLine), - .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), + .CacheFetchLine(ICacheFetchLine), + .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), .DLSUBusBuffer(ILSUBusBuffer), .LSUPAdrM(PCPF), .SelUncachedAdr, .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index e8b182b27..3889b070f 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -37,6 +37,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( input logic clk, reset, + // bus interface input logic [`XLEN-1:0] LSUBusHRDATA, input logic LSUBusAck, @@ -50,15 +51,16 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, + // cache interface. - input logic [`PA_BITS-1:0] DCacheBusAdr, - input logic DCacheFetchLine, - input logic DCacheWriteLine, - output logic DCacheBusAck, + input logic [`PA_BITS-1:0] CacheBusAdr, + input logic CacheFetchLine, + input logic CacheWriteLine, + output logic CacheBusAck, output logic [LINELEN-1:0] DLSUBusBuffer, //*** change name. output logic SelUncachedAdr, - // lsu interface + // lsu/ifu interface input logic [`PA_BITS-1:0] LSUPAdrM, input logic IgnoreRequest, input logic [1:0] LSURWM, @@ -80,14 +82,14 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( - .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, + .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead, .BufferCaptureEn, - .LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .LSUBurstType, .LSUTransType, .LSUTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index ceae87ab1..f0204f3e4 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -38,8 +38,8 @@ module busfsm #(parameter integer WordCountThreshold, input logic IgnoreRequest, input logic [1:0] LSURWM, - input logic DCacheFetchLine, - input logic DCacheWriteLine, + input logic CacheFetchLine, + input logic CacheWriteLine, input logic LSUBusAck, input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. input logic CPUBusy, @@ -52,7 +52,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic [2:0] LSUBurstType, output logic LSUTransComplete, output logic [1:0] LSUTransType, - output logic DCacheBusAck, + output logic CacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, output logic BufferCaptureEn, @@ -116,8 +116,8 @@ module busfsm #(parameter integer WordCountThreshold, STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; - else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; @@ -130,13 +130,13 @@ module busfsm #(parameter integer WordCountThreshold, STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) begin - if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_FETCH; STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) begin - if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_WRITE; default: BusNextState = STATE_BUS_READY; @@ -158,9 +158,9 @@ module busfsm #(parameter integer WordCountThreshold, // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; // Reset if we aren't initiating a transaction or if we are finishing a transaction. - assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | LSUTransComplete; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | @@ -174,13 +174,13 @@ module busfsm #(parameter integer WordCountThreshold, assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); - assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); + assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BufferCaptureEn = UnCachedLSUBusRead | BusCurrState == STATE_BUS_FETCH; // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; - assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | + assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | @@ -188,5 +188,5 @@ module busfsm #(parameter integer WordCountThreshold, BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) | - ~CACHE_ENABLED; // if no dcache always select uncachedadr. + ~CACHE_ENABLED; // if no Cache always select uncachedadr. endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1b7804d8e..10f8060b6 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -225,8 +225,8 @@ module lsu ( .clk, .reset, .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .WordCount, .SelLSUBusWord, - .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, - .DCacheWriteLine, .DCacheBusAck, .DLSUBusBuffer, .LSUPAdrM, + .LSUFunct3M, .LSUBusAdr, .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM);