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https://github.com/openhwgroup/cvw
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fix underscore in instantiation
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@ -28,12 +28,11 @@
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module aesinvsboxword(input logic [31:0] in, output logic [31:0] out);
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module aesinvsboxword(input logic [31:0] in, output logic [31:0] out);
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// Declare the SBOX for (least significant) byte 0 of the input
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// Declare the SBOX for (least significant) byte 0 of the input
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aesinvsbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
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aesinvsbox sboxb0(.in(in[7:0]), .out(out[7:0]));
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// Declare the SBOX for byte 1 of the input
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// Declare the SBOX for byte 1 of the input
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aesinvsbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
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aesinvsbox sboxb1(.in(in[15:8]), .out(out[15:8]));
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// Declare the SBOX for byte 2 of the input
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// Declare the SBOX for byte 2 of the input
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aesinvsbox sbox_b2(.in(in[23:16]), .out(out[23:16]));
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aesinvsbox sboxb2(.in(in[23:16]), .out(out[23:16]));
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// Declare the SBOX for byte 3 of the input
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// Declare the SBOX for byte 3 of the input
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aesinvsbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
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aesinvsbox sboxb3(.in(in[31:24]), .out(out[31:24]));
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endmodule
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endmodule
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@ -28,12 +28,11 @@
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module aessboxword(input logic [31:0] in, output logic [31:0] out);
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module aessboxword(input logic [31:0] in, output logic [31:0] out);
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// Declare the SBOX for (least significant) byte 0 of the input
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// Declare the SBOX for (least significant) byte 0 of the input
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aessbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
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aessbox sboxb0(.in(in[7:0]), .out(out[7:0]));
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// Declare the SBOX for byte 1 of the input
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// Declare the SBOX for byte 1 of the input
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aessbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
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aessbox sboxb1(.in(in[15:8]), .out(out[15:8]));
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// Declare the SBOX for byte 2 of the input
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// Declare the SBOX for byte 2 of the input
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aessbox sbox_b2(.in(in[23:16]), .out(out[23:16]));
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aessbox sboxb2(.in(in[23:16]), .out(out[23:16]));
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// Declare the SBOX for byte 3 of the input
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// Declare the SBOX for byte 3 of the input
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aessbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
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aessbox sboxb3(.in(in[31:24]), .out(out[31:24]));
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endmodule
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endmodule
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@ -4,7 +4,7 @@
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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// Created: 20 February 2024
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//
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//
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// Purpose: aes_shiftrow for taking in first Data line
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// Purpose: aesshiftrow for taking in first Data line
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//
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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// https://github.com/openhwgroup/cvw
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@ -30,6 +30,5 @@ module aesshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
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assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
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assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
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DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],
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DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],
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DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32],
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DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32],
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DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]};
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DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]};
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endmodule
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endmodule
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@ -31,5 +31,4 @@ module galoismultforward(input logic [7:0] in, output logic [7:0] out);
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assign leftshift = {in[6:0], 1'b0};
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assign leftshift = {in[6:0], 1'b0};
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assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift;
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assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift;
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endmodule
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endmodule
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