fix underscore in instantiation

src/ieu/aes_common/aesinvsboxword.sv

@@ -28,12 +28,11 @@
 module aesinvsboxword(input logic [31:0] in, output logic [31:0] out);
    
    // Declare the SBOX for (least significant) byte 0 of the input
-   aesinvsbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
+   aesinvsbox sboxb0(.in(in[7:0]), .out(out[7:0]));
    // Declare the SBOX for byte 1 of the input
-   aesinvsbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
+   aesinvsbox sboxb1(.in(in[15:8]), .out(out[15:8]));
    // Declare the SBOX for byte 2 of the input
-   aesinvsbox sbox_b2(.in(in[23:16]), .out(out[23:16]));	
+   aesinvsbox sboxb2(.in(in[23:16]), .out(out[23:16]));	
    // Declare the SBOX for byte 3 of the input	
-   aesinvsbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
+   aesinvsbox sboxb3(.in(in[31:24]), .out(out[31:24]));   
-   
 endmodule

src/ieu/aes_common/aessboxword.sv

@@ -28,12 +28,11 @@
 module aessboxword(input logic [31:0] in, output logic [31:0] out);   
    
    // Declare the SBOX for (least significant) byte 0 of the input
-   aessbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
+   aessbox sboxb0(.in(in[7:0]), .out(out[7:0]));
    // Declare the SBOX for byte 1 of the input
-   aessbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
+   aessbox sboxb1(.in(in[15:8]), .out(out[15:8]));
    // Declare the SBOX for byte 2 of the input
-   aessbox sbox_b2(.in(in[23:16]), .out(out[23:16]));	
+   aessbox sboxb2(.in(in[23:16]), .out(out[23:16]));	
    // Declare the SBOX for byte 3 of the input	
-   aessbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
+   aessbox sboxb3(.in(in[31:24]), .out(out[31:24]));   
-   
 endmodule

src/ieu/aes_common/aesshiftrow.sv

@@ -4,7 +4,7 @@
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
 //
-// Purpose: aes_shiftrow for taking in first Data line
+// Purpose: aesshiftrow for taking in first Data line
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -30,6 +30,5 @@ module aesshiftrow(input  logic [127:0] DataIn, output logic [127:0] DataOut);
    assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
                      DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],
                      DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32],
-                     DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]};
+                     DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]};   
-   
 endmodule

src/ieu/aes_common/galoismultforward.sv

@@ -31,5 +31,4 @@ module galoismultforward(input logic [7:0] in, output logic [7:0] out);
 
    assign leftshift = {in[6:0], 1'b0};
    assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift;
-
 endmodule