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Merge pull request #189 from kipmacsaigoren/bitmanip_cleanup
Bitmanip: Removed Comparator Flag to ALU
This commit is contained in:
David Harris
GitHub
commit
ad0b430c63
@ -37,14 +37,13 @@ module alu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // For BMU decoding
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, ALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
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@ -84,16 +83,16 @@ module alu #(parameter WIDTH=32) (
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end
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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if (WIDTH == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign PreALUResult = FullResult;
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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.Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .Result);
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.Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .ALUResult);
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end else begin
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assign Result = ALUResult;
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assign ALUResult = PreALUResult;
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assign CondMaskB = B;
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assign CondShiftA = A;
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end
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@ -35,12 +35,13 @@ module bitmanipalu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
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input logic CompLT, // Less-Than flag from comparator
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input logic LT, // less than flag
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input logic LTU, // less than unsigned flag
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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input logic [WIDTH-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
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output logic [WIDTH-1:0] Result); // Result
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output logic [WIDTH-1:0] ALUResult); // Result
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logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
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logic [WIDTH-1:0] MaskB; // BitMask of B
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@ -84,16 +85,16 @@ module bitmanipalu #(parameter WIDTH=32) (
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult);
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Result Select Mux
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always_comb
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case (BSelect)
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// 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC
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2'b00: Result = ALUResult;
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2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: Result = ZBBResult;
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2'b11: Result = ZBCResult;
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2'b00: ALUResult = PreALUResult;
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2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: ALUResult = ZBBResult;
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2'b11: ALUResult = ZBCResult;
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endcase
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endmodule
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@ -48,7 +48,6 @@ module bmuctrl(
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output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
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output logic [2:0] ZBBSelectE, // ZBB mux select signal
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output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
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output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage
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output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage
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);
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@ -56,7 +55,6 @@ module bmuctrl(
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logic [2:0] Funct3D; // Funct3 field in Decode stage
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage
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logic RotateD; // Indicates if rotate instruction in Decode Stage
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logic MaskD; // Indicates if zbs instruction in Decode Stage
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logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
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@ -110,10 +108,10 @@ module bmuctrl(
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
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17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu
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endcase
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if (`XLEN==32)
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casez({OpD, Funct7D, Funct3D})
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@ -172,12 +170,9 @@ module bmuctrl(
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// Pack BALUControl Signals
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assign BALUControlD = {RotateD, MaskD, PreShiftD};
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// Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
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assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
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// Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition
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assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
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// BMU Execute stage pipieline control register
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flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE});
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flopenrc#(9) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE});
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endmodule
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@ -30,20 +30,20 @@
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`include "wally-config.vh"
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module clmul #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [WIDTH-1:0] X, Y, // Operands
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output logic [WIDTH-1:0] ClmulResult); // ZBS result
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logic [(WIDTH*WIDTH)-1:0] s; // intermediary signals for carry-less multiply
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logic [(WIDTH*WIDTH)-1:0] S; // intermediary signals for carry-less multiply
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integer i,j;
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always_comb begin
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for (i=0;i<WIDTH;i++) begin: outer
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s[WIDTH*i]=A[0]&B[i];
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S[WIDTH*i] = X[0] & Y[i];
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for (j=1;j<=i;j++) begin: inner
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s[WIDTH*i+j] = (A[j]&B[i-j])^s[WIDTH*i+j-1];
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S[WIDTH*i+j] = (X[j] & Y[i-j]) ^ S[WIDTH*i+j-1];
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end
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ClmulResult[i] = s[WIDTH*i+j-1];
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ClmulResult[i] = S[WIDTH*i+j-1];
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end
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end
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endmodule
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@ -33,21 +33,25 @@
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic W64, // Indicates word operation
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input logic lt, // lt flag
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input logic LT, // lt flag
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input logic LTU, // ltu flag
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input logic BUnsigned, // max/min (signed) flag
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input logic [2:0] ZBBSelect, // ZBB Result select signal
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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logic lt; // lt given signed/unsigned
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] MinMaxResult; // min, max result
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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// ZBBSelect[2] differentiates between min(u) vs max(u) instruction
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mux2 #(WIDTH) minmaxmux(B, A, lt^ZBBSelect[2], MinMaxResult);
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mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);
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// ZBB Result select mux
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mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
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@ -36,19 +36,16 @@ module zbc #(parameter WIDTH=32) (
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logic [WIDTH-1:0] ClmulResult, RevClmulResult;
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logic [WIDTH-1:0] RevB;
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logic [WIDTH-1:0] x,y;
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logic [1:0] select;
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logic [WIDTH-1:0] X, Y;
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assign select = ~Funct3[1:0];
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bitreverse #(WIDTH) brB(B, RevB);
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bitreverse #(WIDTH) brB(.A(B), .RevA(RevB));
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mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
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mux3 #(WIDTH) ymux({{1'b0}, RevB[WIDTH-2:0]}, RevB, B, ~Funct3[1:0], Y);
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mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, select, x);
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mux3 #(WIDTH) ymux({{1'b0},RevB[WIDTH-2:0]}, RevB, B, select, y);
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clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult));
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clmul #(WIDTH) clm(.X, .Y, .ClmulResult);
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bitreverse #(WIDTH) brClmulResult(.A(ClmulResult), .RevA(RevClmulResult));
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bitreverse #(WIDTH) brClmulResult(ClmulResult, RevClmulResult);
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mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
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endmodule
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@ -125,7 +125,6 @@ module controller(
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logic IntDivM; // Integer divide instruction
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logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
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logic [2:0] ZBBSelectD; // ZBB Mux Select Signal
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logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage
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logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions
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logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions
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logic JFunctD; // detect jalr instruction
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@ -257,7 +256,7 @@ module controller(
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD,
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.BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE,
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.ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE);
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.ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE);
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if (`ZBA_SUPPORTED) begin
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// ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
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assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
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@ -283,7 +282,6 @@ module controller(
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assign BSelectE = 2'b00;
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assign BSelectD = 2'b00;
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assign ZBBSelectE = 3'b000;
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assign BComparatorSignedE = 1'b0;
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assign BALUControlE = 3'b0;
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end
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@ -311,8 +309,7 @@ module controller(
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// Branch Logic
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// The comparator handles both signed and unsigned branches using BranchSignedE
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// Hence, only eq and lt flags are needed
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// We also want comparator to handle signed comparison on a max/min bitmanip instruction
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assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE;
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assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE);
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assign {eqE, ltE} = FlagsE;
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mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
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assign BranchTakenE = BranchFlagE ^ Funct3E[0];
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@ -114,7 +114,7 @@ module datapath (
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE);
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mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
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mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
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