From acd60218b8cdf1b81f2c5a561b988d83e46eb506 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Mar 2022 16:58:26 -0600 Subject: [PATCH] Removed unused signal. --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/busdp.sv | 1 - pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 35dfa4135..c2df13806 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -201,7 +201,7 @@ module ifu ( .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), .DCacheBusWriteData(ICacheBusWriteData), .LSUPAdrM(PCPF), - .FinalWriteDataM(), .SelUncachedAdr, + .SelUncachedAdr, .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 49907bb5c..90f84cd76 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -56,7 +56,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) // lsu interface input logic [`PA_BITS-1:0] LSUPAdrM, - input logic [`XLEN-1:0] FinalWriteDataM, input logic IgnoreRequest, input logic [1:0] LSURWM, input logic CPUBusy, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 0dde84461..843efdd62 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -216,7 +216,7 @@ module lsu ( .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, - .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .FinalWriteDataM, + .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM);