diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c
index b294552e6..a9a26d803 100644
--- a/pipelined/src/fma/fma16_testgen.c
+++ b/pipelined/src/fma/fma16_testgen.c
@@ -11,6 +11,7 @@ typedef union sp {
 // lists of tests, terminated with 0x8000
 uint16_t easyExponents[] = {15, 0x8000};
 uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000};
+uint16_t allExponents[] = {1, 15, 16, 30, 31, 0x8000};
 uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
 uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000}; 
 uint16_t zeros[] = {0x0000, 0x8000};
@@ -37,7 +38,7 @@ float convFloat(float16_t f16) {
 void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) {
     float16_t result;
     int op;
-    char calc[80];
+    char calc[80], flags[80];
     float32_t x32, y32, z32, r32;
     float xf, yf, zf, rf;
     float16_t smallest;
@@ -47,8 +48,15 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
     if (negp) x.v ^= 0x8000; // flip sign of x to negate p
     if (negz) z.v ^= 0x8000; // flip sign of z to negate z
     op = mul<<3 | add<<2 | negp<<1 | negz;
+    softfloat_exceptionFlags = 0; // clear exceptions
     result = f16_mulAdd(x, y, z);
 
+    sprintf(flags, "NV: %d OF: %d UF: %d NX: %d", 
+        (softfloat_exceptionFlags >> 4) % 2,
+        (softfloat_exceptionFlags >> 2) % 2,
+        (softfloat_exceptionFlags >> 1) % 2,
+        (softfloat_exceptionFlags) % 2);
+
     // convert to floats for printing
     xf = convFloat(x);
     yf = convFloat(y);
@@ -67,7 +75,7 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
     if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
     if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed)  fprintf(fptr, "// Skip inf: ");
     if (resultmag.v >  0x7C00 && !nanAllowed)  fprintf(fptr, "// Skip NaN: ");
-    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x // %s\n", x.v, y.v, z.v, op, result.v, calc);
+    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%02x // %s %s\n", x.v, y.v, z.v, op, result.v, softfloat_exceptionFlags, calc, flags);
 }
 
 void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, 
@@ -107,8 +115,8 @@ void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc,
     fclose(fptr);
 }
 
-void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc) {
-    int i, j, numCases;
+void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) {
+    int i, j, k, numCases;
     float16_t x, y, z;
     float16_t cases[100000];
     FILE *fptr;
@@ -122,7 +130,72 @@ void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc)
         x.v = cases[i].v;
         for (j=0; j<numCases; j++) {
             z.v = cases[j].v;
-            //genCase(fptr, x, y, z, 0, 1, 0, 0);
+            for (k=0; k<=sgn; k++) {
+                z.v ^= (k<<15);
+                genCase(fptr, x, y, z, 0, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed);
+            }
+        }
+    }
+    fclose(fptr);
+}
+
+
+void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) {
+    int i, j, k, l, numCases;
+    float16_t x, y, z;
+    float16_t cases[100000];
+    FILE *fptr;
+    char fn[80];
+ 
+    sprintf(fn, "work/%s.tv", testName);
+    fptr = fopen(fn, "w");
+    prepTests(e, f, testName, desc, cases, fptr, &numCases);
+    for (i=0; i < numCases; i++) {
+        x.v = cases[i].v;
+        for (j=0; j<numCases; j++) {
+            y.v = cases[j].v;
+            for (k=0; k<numCases; k++) {
+                z.v = cases[k].v;
+                for (l=0; l<=sgn; l++) {
+                    z.v ^= (l<<15);
+                    genCase(fptr, x, y, z, 1, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed);
+                }
+            }
+        }
+    }
+    fclose(fptr);
+}
+
+void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int zeroAllowed, int infAllowed, int nanAllowed) {
+    int i, j, k, sx, sy, sz, numCases;
+    float16_t x, y, z;
+    float16_t cases[100000];
+    FILE *fptr;
+    char fn[80];
+ 
+    sprintf(fn, "work/%s.tv", testName);
+    fptr = fopen(fn, "w");
+    prepTests(e, f, testName, desc, cases, fptr, &numCases);
+    cases[numCases].v = 0x0000; // add +0 case
+    cases[numCases+1].v = 0x8000; // add -0 case
+    numCases += 2; 
+    for (i=0; i < numCases; i++) {
+        x.v = cases[i].v;
+        for (j=0; j<numCases; j++) {
+            y.v = cases[j].v;
+            for (k=0; k<numCases; k++) {
+                z.v = cases[k].v;
+                for (sx=0; sx<=sgn; sx++) {
+                    x.v ^= (sx<<15);
+                    for (sy=0; sy<=sgn; sy++) {
+                        y.v ^= (sy<<15);
+                        for (sz=0; sz<=sgn; sz++) {
+                            z.v ^= (sz<<15);
+                            genCase(fptr, x, y, z, 1, 1, 0, 0, zeroAllowed, infAllowed, nanAllowed);
+                        }
+                    }
+                }
+            }
         }
     }
     fclose(fptr);
@@ -138,5 +211,26 @@ int main()
     genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0);
     genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0);
 
+    // Test cases: addition
+    genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0);
+    genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0);
+    genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0);
+
+    // Test cases: FMA
+    genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0);
+    genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0);
+    genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0);
+
+    // Test cases: Zero, Infinity, NaN
+    genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 1, 1, 1);
+ 
+    // Full test cases with other rounding modes
+    softfloat_roundingMode = softfloat_round_near_even; 
+    genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1);
+    softfloat_roundingMode = softfloat_round_min; 
+    genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 1, 1, 1);
+    softfloat_roundingMode = softfloat_round_max; 
+    genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 1, 1, 1);
+  
     return 0;
 }
diff --git a/setup.sh b/setup.sh
index c5ba9ebf3..b3452626d 100755
--- a/setup.sh
+++ b/setup.sh
@@ -15,7 +15,7 @@ echo \$WALLY set to ${WALLY}
 export RISCV=/opt/riscv   # change this if you installed the tools in a different location
 
 # Tools
-# GCCZ
+# GCC
 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
 export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin      # GCC tools
 # Spike
@@ -26,8 +26,8 @@ export PATH=$WALLY/bin:$PATH
 # Verilator
 export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
 # ModelSim/Questa (vsim)
-export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim
-export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH    # Change this for your path to Modelsim
+export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim, or delete
+export PATH=/cad/mentor/questa_sim-2022.1_1/questasim/bin:$PATH    # Change this for your path to Modelsim 
 export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
 export PATH=/cad/synopsys/SYN/bin:$PATH  # Change this for your path to Design Compiler
 export SNPSLMD_LICENSE_FILE=27020@134.173.38.214