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Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.

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This commit is contained in:
Ross Thompson 2023-04-17 20:05:59 -05:00
parent dd7f5310e4
commit ac95087042
3 changed files with 51 additions and 52 deletions
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4
fpga/constraints/constraints-ArtyA7.xdc
View File

@ -42,8 +42,8 @@ set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [g
# *** IOSTANDARD is probably wrong
set_property PACKAGE_PIN A9 [get_ports UARTSin]
set_property PACKAGE_PIN D10 [get_ports UARTSout]
set_max_delay -from [get_ports UARTSin] 10.000
set_max_delay -to [get_ports UARTSout] 10.000
set_max_delay -from [get_ports UARTSin] 14.000
set_max_delay -to [get_ports UARTSout] 14.000
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
set_property DRIVE 4 [get_ports UARTSout]

98
fpga/generator/xlnx_ddr3-artya7-mig.prj
View File

@ -65,57 +65,57 @@
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<MemoryVoltage>1.35V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL15" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
<Pin IN_TERM="" IOSTANDARD="LVCMOS15" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL15" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
<Pin IN_TERM="" IOSTANDARD="LVCMOS135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
</PinSelection>
<System_Clock>
<Pin Bank="Select Bank" PADName="No connect" name="sys_clk_i"/>

1
fpga/src/fpgaTopArtyA7.v
View File

@ -416,7 +416,6 @@ module fpgaTop
.ddr3_dm(ddr3_dm),
.ddr3_odt(ddr3_odt),
// clocks. I still don't understand why this needs two?
.sys_clk_i(clk167),
.clk_ref_i(clk200),