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update aes_common with style on separate sv
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James E. Stine
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51
src/ieu/aes_common/aes_inv_mixcols.sv
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51
src/ieu/aes_common/aes_inv_mixcols.sv
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///////////////////////////////////////////
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// aes_inv_mixcols.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: AES Inverted Mix Column Function for use with AES
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col);
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// Declare Internal logic
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logic [31:0] w0, w1, w2, w3;
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logic [31:0] ws0, ws1, ws2, ws3;
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// Break up input data into word components
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assign w0 = data[127:96];
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assign w1 = data[95:64];
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assign w2 = data[63:32];
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assign w3 = data[31:0];
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// Declare mixword components
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inv_mixword mw_0(.word(w0), .mixed_word(ws0));
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inv_mixword mw_1(.word(w1), .mixed_word(ws1));
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inv_mixword mw_2(.word(w2), .mixed_word(ws2));
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inv_mixword mw_3(.word(w3), .mixed_word(ws3));
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// Assign output to mixed word
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assign mixed_col = {ws0, ws1, ws2, ws3};
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endmodule // inv_mixcols
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@ -74,28 +74,3 @@ module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word);
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assign mixed_word = {mb0, mb1, mb2, mb3};
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endmodule // inv_mixword
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module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col);
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// Declare Internal logic
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logic [31:0] w0, w1, w2, w3;
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logic [31:0] ws0, ws1, ws2, ws3;
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// Break up input data into word components
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assign w0 = data[127:96];
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assign w1 = data[95:64];
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assign w2 = data[63:32];
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assign w3 = data[31:0];
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// Declare mixword components
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inv_mixword mw_0(.word(w0), .mixed_word(ws0));
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inv_mixword mw_1(.word(w1), .mixed_word(ws1));
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inv_mixword mw_2(.word(w2), .mixed_word(ws2));
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inv_mixword mw_3(.word(w3), .mixed_word(ws3));
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// Assign output to mixed word
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assign mixed_col = {ws0, ws1, ws2, ws3};
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endmodule // inv_mixcols
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@ -64,50 +64,3 @@ module aes_mixcolumns(data, mixedcols);
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assign mixedcols = {ws0, ws1, ws2, ws3};
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endmodule // mixcolumns
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// This applies the Galois field operations to an individual 32 bit word.
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module mixword (word, mixed_word);
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// Declare Inputs/Outputs
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input logic [31:0] word;
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output logic [31:0] mixed_word;
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// Declare Internal Signals
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logic [7:0] b0, b1, b2, b3;
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logic [7:0] mb0, mb1, mb2, mb3;
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logic [7:0] gm2_0_out;
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logic [7:0] gm3_0_out;
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logic [7:0] gm2_1_out;
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logic [7:0] gm3_1_out;
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logic [7:0] gm2_2_out;
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logic [7:0] gm3_2_out;
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logic [7:0] gm2_3_out;
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logic [7:0] gm3_3_out;
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// Break word into bytes
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assign b0 = word[31:24];
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assign b1 = word[23:16];
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assign b2 = word[15:8];
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assign b3 = word[7:0];
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// mb0 Galois components
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gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
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gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
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// mb1 Galois components
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gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
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gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
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// mb2 Galois components
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gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
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gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
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// mb3 Galois components
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gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
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gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
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// Combine Componenets into mixed word
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assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
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assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
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assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
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assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
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assign mixed_word = {mb0, mb1, mb2, mb3};
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endmodule
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@ -60,36 +60,3 @@ module aes_shiftrow(input logic [127:0] dataIn,
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assign dataOut = {out_w0, out_w1, out_w2, out_w3};
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endmodule
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/*
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* Purpose : This next module provides an alternative way to shift the values.
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in which it takes the shift number (essentially row number) as
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an input and shifts cyclically to the left by that number of bits.
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the complexity here is removed from the module and is more complex in
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input selection (eww more thinking bad return to monkeh)
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*/
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module aes_shiftwordbrutherr(input logic[1:0] shiftAmt,
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input logic [31:0] dataIn,
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output logic [31:0] dataOut);
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logic [7:0] b0 = dataIn[7:0];
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logic [7:0] b1 = dataIn[15:8];
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logic [7:0] b2 = dataIn[23:16];
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logic [7:0] b3 = dataIn[31:24];
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always_comb
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begin
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case(shiftAmt)
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// 00 : Barrel Shift no bytes
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2'b00 : dataOut = {b3, b2, b1, b0};
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// 01 : Barrel Shift one byte
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2'b01 : dataOut = {b2, b1, b0, b3};
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// 10 : Barrel Shift two bytes
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2'b10 : dataOut = {b1, b0, b2, b3};
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// 11 : Barrel Shift three bytes
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default : dataOut = {b0, b1, b2, b3};
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endcase
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end
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endmodule
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72
src/ieu/aes_common/mixword.sv
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72
src/ieu/aes_common/mixword.sv
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@ -0,0 +1,72 @@
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///////////////////////////////////////////
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// mixword.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: Galois field operation to an individual 32-bit word
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module mixword (word, mixed_word);
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// Declare Inputs/Outputs
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input logic [31:0] word;
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output logic [31:0] mixed_word;
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// Declare Internal Signals
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logic [7:0] b0, b1, b2, b3;
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logic [7:0] mb0, mb1, mb2, mb3;
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logic [7:0] gm2_0_out;
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logic [7:0] gm3_0_out;
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logic [7:0] gm2_1_out;
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logic [7:0] gm3_1_out;
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logic [7:0] gm2_2_out;
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logic [7:0] gm3_2_out;
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logic [7:0] gm2_3_out;
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logic [7:0] gm3_3_out;
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// Break word into bytes
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assign b0 = word[31:24];
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assign b1 = word[23:16];
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assign b2 = word[15:8];
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assign b3 = word[7:0];
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// mb0 Galois components
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gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
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gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
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// mb1 Galois components
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gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
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gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
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// mb2 Galois components
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gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
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gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
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// mb3 Galois components
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gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
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gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
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// Combine Componenets into mixed word
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assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
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assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
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assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
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assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
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assign mixed_word = {mb0, mb1, mb2, mb3};
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endmodule
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