update aes_common with style on separate sv

src/ieu/aes_common/aes_inv_mixcols.sv

@@ -0,0 +1,51 @@
+///////////////////////////////////////////
+// aes_inv_mixcols.sv
+//
+// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
+// Created: 20 February 2024
+//
+// Purpose: AES Inverted Mix Column Function for use with AES
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module aes_inv_mixcols (input  logic [127:0] data, output logic [127:0] mixed_col);
+
+   // Declare Internal logic
+   logic [31:0] 	w0, w1, w2, w3;
+   logic [31:0] 	ws0, ws1, ws2, ws3;
+   
+   // Break up input data into word components
+   assign w0 = data[127:96];
+   assign w1 = data[95:64];
+   assign w2 = data[63:32];
+   assign w3 = data[31:0];
+
+   // Declare mixword components
+   inv_mixword mw_0(.word(w0), .mixed_word(ws0));
+   inv_mixword mw_1(.word(w1), .mixed_word(ws1));
+   inv_mixword mw_2(.word(w2), .mixed_word(ws2));
+   inv_mixword mw_3(.word(w3), .mixed_word(ws3));
+
+   // Assign output to mixed word
+   assign mixed_col = {ws0, ws1, ws2, ws3};
+
+endmodule // inv_mixcols
+
+

src/ieu/aes_common/aes_inv_mixcolumns.sv

@@ -74,28 +74,3 @@ module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word);
    assign mixed_word = {mb0, mb1, mb2, mb3};  
 
 endmodule // inv_mixword
-
-module aes_inv_mixcols (input  logic [127:0] data, output logic [127:0] mixed_col);
-
-   // Declare Internal logic
-   logic [31:0] 	w0, w1, w2, w3;
-   logic [31:0] 	ws0, ws1, ws2, ws3;
-   
-   // Break up input data into word components
-   assign w0 = data[127:96];
-   assign w1 = data[95:64];
-   assign w2 = data[63:32];
-   assign w3 = data[31:0];
-
-   // Declare mixword components
-   inv_mixword mw_0(.word(w0), .mixed_word(ws0));
-   inv_mixword mw_1(.word(w1), .mixed_word(ws1));
-   inv_mixword mw_2(.word(w2), .mixed_word(ws2));
-   inv_mixword mw_3(.word(w3), .mixed_word(ws3));
-
-   // Assign output to mixed word
-   assign mixed_col = {ws0, ws1, ws2, ws3};
-
-endmodule // inv_mixcols
-
-

src/ieu/aes_common/aes_mixcolumns.sv

@@ -64,50 +64,3 @@ module aes_mixcolumns(data, mixedcols);
    assign mixedcols = {ws0, ws1, ws2, ws3};
    
 endmodule // mixcolumns
-
-// This applies the Galois field operations to an individual 32 bit word.
-module mixword (word, mixed_word);
-   
-   // Declare Inputs/Outputs
-   input logic [31:0] word;
-   output logic [31:0] mixed_word;
-   
-   // Declare Internal Signals
-   logic [7:0] 	       b0, b1, b2, b3;
-   logic [7:0] 	       mb0, mb1, mb2, mb3;   
-   logic [7:0] 	       gm2_0_out;
-   logic [7:0] 	       gm3_0_out;   
-   logic [7:0] 	       gm2_1_out;
-   logic [7:0] 	       gm3_1_out;   
-   logic [7:0] 	       gm2_2_out;
-   logic [7:0] 	       gm3_2_out;   
-   logic [7:0] 	       gm2_3_out;
-   logic [7:0] 	       gm3_3_out;   
-   
-   // Break word into bytes
-   assign b0 = word[31:24];
-   assign b1 = word[23:16];
-   assign b2 = word[15:8];
-   assign b3 = word[7:0];
-
-   // mb0 Galois components
-   gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
-   gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
-   // mb1 Galois components
-   gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
-   gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
-   // mb2 Galois components
-   gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
-   gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
-   // mb3 Galois components
-   gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
-   gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
-
-   // Combine Componenets into mixed word
-   assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
-   assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
-   assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
-   assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
-   assign mixed_word = {mb0, mb1, mb2, mb3};
-   
-endmodule

src/ieu/aes_common/aes_shiftrow.sv

@@ -60,36 +60,3 @@ module aes_shiftrow(input logic [127:0] dataIn,
    assign dataOut = {out_w0, out_w1, out_w2, out_w3};
    
 endmodule
-
-/*
- * Purpose : This next module provides an alternative way to shift the values.
- in which it takes the shift number (essentially row number) as 
- an input and shifts cyclically to the left by that number of bits.
- the complexity here is removed from the module and is more complex in
- input selection (eww more thinking bad return to monkeh)
- */
-
-module aes_shiftwordbrutherr(input logic[1:0] shiftAmt,
-			     input logic [31:0]  dataIn,
-			     output logic [31:0] dataOut);		     
-   
-   logic [7:0] 					 b0 = dataIn[7:0];
-   logic [7:0] 					 b1 = dataIn[15:8];
-   logic [7:0] 					 b2 = dataIn[23:16];
-   logic [7:0] 					 b3 = dataIn[31:24];
-   
-   always_comb
-     begin
-	case(shiftAmt)	  
-	  // 00 : Barrel Shift no bytes
-	  2'b00 : dataOut = {b3, b2, b1, b0};
-	  // 01 : Barrel Shift one byte
-	  2'b01 : dataOut = {b2, b1, b0, b3};
-	  // 10 : Barrel Shift two bytes
-	  2'b10 : dataOut = {b1, b0, b2, b3};
-	  // 11 : Barrel Shift three bytes
-	  default : dataOut = {b0, b1, b2, b3};
-	endcase
-     end
-
-endmodule			

src/ieu/aes_common/mixword.sv

@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// mixword.sv
+//
+// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
+// Created: 20 February 2024
+//
+// Purpose: Galois field operation to an individual 32-bit word
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module mixword (word, mixed_word);
+   
+   // Declare Inputs/Outputs
+   input logic [31:0] word;
+   output logic [31:0] mixed_word;
+   
+   // Declare Internal Signals
+   logic [7:0] 	       b0, b1, b2, b3;
+   logic [7:0] 	       mb0, mb1, mb2, mb3;   
+   logic [7:0] 	       gm2_0_out;
+   logic [7:0] 	       gm3_0_out;   
+   logic [7:0] 	       gm2_1_out;
+   logic [7:0] 	       gm3_1_out;   
+   logic [7:0] 	       gm2_2_out;
+   logic [7:0] 	       gm3_2_out;   
+   logic [7:0] 	       gm2_3_out;
+   logic [7:0] 	       gm3_3_out;   
+   
+   // Break word into bytes
+   assign b0 = word[31:24];
+   assign b1 = word[23:16];
+   assign b2 = word[15:8];
+   assign b3 = word[7:0];
+
+   // mb0 Galois components
+   gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
+   gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
+   // mb1 Galois components
+   gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
+   gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
+   // mb2 Galois components
+   gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
+   gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
+   // mb3 Galois components
+   gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
+   gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
+
+   // Combine Componenets into mixed word
+   assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
+   assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
+   assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
+   assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
+   assign mixed_word = {mb0, mb1, mb2, mb3};
+   
+endmodule