diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 04df2d72f..8cb29a8de 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -215,6 +215,13 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
 add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/BusCurrState
 add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusRead
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/UnCachedLsuBusWrite
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
@@ -468,9 +475,8 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChang
 add wave -noupdate /testbench/dut/hart/priv/priv/csr/MEPC_REGW
 add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr
 add wave -noupdate /testbench/dut/hart/lsu/BasePAdrMaskedM
-add wave -noupdate /testbench/dut/hart/lsu/match
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35021 ns} 0} {{Cursor 4} {49574 ns} 1}
+WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35522 ns} 0} {{Cursor 4} {49574 ns} 1}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
@@ -486,4 +492,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {34887 ns} {35269 ns}
+WaveRestoreZoom {35088 ns} {35954 ns}
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 7f49d32ce..74cf0d384 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -351,7 +351,7 @@ module lsu
   logic 			   WordCountFlag;
   
   logic [`XLEN-1:0]    FinalAMOWriteDataM, FinalWriteDataM;
-  (* mark_debug = "true" *) logic [`XLEN-1:0]    DC_HWDATA_FIXNAME;
+  (* mark_debug = "true" *) logic [`XLEN-1:0]    PreLsuBusHWDATA;
   logic 			   SelFlush;
   logic [`XLEN-1:0]    ReadDataWordM;
   logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData;
@@ -428,11 +428,10 @@ module lsu
 			    .HWDATAIN(FinalAMOWriteDataM),
 			    .HWDATA(FinalWriteDataM));
 
-  assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM;
 
   generate
-    if (`XLEN == 32) assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b010;
-    else assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b011;
+    if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010;
+    else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011;
   endgenerate;
 
   // Bus Side logic
@@ -452,13 +451,17 @@ module lsu
 
 
 
-  //assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ;
   assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ;
 
   assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
   
-  assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[WordCount];
+  assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount];
 
+  assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA;  // *** why is this not FinalWriteDataM? which does not work.
+
+
+
+  
   assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
   assign CntEn = PreCntEn & LsuBusAck;