diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index 0ca45420a..41a6db450 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -60,6 +60,7 @@ module testbench;
 
   logic [P.AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
+  logic             HSELEXTSDC;
   logic [P.PA_BITS-1:0] HADDR;
   logic [P.AHBW-1:0] HWDATA;
   logic [P.XLEN/8-1:0] HWSTRB;
@@ -81,13 +82,7 @@ module testbench;
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
 
-  logic        SDCCLK;
-  logic        SDCCmdIn;
-  logic        SDCCmdOut;
-  logic        SDCCmdOE;
-  logic [3:0]  SDCDatIn;
-  tri1 [3:0]   SDCDat;
-  tri1         SDCCmd;
+  logic        SDCIntr;
 
   logic        HREADY;
   logic        HSELEXT;
@@ -239,6 +234,8 @@ module testbench;
   end
 
   if(P.FPGA) begin : sdcard
+    // *** fix later
+/* -----\/----- EXCLUDED -----\/-----
     sdModel sdcard
       (.sdClk(SDCCLK),
        .cmd(SDCCmd), 
@@ -247,15 +244,16 @@ module testbench;
     assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
     assign SDCCmdIn = SDCCmd;
     assign SDCDatIn = SDCDat;
+ -----/\----- EXCLUDED -----/\----- */
+    assign SDCIntr = '0;
   end else begin
-    assign SDCCmd = '0;
-    assign SDCDat = '0;
+    assign SDCIntr = '0;
   end
 
-  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+                        .UARTSin, .UARTSout, .SDCIntr); 
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,