diff --git a/config/derivlist.txt b/config/derivlist.txt
index 6851278b3..1c4f19fe2 100644
--- a/config/derivlist.txt
+++ b/config/derivlist.txt
@@ -616,6 +616,10 @@ deriv f_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
+deriv f_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   0
+
 deriv f_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
@@ -662,6 +666,10 @@ deriv fh_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
+deriv fh_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   1
+
 deriv fh_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
@@ -708,6 +716,10 @@ deriv fd_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
+deriv fd_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   0
+
 deriv fd_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
@@ -755,6 +767,10 @@ deriv fdh_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
+deriv fdh_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   1
+
 deriv fdh_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
@@ -801,6 +817,10 @@ deriv fdq_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
+deriv fdq_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   0
+
 deriv fdq_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
@@ -847,6 +867,10 @@ deriv fdqh_div_4_2_rv32gc    div_4_2_rv32gc
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
+deriv fdqh_div_4_4_rv32gc    div_4_4_rv32gc    
+MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   1
+
 deriv fdqh_div_2_1_rv64gc    div_2_1_rv64gc    
 MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
@@ -888,6 +912,9 @@ IEEE754         1
 deriv f_ieee_div_4_2_rv32gc    f_div_4_2_rv32gc    
 IEEE754         1
 
+deriv f_ieee_div_4_4_rv32gc    f_div_4_4_rv32gc    
+IEEE754         1
+
 deriv f_ieee_div_2_1_rv64gc    f_div_2_1_rv64gc    
 IEEE754         1
 
@@ -922,6 +949,9 @@ IEEE754         1
 deriv fh_ieee_div_4_2_rv32gc    fh_div_4_2_rv32gc    
 IEEE754         1
 
+deriv fh_ieee_div_4_4_rv32gc    fh_div_4_4_rv32gc    
+IEEE754         1
+
 deriv fh_ieee_div_2_1_rv64gc    fh_div_2_1_rv64gc    
 IEEE754         1
 
@@ -956,6 +986,9 @@ IEEE754         1
 deriv fd_ieee_div_4_2_rv32gc    fd_div_4_2_rv32gc    
 IEEE754         1
 
+deriv fd_ieee_div_4_4_rv32gc    fd_div_4_4_rv32gc    
+IEEE754         1
+
 deriv fd_ieee_div_2_1_rv64gc    fd_div_2_1_rv64gc    
 IEEE754         1
 
@@ -991,6 +1024,9 @@ IEEE754         1
 deriv fdh_ieee_div_4_2_rv32gc    fdh_div_4_2_rv32gc    
 IEEE754         1
 
+deriv fdh_ieee_div_4_4_rv32gc    fdh_div_4_4_rv32gc    
+IEEE754         1
+
 deriv fdh_ieee_div_2_1_rv64gc    fdh_div_2_1_rv64gc    
 IEEE754         1
 
@@ -1025,6 +1061,9 @@ IEEE754         1
 deriv fdq_ieee_div_4_2_rv32gc    fdq_div_4_2_rv32gc    
 IEEE754         1
 
+deriv fdq_ieee_div_4_4_rv32gc    fdq_div_4_4_rv32gc    
+IEEE754         1
+
 deriv fdq_ieee_div_2_1_rv64gc    fdq_div_2_1_rv64gc    
 IEEE754         1
 
@@ -1060,6 +1099,9 @@ IEEE754         1
 deriv fdqh_ieee_div_4_2_rv32gc    fdqh_div_4_2_rv32gc    
 IEEE754         1
 
+deriv fdqh_ieee_div_4_4_rv32gc    fdqh_div_4_4_rv32gc    
+IEEE754         1
+
 deriv fdqh_ieee_div_2_1_rv64gc    fdqh_div_2_1_rv64gc    
 IEEE754         1
 
@@ -1078,4 +1120,231 @@ IEEE754         1
 deriv fdqh_ieee_div_4_4_rv64gc    fdqh_div_4_4_rv64gc    
 IEEE754         1
 
+#### DIVIDER VARIANTS WITH IDIV ON FPU
+
+deriv f_ieee_div_2_1i_rv32gc f_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_2_2i_rv32gc f_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_2_4i_rv32gc f_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_1i_rv32gc f_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_2i_rv32gc f_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_4i_rv32gc f_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_2_1i_rv64gc f_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_2_2i_rv64gc f_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_2_4i_rv64gc f_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_1i_rv64gc f_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_2i_rv64gc f_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv f_ieee_div_4_4i_rv64gc f_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
+#### FH_only, RK variable
+deriv fh_ieee_div_2_1i_rv32gc fh_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_2_2i_rv32gc fh_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_2_4i_rv32gc fh_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_1i_rv32gc fh_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_2i_rv32gc fh_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_4i_rv32gc fh_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_2_1i_rv64gc fh_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_2_2i_rv64gc fh_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_2_4i_rv64gc fh_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_1i_rv64gc fh_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_2i_rv64gc fh_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fh_ieee_div_4_4i_rv64gc fh_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
+# FD only , rk variable
+
+deriv fd_ieee_div_2_1i_rv32gc fd_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_2_2i_rv32gc fd_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_2_4i_rv32gc fd_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_1i_rv32gc fd_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_2i_rv32gc fd_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_4i_rv32gc fd_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_2_1i_rv64gc fd_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_2_2i_rv64gc fd_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_2_4i_rv64gc fd_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_1i_rv64gc fd_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_2i_rv64gc fd_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fd_ieee_div_4_4i_rv64gc fd_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
+# FDH only , rk variable
+
+deriv fdh_ieee_div_2_1i_rv32gc fdh_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_2_2i_rv32gc fdh_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_2_4i_rv32gc fdh_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_1i_rv32gc fdh_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_2i_rv32gc fdh_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_4i_rv32gc fdh_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_2_1i_rv64gc fdh_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_2_2i_rv64gc fdh_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_2_4i_rv64gc fdh_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_1i_rv64gc fdh_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_2i_rv64gc fdh_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdh_ieee_div_4_4i_rv64gc fdh_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
+# FDQ only , rk variable
+
+deriv fdq_ieee_div_2_1i_rv32gc fdq_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_2_2i_rv32gc fdq_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_2_4i_rv32gc fdq_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_1i_rv32gc fdq_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_2i_rv32gc fdq_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_4i_rv32gc fdq_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_2_1i_rv64gc fdq_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_2_2i_rv64gc fdq_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_2_4i_rv64gc fdq_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_1i_rv64gc fdq_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_2i_rv64gc fdq_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdq_ieee_div_4_4i_rv64gc fdq_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
+# FDQH only , rk variable
+
+deriv fdqh_ieee_div_2_1i_rv32gc fdqh_ieee_div_2_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_2_2i_rv32gc fdqh_ieee_div_2_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_2_4i_rv32gc fdqh_ieee_div_2_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_1i_rv32gc fdqh_ieee_div_4_1_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_2i_rv32gc fdqh_ieee_div_4_2_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_4i_rv32gc fdqh_ieee_div_4_4_rv32gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_2_1i_rv64gc fdqh_ieee_div_2_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_2_2i_rv64gc fdqh_ieee_div_2_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_2_4i_rv64gc fdqh_ieee_div_2_4_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_1i_rv64gc fdqh_ieee_div_4_1_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_2i_rv64gc fdqh_ieee_div_4_2_rv64gc        
+IDIV_ON_FPU     1
+
+deriv fdqh_ieee_div_4_4i_rv64gc fdqh_ieee_div_4_4_rv64gc        
+IDIV_ON_FPU     1
+
 
diff --git a/sim/regression-wally b/sim/regression-wally
index 42c54d016..7c940f82b 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -313,40 +313,30 @@ for test in tests32e:
 # softfloat tests
 if (softfloat):
     configs = []
-    softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \
-    'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \
-    'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \
-    'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \
-    'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \
-    'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \
-    'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \
-    'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc']
-    softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \
-    'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \
-    'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \
-    'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \
-    'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \
-    'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \
-    'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \
-    'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \
-    'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \
-    'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \
-    'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \
-    'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\
-    'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \
-    'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\
-    'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \
-    'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \
-    'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \
-    'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \
-    'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\
-    'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\
-    'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \
-    'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \
-    'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \
-    'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \
-    'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \
-    'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc']
+    softfloatconfigs = [
+    "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
+    "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
+    "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
+    "fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv64gc", "fd_ieee_div_2_1_rv32gc",
+    "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc", "fd_ieee_div_2_2_rv64gc",
+    "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc", "fd_ieee_div_4_1_rv32gc",
+    "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc", "fd_ieee_div_4_2_rv64gc",
+    "fd_ieee_div_4_4_rv64gc", "fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc",
+    "fdqh_ieee_div_2_2_rv32gc", "fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc",
+    "fdqh_ieee_div_2_4_rv64gc", "fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc",
+    "fdqh_ieee_div_4_2_rv32gc", "fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv64gc",
+    "fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc",
+    "fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc",
+    "fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc",
+    "fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv64gc", "fh_ieee_div_2_1_rv32gc",
+    "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc", "fh_ieee_div_2_2_rv64gc",
+    "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc", "fh_ieee_div_4_1_rv32gc",
+    "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc", "fh_ieee_div_4_2_rv64gc",
+    "fh_ieee_div_4_4_rv64gc", "f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc",
+    "f_ieee_div_2_2_rv32gc", "f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc",
+    "f_ieee_div_2_4_rv64gc", "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc",
+    "f_ieee_div_4_2_rv32gc", "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv64gc"
+    ]
     for config in softfloatconfigs:
         # div test case
         divtest = TestCase(