From adcc7afffa5bf35d3fbee321c794fd1441cbe777 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 7 Jul 2021 17:52:16 -0500 Subject: [PATCH 01/47] Partial implementation of the data cache. Missing the fsm. --- wally-pipelined/src/cache/DCacheMem.sv | 107 ++++++++++++ wally-pipelined/src/cache/ICacheMem.sv | 4 +- wally-pipelined/src/cache/dcache.sv | 221 +++++++++++++++++++++++++ wally-pipelined/src/lsu/dcache.sv | 184 -------------------- 4 files changed, 330 insertions(+), 186 deletions(-) create mode 100644 wally-pipelined/src/cache/DCacheMem.sv create mode 100644 wally-pipelined/src/cache/dcache.sv delete mode 100644 wally-pipelined/src/lsu/dcache.sv diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv new file mode 100644 index 000000000..b82858dbc --- /dev/null +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -0,0 +1,107 @@ +/////////////////////////////////////////// +// DCacheMem (Memory for the Data Cache) +// +// Written: ross1728@gmail.com July 07, 2021 +// Implements the data, tag, valid, dirty, and replacement bits. +// +// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26) + (input logic clk, + input logic reset, + + input logic [$clog2(NUMLINES)-1:0] Adr, + input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only + input logic WriteEnable, + input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, + input logic [BLOCKLEN-1:0] WriteData, + input logic [TAGLEN-1:0] WriteTag, + input logic SetValid, + input logic ClearValid, + input logic SetDirty, + input logic ClearDirty, + + output logic [BLOCKLEN-1:0] ReadData, + output logic [TAGLEN-1:0] ReadTag, + output logic Valid, + output logic Dirty + ); + + genvar words; + + generate + for(words = 0; words < BLOCKLEN/`XLEN; words++) begin + sram1rw #(.DEPTH(`XLEN), + .WIDTH(NUMLINES)) + CacheDataMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadData[(words+1)*`XLEN-1:words*`XLEN]), + .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), + .WriteEnable(WriteEnable & WriteWordEnable[words])); + end + endgenerate + + sram1rw #(.DEPTH(TAGLEN), + .WIDTH(NUMLINES)) + CacheTagMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadTag), + .WriteData(WriteTag), + .WriteEnable(WriteEnable)); + + + sram1rw #(.DEPTH(BLOCKLEN), + .WIDTH(NUMLINES)) + CacheDataMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadData), + .WriteData(WriteData), + .WriteEnable(WriteEnable)); + + sram1rw #(.DEPTH(TAGLEN), + .WIDTH(NUMLINES)) + CacheTagMem(.clk(clk), + .Addr(Adr), + .ReadData(ReadTag), + .WriteData(WriteTag), + .WriteEnable(WriteEnable)); + + always_ff @(posedge clk, posedge reset) begin + if (reset) + ValidBits <= {NUMLINES{1'b0}}; + else if (SetValid & WriteEnable) ValidBits[WAdr] <= 1'b1; + else if (ClearValid & WriteEnable) ValidBits[WAdr] <= 1'b0; + Valid <= ValidBits[Adr]; + end + + always_ff @(posedge clk, posedge reset) begin + if (reset) + DirtyBits <= {NUMLINES{1'b0}}; + else if (SetDirty & WriteEnable) DirtyBits[WAdr] <= 1'b1; + else if (ClearDirty & WriteEnable) DirtyBits[WAdr] <= 1'b0; + Dirty <= DirtyBits[Adr]; + end + + +endmodule; // DCacheMemWay + + diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index 9a5fdbe2f..ce3507ba1 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) // If flush is high, invalidate the entire cache input logic flush, - input logic [`PA_BITS-1:0] PCTagF, // physical address - input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address + input logic [`PA_BITS-1:0] PCTagF, // physical address + input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address input logic WriteEnable, input logic [BLOCKLEN-1:0] WriteLine, output logic [BLOCKLEN-1:0] ReadLineF, diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv new file mode 100644 index 000000000..54b5276d9 --- /dev/null +++ b/wally-pipelined/src/cache/dcache.sv @@ -0,0 +1,221 @@ +/////////////////////////////////////////// +// dcache (data cache) +// +// Written: ross1728@gmail.com July 07, 2021 +// Implements the L1 data cache +// +// Purpose: Storage for data and meta data. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module dcache + (input logic clk, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, + + // cpu side + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [1:0] AtomicM, + input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] MemPAdrM, // physical address + + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] ReadDataW, + output logic DCacheStall, + + // inputs from TLB and PMA/P + input logic FaultM, + input logic DTLBMissM, + // ahb side + output logic [`PA_BITS-1:0] AHBPAdr, // to ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb + input logic [`XLEN-1:0] HRDATA, // from ahb + output logic [`XLEN-1:0] HWDATA, // to ahb + output logic [2:0] AHBSize + ); + + localparam integer BLOCKLEN = 256; + localparam integer NUMLINES = 512; + localparam integer NUMWAYS = 4; + localparam integer NUMREPL_BITS = 3; + + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + + + logic [1:0] AdrSel; + logic [`PA_BITS-1:0] MemPAdrW; + logic [INDEXLEN-1:0] SRAMAdr; + logic [NUMWAYS-1:0] WriteEnable; + logic [NUMWAYS-1:0] WriteWordEnable; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic [TAGLEN-1:0] WriteTag; + logic SetValid, ClearValid; + logic SetDirty, ClearDirty; + logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] Valid, Dirty, WayHit; + logic Hit; + logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; + logic [BLOCKLEN-1:0] ReadDataSelectWayM; + logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [`XLEN-1:0] WriteDataW, FinalWriteDataW; + logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + + + typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_WRITE_BACK, + STATE_MISS_READ_SRAM, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_WRITE_BACK, + STATE_AMO_MISS_READ_SRAM, + STATE_AMO_MISS_UPDATE, + STATE_AMO_MISS_WRITE, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_FETCH, + STATE_UNCACHED} statetype; + + statetype CurrState, NextState; + + + flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), + .en(~StallW), + .d(MemPAdrM), + .q(MemPAdrW)); + + mux3 #(INDEXLEN) + AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), + .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), + .d2(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .s(AdrSel), + .y(SRAMAdr)); + + genvar way; + generate + for(way = 0; way < NUMWAYS; way = way + 1) begin + DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) + MemWay(.clk(clk), + .reset(reset), + .Adr(SRAMAdr), + .WAdr(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .WriteEnable(SRAMWriteEnable[way]), + .WriteWordEnable(SRAMWordEnable[way]), + .WriteData(SRAMWriteData), + .WriteTag(WriteTag), + .SetValid(SetValid), + .ClearValid(ClearValid), + .SetDirty(SetDirty), + .ClearDirty(ClearDirty), + .ReadData(ReadDataM[way]), + .ReadTag(ReadTag[way]), + .Valid(Valid[way]), + .Dirty(Dirty[way])); + assign WayHit = Valid & (ReadTag[way] == MemAdrM); + assign ReadDataMaskedM = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + end + endgenerate + + always_ff @(posedge clk, posedge reset) begin + if (reset) ReplacementBits <= '0; + else if (WriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + end + + assign Hit = |WayHit; + assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. + + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can + // easily build a variable input mux. + genvar index; + generate + for (index = 0; index < WORDSPERLINE; index++) begin + assign ReadDataSelectWayM[index] = ReadDataSelectM[((index+1)*`XLEN)-1: (index*`XLEN)]; + end + endgenerate + + // variable input mux + assign WordReadDataM = ReadDataSelectWayM[MemPAdrM[WORDSPERLINE+$clog2(`XLEN/8) : $clog2(`XLEN/8)]]; + // finally swr + subwordread subwordread(.HRDATA(WordReadDataM), + .HADDRD(MemPAdrM[`XLEN/8-1:0]), + .HSIZED(Funct3M), + .HRDATAMasked(FinalReadDataM)); + + flopen #(XLEN) ReadDataWReg(.clk(clk), + .en(~StallW), + .d(FinalReadDataM), + .q(ReadDataW)); + + // write path + flopen #(XLEN) WriteDataWReg(.clk(clk), + .en(~StallW), + .d(WriteDataM), + .q(WriteDataW)); + + subwordwrite subwordwrite(.HRDATA(ReadDataW), + .HADDRD(MemPAdrM[`XLEN/8-1:0]), + .HSIZED(Funct3W), + .HWDATAIN(WriteDataW), + .HWDATA(FinalWriteDataW)); + + // register the fetch data from the next level of memory. + generate + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + flopen #(`XLEN) fb(.clk(clk), + .en(AHBAck & (index == FetchCount)), + .d(HRDATA), + .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); + end + endgenerate + + // mux between the CPU's write and the cache fetch. + generate + for(index = 0; index < WORDSPERLINE; index++) begin + assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataW; + end + endgenerate + + mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), + .d1(DCacheMemWriteData), + .s(SelMemWriteData), + .y(SRAMWriteData)); + + + + + +endmodule; // dcache + + diff --git a/wally-pipelined/src/lsu/dcache.sv b/wally-pipelined/src/lsu/dcache.sv deleted file mode 100644 index e8dfeb5cd..000000000 --- a/wally-pipelined/src/lsu/dcache.sv +++ /dev/null @@ -1,184 +0,0 @@ -/////////////////////////////////////////// -// dcache.sv -// -// Written: jaallen@g.hmc.edu 2021-04-15 -// Modified: -// -// Purpose: Cache memory for the dmem so it can access memory less often, saving cycles -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -`include "wally-config.vh" - -module dcache( - // Basic pipeline stuff - input logic clk, reset, - input logic StallW, - input logic FlushW, - // Upper bits of physical address - input logic [`PA_BITS-1:12] UpperPAdrM, - // Lower 12 bits of virtual address, since it's faster this way - input logic [11:0] LowerVAdrM, - // Write to the dcache - input logic [`XLEN-1:0] DCacheWriteDataM, - input logic DCacheReadM, DCacheWriteM, - // Data read in from the ebu unit - input logic [`XLEN-1:0] ReadDataW, - input logic MemAckW, - // Access requested from the ebu unit - output logic [`PA_BITS-1:0] MemPAdrM, - output logic MemReadM, MemWriteM, - // High if the dcache is requesting a stall - output logic DCacheStallW, - // The data that was requested from the cache - output logic [`XLEN-1:0] DCacheReadW -); - - // Configuration parameters - // TODO Move these to a config file - localparam integer DCACHELINESIZE = 256; - localparam integer DCACHENUMLINES = 512; - - // Input signals to cache memory - logic FlushMem; - logic [`PA_BITS-1:12] DCacheMemUpperPAdr; - logic [11:0] DCacheMemLowerAdr; - logic DCacheMemWriteEnable; - logic [DCACHELINESIZE-1:0] DCacheMemWriteData; - logic [`XLEN-1:0] DCacheMemWritePAdr; - logic EndFetchState; - // Output signals from cache memory - logic [`XLEN-1:0] DCacheMemReadData; - logic DCacheMemReadValid; - - wtdirectmappedmem #(.LINESIZE(DCACHELINESIZE), .NUMLINES(DCACHENUMLINES), .WORDSIZE(`XLEN)) cachemem( - .*, - // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall - .stall(StallW), - .flush(FlushMem), - .ReadUpperPAdr(DCacheMemUpperPAdr), - .ReadLowerAdr(DCacheMemLowerAdr), - .LoadEnable(DCacheMemWriteEnable), - .LoadLine(DCacheMemWriteData), - .LoadPAdr(DCacheMemWritePAdr), - .DataWord(DCacheMemReadData), - .DataValid(DCacheMemReadValid), - .WriteEnable(0), - .WriteWord(0), - .WritePAdr(0), - .WriteSize(2'b10) - ); - - dcachecontroller #(.LINESIZE(DCACHELINESIZE)) controller(.*); - - // For now, assume no writes to executable memory - assign FlushMem = 1'b0; -endmodule - -module dcachecontroller #(parameter LINESIZE = 256) ( - // Inputs from pipeline - input logic clk, reset, - input logic StallW, - input logic FlushW, - - // Input the address to read - // The upper bits of the physical pc - input logic [`PA_BITS-1:12] DCacheMemUpperPAdr, - // The lower bits of the virtual pc - input logic [11:0] DCacheMemLowerAdr, - - // Signals to/from cache memory - // The read coming out of it - input logic [`XLEN-1:0] DCacheMemReadData, - input logic DCacheMemReadValid, - // Load data into the cache - output logic DCacheMemWriteEnable, - output logic [LINESIZE-1:0] DCacheMemWriteData, - output logic [`XLEN-1:0] DCacheMemWritePAdr, - - // The read that was requested - output logic [31:0] DCacheReadW, - - // Outputs to pipeline control stuff - output logic DCacheStallW, EndFetchState, - - // Signals to/from ahblite interface - // A read containing the requested data - input logic [`XLEN-1:0] ReadDataW, - input logic MemAckW, - // The read we request from main memory - output logic [`PA_BITS-1:0] MemPAdrM, - output logic MemReadM, MemWriteM -); - - // Cache fault signals - logic FaultStall; - - // Handle happy path (data in cache) - - always_comb begin - DCacheReadW = DCacheMemReadData; - end - - - // Handle cache faults - - localparam integer WORDSPERLINE = LINESIZE/`XLEN; - localparam integer LOGWPL = $clog2(WORDSPERLINE); - localparam integer OFFSETWIDTH = $clog2(LINESIZE/8); - - logic FetchState, BeginFetchState; - logic [LOGWPL:0] FetchWordNum, NextFetchWordNum; - logic [`PA_BITS-1:0] LineAlignedPCPF; - - flopr #(1) FetchStateFlop(clk, reset, BeginFetchState | (FetchState & ~EndFetchState), FetchState); - flopr #(LOGWPL+1) FetchWordNumFlop(clk, reset, NextFetchWordNum, FetchWordNum); - - genvar i; - generate - for (i=0; i < WORDSPERLINE; i++) begin:sb - flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), ReadDataW, DCacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]); - end - endgenerate - - // Enter the fetch state when we hit a cache fault - always_comb begin - BeginFetchState = ~DCacheMemReadValid & ~FetchState & (FetchWordNum == 0); - end - // Exit the fetch state once the cache line has been loaded - flopr #(1) EndFetchStateFlop(clk, reset, DCacheMemWriteEnable, EndFetchState); - - // Machinery to request the correct addresses from main memory - always_comb begin - MemReadM = FetchState & ~EndFetchState & ~DCacheMemWriteEnable; - LineAlignedPCPF = {DCacheMemUpperPAdr, DCacheMemLowerAdr[11:OFFSETWIDTH], {OFFSETWIDTH{1'b0}}}; - MemPAdrM = LineAlignedPCPF + FetchWordNum*(`XLEN/8); - NextFetchWordNum = FetchState ? FetchWordNum+MemAckW : {LOGWPL+1{1'b0}}; - end - - // Write to cache memory when we have the line here - always_comb begin - DCacheMemWritePAdr = LineAlignedPCPF; - DCacheMemWriteEnable = FetchWordNum == {1'b1, {LOGWPL{1'b0}}} & FetchState & ~EndFetchState; - end - - // Stall the pipeline while loading a new line from memory - always_comb begin - DCacheStallW = FetchState | ~DCacheMemReadValid; - end -endmodule From 4c5aee3042191d867dcffdc77d80a97dfac8ae8c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 15:26:16 -0500 Subject: [PATCH 02/47] This d cache fsm is getting complex. --- wally-pipelined/src/cache/ICacheCntrl.sv | 1 + wally-pipelined/src/cache/dcache.sv | 387 +++++++++++++++++------ 2 files changed, 298 insertions(+), 90 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index e7098d755..2b5ce55df 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -413,6 +413,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) assign NextFetchCount = FetchCount + 1'b1; // This part is confusing. + // *** Ross Thompson reduce the complexity. This is just dumb. // we need to remove the offset bits (PCPTrunkF). Because the AHB interface is XLEN wide // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 54b5276d9..2988c6a4e 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -5,125 +5,130 @@ // Implements the L1 data cache // // Purpose: Storage for data and meta data. -// +// // A component of the Wally configurable RISC-V project. -// +// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software // is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// `include "wally-config.vh" module dcache - (input logic clk, - input logic reset, - input logic StallM, - input logic StallW, - input logic FlushM, - input logic FlushW, + (input logic clk, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [1:0] AtomicM, + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [1:0] AtomicM, input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - - input logic [`XLEN-1:0] WriteDataM, + + input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic DCacheStall, + output logic DCacheStall, // inputs from TLB and PMA/P - input logic FaultM, - input logic DTLBMissM, + input logic FaultM, + input logic DTLBMissM, + input logic UncachedM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - output logic AHBRead, - output logic AHBWrite, - input logic AHBAck, // from ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb input logic [`XLEN-1:0] HRDATA, // from ahb - output logic [`XLEN-1:0] HWDATA, // to ahb - output logic [2:0] AHBSize + output logic [`XLEN-1:0] HWDATA, // to ahb + output logic [2:0] AHBSize ); - localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; - localparam integer NUMWAYS = 4; - localparam integer NUMREPL_BITS = 3; + localparam integer BLOCKLEN = 256; + localparam integer NUMLINES = 512; + localparam integer NUMWAYS = 4; + localparam integer NUMREPL_BITS = 3; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer LOGWPL = $clog2(WORDSPERLINE); + - logic [1:0] AdrSel; - logic [`PA_BITS-1:0] MemPAdrW; - logic [INDEXLEN-1:0] SRAMAdr; - logic [NUMWAYS-1:0] WriteEnable; - logic [NUMWAYS-1:0] WriteWordEnable; - logic [BLOCKLEN-1:0] SRAMWriteData; - logic [TAGLEN-1:0] WriteTag; - logic SetValid, ClearValid; - logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; - logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] Valid, Dirty, WayHit; - logic Hit; + logic SelAdrM; + logic [`PA_BITS-1:0] MemPAdrW; + logic [INDEXLEN-1:0] SRAMAdr; + logic [NUMWAYS-1:0] WriteEnable; + logic [NUMWAYS-1:0] WriteWordEnable; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic SetValidM, ClearValidM, SetValidW, ClearValidW; + logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; + logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] Valid, Dirty, WayHit; + logic CacheHit; logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; - logic [BLOCKLEN-1:0] ReadDataSelectWayM; - logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; - logic [`XLEN-1:0] WriteDataW, FinalWriteDataW; - logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [BLOCKLEN-1:0] ReadDataSelectWayM; + logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; + logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [LOGWPL:0] FetchCount, NextFetchCount; + logic [NUMWAYS-1:0] SRAMWordWriteEnableM, SRAMWordWriteEnableW; + logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; + logic SelMemWriteDataM, SelMemWriteDataW; + logic [2:0] Funct3W; + + logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; + logic SRAMBlockWriteEnableM; + logic SRAMWriteEnable; + + logic SaveSRAMRead; + logic [1:0] AtomicW; + + - typedef enum {STATE_READY, - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_WRITE_BACK, - STATE_MISS_READ_SRAM, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_WRITE_BACK, - STATE_AMO_MISS_READ_SRAM, - STATE_AMO_MISS_UPDATE, - STATE_AMO_MISS_WRITE, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_SRAM_BUSY, - STATE_PTW_READY, - STATE_PTW_FETCH, - STATE_UNCACHED} statetype; - - statetype CurrState, NextState; + // data path flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), .en(~StallW), .d(MemPAdrM), .q(MemPAdrW)); - mux3 #(INDEXLEN) + mux2 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), - .d2(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), - .s(AdrSel), - .y(SRAMAdr)); + .s(SelAdrM), + .y(AdrMuxOut)); - genvar way; + + mux2 #(INDEXLEN) + SelAdrlMux2(.d0(AdrMuxOut), + .d1(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .s(SRAMWordWriteEnableW), + .y(SRAMAdr)); + + + genvar way; generate for(way = 0; way < NUMWAYS; way = way + 1) begin DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) @@ -134,11 +139,11 @@ module dcache .WriteEnable(SRAMWriteEnable[way]), .WriteWordEnable(SRAMWordEnable[way]), .WriteData(SRAMWriteData), - .WriteTag(WriteTag), - .SetValid(SetValid), - .ClearValid(ClearValid), - .SetDirty(SetDirty), - .ClearDirty(ClearDirty), + .WriteTag(MemPAdrW[`PA_BITS-1:OFFSET+INDEXLEN]), + .SetValid(SetValidW), + .ClearValid(ClearValidW), + .SetDirty(SetDirtyW), + .ClearDirty(ClearDirtyW), .ReadData(ReadDataM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), @@ -150,10 +155,13 @@ module dcache always_ff @(posedge clk, posedge reset) begin if (reset) ReplacementBits <= '0; - else if (WriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; end - - assign Hit = |WayHit; + + // *** TODO add replacement policy + assign NewReplacement = '0; + + assign CacheHit = |WayHit; assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can @@ -183,13 +191,29 @@ module dcache .en(~StallW), .d(WriteDataM), .q(WriteDataW)); - + + flopr #(3) Funct3WReg(.clk(clk), + .reset(reset), + .d(Funct3M), + .q(Funct3W)); + subwordwrite subwordwrite(.HRDATA(ReadDataW), .HADDRD(MemPAdrM[`XLEN/8-1:0]), .HSIZED(Funct3W), .HWDATAIN(WriteDataW), .HWDATA(FinalWriteDataW)); + generate + if (`A_SUPPORTED) begin + logic [`XLEN-1:0] AMOResult; + amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W), + .result(AMOResult)); + mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); + end else + assign FinalAMOWriteDataW = FinalWriteDataW; + endgenerate + + // register the fetch data from the next level of memory. generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer @@ -199,23 +223,206 @@ module dcache .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); end endgenerate + + flopenr #(LOGWPL+1) + FetchCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); + + assign NextFetchCount = FetchCount + 1'b1; + + assign AHBPAdr = (FetchCount << (`XLEN/8)) + MemPAdrM; + // remove later + assign AHBSize = 3'b000; + // mux between the CPU's write and the cache fetch. generate for(index = 0; index < WORDSPERLINE; index++) begin - assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataW; + assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataW; end endgenerate mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), .d1(DCacheMemWriteData), - .s(SelMemWriteData), + .s(SRAMBlockWriteEnableM), .y(SRAMWriteData)); + + // control path *** eventually move to own module. + + logic AnyCPUReqM; + logic FetchCountFlag; + logic PreCntEn; + logic CntEn; + logic CntReset; + + typedef enum {STATE_READY, + STATE_READ_MISS_FETCH_WDV, + STATE_READ_MISS_FETCH_DONE, + STATE_READ_MISS_CHECK_EVICTED_DIRTY, + STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_READ_MISS_WRITE_CACHE_BLOCK, + STATE_READ_MISS_READ_WORD, + STATE_WRITE_MISS_FETCH_WDV, + STATE_WRITE_MISS_FETCH_DONE, + STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_WRITE_MISS_WRITE_CACHE_BLOCK, + STATE_WRITE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WDV, + STATE_UNCACHED_DONE} statetype; + + statetype CurrState, NextState; + localparam FetchCountThreshold = WORDSPERLINE - 1; + + assign AnyCPUReqM = |MemRWM | (|AtomicM); + assign FetchCountFlag = (FetchCount == FetchCountThreshold); + + flopenr #(LOGWPL+1) + FetchCountReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); + + assign NextFetchCount = FetchCount + 1'b1; + + assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableW; + + flopr #(1+4+2) + SRAMWritePipeReg(.clk(clk), + .reset(reset), + .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDiryM, ClearDirtyM, AtomicM}), + .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDiryM, ClearDirtyM, AtomicW})); + + + // fsm state regs + flopenl #(.TYPE(statetype)) + FSMReg(.clk(clk), + .load(reset), + .en(1'b1), + .val(STATE_READY), + .d(NextState), + .q(CurrState)); + + // next state logic and some state ouputs. + always_comb begin + DCacheStall = 1'b0; + SelAdrM = 2'b00; + PreCntEn = 1'b0; + SetValidM = 1'b0; + ClearValidM = 1'b0; + SetDirtyM = 1'b0; + ClearDirtyM = 1'b0; + SelMemWriteDataM = 1'b0; + SRAMWordWriteEnableM = 1'b0; + SRAMBlockWriteEnableM = 1'b0; + SaveSRAMRead = 1'b1; + CntReset = 1'b0; + + case (CurrState) + STATE_READY: begin + // sram busy + if (AnyCPUReqM & SRAMWordWriteEnableW) begin + NextState = STATE_BUSY; + DCacheStall = 1'b1; + end + // TLB Miss + else if(AnyCPUReqM & DTLBMissM) begin + NextState = STATE_PTW_MISS_FETCH_WDV; + end + // amo hit + else if(|AtomicM & ~UncachedM & ~FSMReg & CacheHit & ~DTLBMissM) begin + NextState = STATE_AMO_UPDATE; + DCacheStall = 1'b1; + end + // read hit valid cached + else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end + // write hit valid cached + else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + end + // read miss valid cached + else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_READ_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + // fault + else if(|MemRWM & FaultM & ~DTLBMissM) begin + NextState = STATE_READY; + end + end + STATE_AMO_UPDATE: begin + NextState = STATE_AMO_WRITE; + SaveSRAMRead = 1'b1; + SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle + end + STATE_AMO_WRITE: begin + NextState = STATE_READY; + SelAMOWrite = 1'b1; + end + + STATE_READ_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_READ_MISS_FETCH_DONE; + end else begin + NextState = STATE_READ_MISS_FETCH_WDV; + end + end + + STATE_READ_MISS_FETCH_DONE: begin + DCacheStall = 1'b1; + NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + end + + STATE_PTW_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + AdrSel = 2'b01; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_PTW_MISS_FETCH_DONE; + end else begin + NextState = STATE_PTW_MISS_FETCH_WDV; + end + end + default: begin + end + endcase + end + + assign CntEn = PreCntEn & AHBAck; + endmodule; // dcache - - From 6041aef263a4aa6024409dd119beee1f5cc48f9f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 17:53:08 -0500 Subject: [PATCH 03/47] completed read miss branch through dcache fsm. The challenge now is to connect to ahb and lsu. --- wally-pipelined/src/cache/dcache.sv | 42 ++++++++++++++++++++++++++--- wally-pipelined/src/ebu/ahblite.sv | 7 +---- wally-pipelined/src/ifu/ifu.sv | 2 -- 3 files changed, 39 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 2988c6a4e..84370328d 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -81,6 +81,7 @@ module dcache logic SetValidM, ClearValidM, SetValidW, ClearValidW; logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] VictimReadDataMaskedM [NUMWAYS-1:0]; logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; @@ -102,7 +103,11 @@ module dcache logic SaveSRAMRead; logic [1:0] AtomicW; - + logic [NUMWAYS-1:0] VictimWay; + logic [NUMWAYS-1:0] VictimDirtyWay; + logic [BLOCKLEN-1:0] VictimReadDataSelectWayM; + logic VictimDirty; + @@ -149,7 +154,11 @@ module dcache .Valid(Valid[way]), .Dirty(Dirty[way])); assign WayHit = Valid & (ReadTag[way] == MemAdrM); - assign ReadDataMaskedM = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + assign ReadDataMaskedM[way] = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + + // the cache block candiate for eviction + assign VictimReadDataMaskedM[way] = VictimWay[way] & ReadDataM[way]; + assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; end endgenerate @@ -160,9 +169,14 @@ module dcache // *** TODO add replacement policy assign NewReplacement = '0; + assign VictimWay = 4'b0001; + assign SRAMWriteEnable = SRAMBlockWriteEnableM ? VictimWay : '0; assign CacheHit = |WayHit; assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. + assign VictimReadDataSelectWayM = | VictimReadDataMaskedM; + assign VictimDirty = | VictimDirtyWay; + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. @@ -344,7 +358,9 @@ module dcache SRAMBlockWriteEnableM = 1'b0; SaveSRAMRead = 1'b1; CntReset = 1'b0; - + AHBRead = 1'b0; + AHBWrite = 1'b0; + case (CurrState) STATE_READY: begin // sram busy @@ -397,6 +413,7 @@ module dcache STATE_READ_MISS_FETCH_WDV: begin DCacheStall = 1'b1; PreCntEn = 1'b1; + AHBRead = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_READ_MISS_FETCH_DONE; end else begin @@ -406,7 +423,24 @@ module dcache STATE_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + if(VictimDirt) begin + NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; + end else begin + NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; + end + end + + STATE_READ_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_READ_MISS_READ_WORD; + SelAdrM = 1'b1; + end + + STATE_READ_MISS_READ_WORD: begin + DCacheStall = 1'b1; + SelAdrM = 1'b1; + NextState = STATE_READY; end STATE_PTW_MISS_FETCH_WDV: begin diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 4bd079e96..fda8f693d 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -109,16 +109,11 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: /*if (MMUTranslate) ProposedNextBusState = MMUTRANSLATE; - else*/ if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; + IDLE: if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions else if (MemWriteM) ProposedNextBusState = MEMWRITE; else if (InstrReadF) ProposedNextBusState = INSTRREAD; else ProposedNextBusState = IDLE; -/* -----\/----- EXCLUDED -----\/----- - MMUTRANSLATE: if (~HREADY) ProposedNextBusState = MMUTRANSLATE; - else ProposedNextBusState = IDLE; - -----/\----- EXCLUDED -----/\----- */ ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD; else ProposedNextBusState = ATOMICWRITE; ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 8b113f8cd..e306efa40 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -84,8 +84,6 @@ module ifu ( output logic InstrAccessFaultF, output logic ISquashBusAccessF -// output logic [5:0] IHSELRegionsF - ); logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; From 2efb7a4f81d8871997e00887ca44d3e5283d31a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 8 Jul 2021 18:03:52 -0500 Subject: [PATCH 04/47] Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. --- wally-pipelined/src/lsu/lsu.sv | 128 ++++++++++----------- wally-pipelined/src/lsu/lsuArb.sv | 42 +++---- wally-pipelined/src/mmu/pagetablewalker.sv | 36 +++--- 3 files changed, 103 insertions(+), 103 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index ff47138c4..51fa0a4af 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -123,22 +123,22 @@ module lsu logic [`XLEN-1:0] PageTableEntryM; logic [1:0] PageTypeM; logic DTLBWriteM; - logic [`XLEN-1:0] MMUReadPTE; + logic [`XLEN-1:0] HPTWReadPTE; logic MMUReady; logic HPTWStall; - logic [`XLEN-1:0] MMUPAdr; - logic MMUTranslate; + logic [`XLEN-1:0] HPTWPAdr; + logic HPTWTranslate; logic HPTWRead; - logic [1:0] MemRWMtoLSU; - logic [2:0] SizeToLSU; - logic [1:0] AtomicMtoLSU; - logic [`XLEN-1:0] MemAdrMtoLSU; - logic [`XLEN-1:0] WriteDataMtoLSU; - logic [`XLEN-1:0] ReadDataWFromLSU; - logic StallWtoLSU; - logic CommittedMfromLSU; - logic SquashSCWfromLSU; - logic DataMisalignedMfromLSU; + logic [1:0] MemRWMtoDCache; + logic [2:0] SizetoDCache; + logic [1:0] AtomicMtoDCache; + logic [`XLEN-1:0] MemAdrMtoDCache; + logic [`XLEN-1:0] WriteDataMtoDCache; + logic [`XLEN-1:0] ReadDataWfromDCache; + logic StallWtoDCache; + logic CommittedMfromDCache; + logic SquashSCWfromDCache; + logic DataMisalignedMfromDCache; logic HPTWReady; logic LSUStall; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. @@ -148,7 +148,7 @@ module lsu // for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the // CPU's read data input ReadDataW. - assign ReadDataWFromLSU = HRDATAW; + assign ReadDataWfromDCache = HRDATAW; pagetablewalker pagetablewalker( @@ -166,11 +166,11 @@ module lsu .PageTypeM(PageTypeM), .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), - .MMUReadPTE(MMUReadPTE), + .HPTWReadPTE(HPTWReadPTE), .MMUReady(HPTWReady), .HPTWStall(HPTWStall), - .MMUPAdr(MMUPAdr), - .MMUTranslate(MMUTranslate), + .HPTWPAdr(HPTWPAdr), + .HPTWTranslate(HPTWTranslate), .HPTWRead(HPTWRead), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), @@ -182,10 +182,10 @@ module lsu lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection - .HPTWTranslate(MMUTranslate), + .HPTWTranslate(HPTWTranslate), .HPTWRead(HPTWRead), - .HPTWPAdr(MMUPAdr), - .HPTWReadPTE(MMUReadPTE), + .HPTWPAdr(HPTWPAdr), + .HPTWReadPTE(HPTWReadPTE), .HPTWStall(HPTWStall), // CPU connection .MemRWM(MemRWM), @@ -201,23 +201,23 @@ module lsu .DCacheStall(DCacheStall), // LSU .DisableTranslation(DisableTranslation), - .MemRWMtoLSU(MemRWMtoLSU), - .SizeToLSU(SizeToLSU), - .AtomicMtoLSU(AtomicMtoLSU), - .MemAdrMtoLSU(MemAdrMtoLSU), - .WriteDataMtoLSU(WriteDataMtoLSU), // *** ?????????????? - .StallWtoLSU(StallWtoLSU), - .CommittedMfromLSU(CommittedMfromLSU), - .SquashSCWfromLSU(SquashSCWfromLSU), - .DataMisalignedMfromLSU(DataMisalignedMfromLSU), - .ReadDataWFromLSU(ReadDataWFromLSU), + .MemRWMtoDCache(MemRWMtoDCache), + .SizetoDCache(SizetoDCache), + .AtomicMtoDCache(AtomicMtoDCache), + .MemAdrMtoDCache(MemAdrMtoDCache), + .WriteDataMtoDCache(WriteDataMtoDCache), // *** ?????????????? + .StallWtoDCache(StallWtoDCache), + .CommittedMfromDCache(CommittedMfromDCache), + .SquashSCWfromDCache(SquashSCWfromDCache), + .DataMisalignedMfromDCache(DataMisalignedMfromDCache), + .ReadDataWfromDCache(ReadDataWfromDCache), .DataStall(LSUStall)); mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.VirtualAddress(MemAdrMtoLSU), - .Size(SizeToLSU[1:0]), + dmmu(.VirtualAddress(MemAdrMtoDCache), + .Size(SizetoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), @@ -228,8 +228,8 @@ module lsu .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), .AtomicAccessM(AtomicMaskedM[1]), - .WriteAccessM(MemRWMtoLSU[0]), - .ReadAccessM(MemRWMtoLSU[1]), + .WriteAccessM(MemRWMtoDCache[0]), + .ReadAccessM(MemRWMtoDCache[1]), .SquashBusAccess(DSquashBusAccessM), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), @@ -237,36 +237,36 @@ module lsu .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? // Specify which type of page fault is occurring - assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLSU[1]; - assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLSU[0]; + assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1]; + assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0]; // Determine if an Unaligned access is taking place always_comb - case(SizeToLSU[1:0]) - 2'b00: DataMisalignedMfromLSU = 0; // lb, sb, lbu - 2'b01: DataMisalignedMfromLSU = MemAdrMtoLSU[0]; // lh, sh, lhu - 2'b10: DataMisalignedMfromLSU = MemAdrMtoLSU[1] | MemAdrMtoLSU[0]; // lw, sw, flw, fsw, lwu - 2'b11: DataMisalignedMfromLSU = |MemAdrMtoLSU[2:0]; // ld, sd, fld, fsd + case(SizetoDCache[1:0]) + 2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu + 2'b01: DataMisalignedMfromDCache = MemAdrMtoDCache[0]; // lh, sh, lhu + 2'b10: DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu + 2'b11: DataMisalignedMfromDCache = |MemAdrMtoDCache[2:0]; // ld, sd, fld, fsd endcase // Squash unaligned data accesses and failed store conditionals // *** this is also the place to squash if the cache is hit - // Changed DataMisalignedMfromLSU to a larger combination of trap sources + // Changed DataMisalignedMfromDCache to a larger combination of trap sources // NonBusTrapM is anything that the bus doesn't contribute to producing // By contrast, using TrapM results in circular logic errors - assign MemReadM = MemRWMtoLSU[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; - assign MemWriteM = MemRWMtoLSU[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; - assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoLSU : 2'b00 ; + assign MemReadM = MemRWMtoDCache[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; + assign MemWriteM = MemRWMtoDCache[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; + assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ; assign MemAccessM = MemReadM | MemWriteM; // Determine if M stage committed // Reset whenever unstalled. Set when access successfully occurs - flopr #(1) committedMreg(clk,reset,(CommittedMfromLSU | CommitM) & StallM,preCommittedM); - assign CommittedMfromLSU = preCommittedM | CommitM; + flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM); + assign CommittedMfromDCache = preCommittedM | CommitM; // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[1]; - assign StoreMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[0]; + assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; + assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // Handle atomic load reserved / store conditional generate @@ -275,9 +275,9 @@ module lsu logic ReservationValidM, ReservationValidW; logic lrM, scM, WriteAdrMatchM; - assign lrM = MemReadM && AtomicMtoLSU[0]; - assign scM = MemRWMtoLSU[0] && AtomicMtoLSU[0]; - assign WriteAdrMatchM = MemRWMtoLSU[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; + assign lrM = MemReadM && AtomicMtoDCache[0]; + assign scM = MemRWMtoDCache[0] && AtomicMtoDCache[0]; + assign WriteAdrMatchM = MemRWMtoDCache[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve @@ -286,10 +286,10 @@ module lsu end flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); - flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoLSU, SquashSCM, SquashSCWfromLSU); + flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCWfromDCache); end else begin // Atomic operations not supported assign SquashSCM = 0; - assign SquashSCWfromLSU = 0; + assign SquashSCWfromDCache = 0; end endgenerate @@ -319,10 +319,10 @@ module lsu end else if (AtomicMaskedM[1]) begin NextState = STATE_FETCH_AMO_1; // *** should be some misalign check LSUStall = 1'b1; - end else if((MemReadM & AtomicMtoLSU[0]) | (MemWriteM & AtomicMtoLSU[0])) begin + end else if((MemReadM & AtomicMtoDCache[0]) | (MemWriteM & AtomicMtoDCache[0])) begin NextState = STATE_FETCH_AMO_2; LSUStall = 1'b1; - end else if (MemAccessM & ~DataMisalignedMfromLSU) begin + end else if (MemAccessM & ~DataMisalignedMfromDCache) begin NextState = STATE_FETCH; LSUStall = 1'b1; end else begin @@ -339,9 +339,9 @@ module lsu end STATE_FETCH_AMO_2: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoLSU) begin + if (MemAckW & ~StallWtoDCache) begin NextState = STATE_FETCH_AMO_2; - end else if (MemAckW & StallWtoLSU) begin + end else if (MemAckW & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH_AMO_2; @@ -349,9 +349,9 @@ module lsu end STATE_FETCH: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoLSU) begin + if (MemAckW & ~StallWtoDCache) begin NextState = STATE_READY; - end else if (MemAckW & StallWtoLSU) begin + end else if (MemAckW & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH; @@ -359,7 +359,7 @@ module lsu end STATE_STALLED: begin LSUStall = 1'b0; - if (~StallWtoLSU) begin + if (~StallWtoDCache) begin NextState = STATE_READY; end else begin NextState = STATE_STALLED; @@ -370,7 +370,7 @@ module lsu if (DTLBWriteM) begin NextState = STATE_READY; LSUStall = 1'b1; - end else if (MemReadM & ~DataMisalignedMfromLSU) begin + end else if (MemReadM & ~DataMisalignedMfromDCache) begin NextState = STATE_PTW_FETCH; end else begin NextState = STATE_PTW_READY; @@ -397,8 +397,8 @@ module lsu end // always_comb // *** for now just pass through size - assign SizeFromLSU = SizeToLSU; - assign StallWfromLSU = StallWtoLSU; + assign SizeFromLSU = SizetoDCache; + assign StallWfromLSU = StallWtoDCache; endmodule diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 23e88970f..0c7730f15 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -53,17 +53,17 @@ module lsuArb // to LSU output logic DisableTranslation, - output logic [1:0] MemRWMtoLSU, - output logic [2:0] SizeToLSU, - output logic [1:0] AtomicMtoLSU, - output logic [`XLEN-1:0] MemAdrMtoLSU, - output logic [`XLEN-1:0] WriteDataMtoLSU, - output logic StallWtoLSU, + output logic [1:0] MemRWMtoDCache, + output logic [2:0] SizetoDCache, + output logic [1:0] AtomicMtoDCache, + output logic [`XLEN-1:0] MemAdrMtoDCache, + output logic [`XLEN-1:0] WriteDataMtoDCache, + output logic StallWtoDCache, // from LSU - input logic CommittedMfromLSU, - input logic SquashSCWfromLSU, - input logic DataMisalignedMfromLSU, - input logic [`XLEN-1:0] ReadDataWFromLSU, + input logic CommittedMfromDCache, + input logic SquashSCWfromDCache, + input logic DataMisalignedMfromDCache, + input logic [`XLEN-1:0] ReadDataWfromDCache, input logic DataStall ); @@ -136,25 +136,25 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); - assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw endgenerate - mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizeToLSU); + mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizetoDCache); - assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM; - assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM; - assign WriteDataMtoLSU = SelPTW ? `XLEN'b0 : WriteDataM; - assign StallWtoLSU = SelPTW ? 1'b0 : StallW; + assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; + assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; + assign WriteDataMtoDCache = SelPTW ? `XLEN'b0 : WriteDataM; + assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // demux the inputs from LSU to walker or cpu's data port. - assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWFromLSU; // probably can avoid this demux - assign HPTWReadPTE = SelPTW ? ReadDataWFromLSU : `XLEN'b0 ; // probably can avoid this demux - assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU; - assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU; - assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU; + assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux + assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux + assign CommittedM = SelPTW ? 1'b0 : CommittedMfromDCache; + assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; + assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 6357f1c6a..83d15f9b9 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -54,13 +54,13 @@ module pagetablewalker // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU - input logic [`XLEN-1:0] MMUReadPTE, + input logic [`XLEN-1:0] HPTWReadPTE, input logic MMUReady, input logic HPTWStall, // *** modify to send to LSU - output logic [`XLEN-1:0] MMUPAdr, // this probalby should be `PA_BITS wide - output logic MMUTranslate, // *** rename to HPTWReq + output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide + output logic HPTWTranslate, // *** rename to HPTWReq output logic HPTWRead, @@ -158,8 +158,8 @@ module pagetablewalker (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); - assign MMUTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; - //assign MMUTranslate = DTLBMissM | ITLBMissF; + assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; + //assign HPTWTranslate = DTLBMissM | ITLBMissF; // unswizzle PTE bits assign {Dirty, Accessed, Global, User, @@ -203,7 +203,7 @@ module pagetablewalker case (WalkerState) IDLE: begin - if (MMUTranslate && SvMode == `SV32) begin // *** Added SvMode + if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode NextWalkerState = START; end else begin NextWalkerState = IDLE; @@ -303,15 +303,15 @@ module pagetablewalker // a load delay hazard. This will require rewriting the walker fsm. // also need a new signal to save. Should be a mealy output of the fsm // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE); + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); assign CurrentPTE = SavedPTE; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces - assign MMUPAdr = TranslationPAdr[31:0]; + assign HPTWPAdr = TranslationPAdr[31:0]; end else begin @@ -326,7 +326,7 @@ module pagetablewalker WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ - //assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || WalkerState == LEVEL3 || + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || // WalkerState == LEVEL2 || WalkerState == LEVEL1; @@ -345,7 +345,7 @@ module pagetablewalker case (WalkerState) IDLE: begin - if (MMUTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin + if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin NextWalkerState = START; end else begin NextWalkerState = IDLE; @@ -353,11 +353,11 @@ module pagetablewalker end START: begin - if (MMUTranslate && SvMode == `SV48) begin + if (HPTWTranslate && SvMode == `SV48) begin NextWalkerState = LEVEL3_WDV; TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; HPTWRead = 1'b1; - end else if (MMUTranslate && SvMode == `SV39) begin + end else if (HPTWTranslate && SvMode == `SV39) begin NextWalkerState = LEVEL2_WDV; TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; HPTWRead = 1'b1; @@ -541,20 +541,20 @@ module pagetablewalker // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, PRegEn, CurrentPTE); + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); assign CurrentPTE = SavedPTE; assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; // Assign outputs to ahblite // *** Currently truncate address to 32 bits. This must be changed if // we support larger physical address spaces - assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end //endgenerate end else begin - assign MMUPAdr = 0; - assign MMUTranslate = 0; + assign HPTWPAdr = 0; + assign HPTWTranslate = 0; assign HPTWRead = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; From 6abd23a61dc9d45c231530e784598c4f6204fb4a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 15:16:38 -0500 Subject: [PATCH 05/47] Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. Also faults and the dcache ptw interlock are not implemented. --- wally-pipelined/src/cache/DCacheMem.sv | 19 +- wally-pipelined/src/cache/ICacheCntrl.sv | 1 + wally-pipelined/src/cache/dcache.sv | 190 ++++++++++-------- wally-pipelined/src/ebu/ahblite.sv | 146 ++++++-------- wally-pipelined/src/ieu/datapath.sv | 3 +- wally-pipelined/src/ieu/ieu.sv | 2 +- wally-pipelined/src/lsu/lsu.sv | 127 +++++++----- wally-pipelined/src/lsu/lsuArb.sv | 15 +- .../src/wally/wallypipelinedhart.sv | 113 +++++------ 9 files changed, 322 insertions(+), 294 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index b82858dbc..70668b5d3 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -46,6 +46,9 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 output logic Dirty ); + logic [NUMLINES-1:0] ValidBits, DirtyBits; + + genvar words; generate @@ -69,22 +72,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .WriteEnable(WriteEnable)); - sram1rw #(.DEPTH(BLOCKLEN), - .WIDTH(NUMLINES)) - CacheDataMem(.clk(clk), - .Addr(Adr), - .ReadData(ReadData), - .WriteData(WriteData), - .WriteEnable(WriteEnable)); - - sram1rw #(.DEPTH(TAGLEN), - .WIDTH(NUMLINES)) - CacheTagMem(.clk(clk), - .Addr(Adr), - .ReadData(ReadTag), - .WriteData(WriteTag), - .WriteEnable(WriteEnable)); - always_ff @(posedge clk, posedge reset) begin if (reset) ValidBits <= {NUMLINES{1'b0}}; diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 2b5ce55df..629ec7cc5 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -196,6 +196,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0; assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit. // verilator lint_off WIDTH + // *** Bug width is wrong. assign FetchCountFlag = (FetchCount == FetchCountThreshold); // verilator lint_on WIDTH diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 84370328d..65a0fe8bd 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -27,35 +27,35 @@ module dcache (input logic clk, - input logic reset, - input logic StallM, - input logic StallW, - input logic FlushM, - input logic FlushW, + input logic reset, + input logic StallM, + input logic StallW, + input logic FlushM, + input logic FlushW, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [1:0] AtomicM, - input logic [`PA_BITS-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic DCacheStall, + output logic DCacheStall, // inputs from TLB and PMA/P - input logic FaultM, - input logic DTLBMissM, - input logic UncachedM, + input logic FaultM, + input logic DTLBMissM, + input logic UncachedM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb - output logic AHBRead, - output logic AHBWrite, - input logic AHBAck, // from ahb + output logic AHBRead, + output logic AHBWrite, + input logic AHBAck, // from ahb input logic [`XLEN-1:0] HRDATA, // from ahb - output logic [`XLEN-1:0] HWDATA, // to ahb - output logic [2:0] AHBSize + output logic [`XLEN-1:0] HWDATA // to ahb ); localparam integer BLOCKLEN = 256; @@ -78,21 +78,23 @@ module dcache logic [NUMWAYS-1:0] WriteEnable; logic [NUMWAYS-1:0] WriteWordEnable; logic [BLOCKLEN-1:0] SRAMWriteData; + logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValidM, ClearValidM, SetValidW, ClearValidW; logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; - logic [BLOCKLEN-1:0] ReadDataM, ReadDataMaskedM [NUMWAYS-1:0]; - logic [BLOCKLEN-1:0] VictimReadDataMaskedM [NUMWAYS-1:0]; - logic [TAGLEN-1:0] TagData [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0]; + logic [TAGLEN-1:0] ReadTag [NUMWAYS-1:0]; logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; - logic [NUMREPL_BITS-1:0] ReplacementBits, NewReplacement; - logic [BLOCKLEN-1:0] ReadDataSelectWayM; - logic [`XLEN-1:0] ReadDataSelectWayXLEN [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] WordReadDataM, FinalReadDataM; + logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0]; + logic [NUMREPL_BITS-1:0] NewReplacement [NUMLINES-1:0]; + logic [BLOCKLEN-1:0] ReadDataBlockM; + logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [NUMWAYS-1:0] SRAMWordWriteEnableM, SRAMWordWriteEnableW; logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; logic SelMemWriteDataM, SelMemWriteDataW; logic [2:0] Funct3W; @@ -100,16 +102,27 @@ module dcache logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; logic SRAMBlockWriteEnableM; logic SRAMWriteEnable; + logic [NUMWAYS-1:0] SRAMWayWriteEnable; + logic SaveSRAMRead; logic [1:0] AtomicW; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; - logic [BLOCKLEN-1:0] VictimReadDataSelectWayM; + logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; - + logic SelAMOWrite; + logic [6:0] Funct7W; + logic [INDEXLEN-1:0] AdrMuxOut; + + flopenr #(7) Funct7WReg(.clk(clk), + .reset(reset), + .en(~StallW), + .d(Funct7M), + .q(Funct7W)); + // data path @@ -120,15 +133,15 @@ module dcache .q(MemPAdrW)); mux2 #(INDEXLEN) - AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSET-1:OFFSET]), - .d1(MemPAdrM[INDEXLEN+OFFSET-1:OFFSET]), + AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SelAdrM), .y(AdrMuxOut)); mux2 #(INDEXLEN) SelAdrlMux2(.d0(AdrMuxOut), - .d1(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), + .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); @@ -140,68 +153,89 @@ module dcache MemWay(.clk(clk), .reset(reset), .Adr(SRAMAdr), - .WAdr(MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]), - .WriteEnable(SRAMWriteEnable[way]), + .WAdr(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .WriteEnable(SRAMWayWriteEnable[way]), .WriteWordEnable(SRAMWordEnable[way]), .WriteData(SRAMWriteData), - .WriteTag(MemPAdrW[`PA_BITS-1:OFFSET+INDEXLEN]), + .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .SetValid(SetValidW), .ClearValid(ClearValidW), .SetDirty(SetDirtyW), .ClearDirty(ClearDirtyW), - .ReadData(ReadDataM[way]), + .ReadData(ReadDataBlockWayM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), .Dirty(Dirty[way])); - assign WayHit = Valid & (ReadTag[way] == MemAdrM); - assign ReadDataMaskedM[way] = Valid[way] ? ReadDataM[way] : '0; // first part of AO mux. + assign WayHit[way] = Valid[way] & (ReadTag[way] == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]); + assign ReadDataBlockWayMaskedM[way] = Valid[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. // the cache block candiate for eviction - assign VictimReadDataMaskedM[way] = VictimWay[way] & ReadDataM[way]; + assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; end endgenerate always_ff @(posedge clk, posedge reset) begin - if (reset) ReplacementBits <= '0; - else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSET-1:OFFSET]] <= NewReplacement; + if (reset) begin + for(int index = 0; index < NUMLINES-1; index++) + ReplacementBits[index] <= '0; + end + else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; end // *** TODO add replacement policy - assign NewReplacement = '0; + genvar index; + generate + for(index = 0; index < NUMLINES-1; index++) + assign NewReplacement[index] = '0; + endgenerate assign VictimWay = 4'b0001; - assign SRAMWriteEnable = SRAMBlockWriteEnableM ? VictimWay : '0; + mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), + .d1(SRAMBlockWriteEnableM ? VictimWay : '0), + .s(SRAMBlockWriteEnableM), + .y(SRAMWayWriteEnable)); + + assign CacheHit = |WayHit; - assign ReadDataSelectWayM = |ReadDataMaskedM; // second part of AO mux. - assign VictimReadDataSelectWayM = | VictimReadDataMaskedM; + // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. + // Need to OR together each way in a bitwise manner. + // Final part of the AO Mux. + always_comb begin + ReadDataBlockM = '0; + VictimReadDataBlockM = '0; + for(int index = 0; index < NUMWAYS; index++) begin + ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM; + VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM; + end + end assign VictimDirty = | VictimDirtyWay; // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. - genvar index; generate for (index = 0; index < WORDSPERLINE; index++) begin - assign ReadDataSelectWayM[index] = ReadDataSelectM[((index+1)*`XLEN)-1: (index*`XLEN)]; + assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate // variable input mux - assign WordReadDataM = ReadDataSelectWayM[MemPAdrM[WORDSPERLINE+$clog2(`XLEN/8) : $clog2(`XLEN/8)]]; + assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; // finally swr - subwordread subwordread(.HRDATA(WordReadDataM), - .HADDRD(MemPAdrM[`XLEN/8-1:0]), - .HSIZED(Funct3M), - .HRDATAMasked(FinalReadDataM)); + // *** BUG fix HSIZED? why was it this way? + subwordread subwordread(.HRDATA(ReadDataWordM), + .HADDRD(MemPAdrM[2:0]), + .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), + .HRDATAMasked(FinalReadDataWordM)); - flopen #(XLEN) ReadDataWReg(.clk(clk), + flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(~StallW), - .d(FinalReadDataM), + .d(FinalReadDataWordM), .q(ReadDataW)); // write path - flopen #(XLEN) WriteDataWReg(.clk(clk), + flopen #(`XLEN) WriteDataWReg(.clk(clk), .en(~StallW), .d(WriteDataM), .q(WriteDataW)); @@ -212,15 +246,15 @@ module dcache .q(Funct3W)); subwordwrite subwordwrite(.HRDATA(ReadDataW), - .HADDRD(MemPAdrM[`XLEN/8-1:0]), - .HSIZED(Funct3W), + .HADDRD(MemPAdrM[2:0]), + .HSIZED({Funct3W[2], 1'b0, Funct3W[1:0]}), .HWDATAIN(WriteDataW), .HWDATA(FinalWriteDataW)); generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W), + amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W[1:0]), .result(AMOResult)); mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); end else @@ -238,19 +272,16 @@ module dcache end endgenerate - flopenr #(LOGWPL+1) - FetchCountReg(.clk(clk), - .reset(reset | CntReset), - .en(CntEn), - .d(NextFetchCount), - .q(FetchCount)); - - assign NextFetchCount = FetchCount + 1'b1; - - assign AHBPAdr = (FetchCount << (`XLEN/8)) + MemPAdrM; - // remove later - assign AHBSize = 3'b000; - + // *** Coding style. this is just awful. The purpose is to align FetchCount to the + // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. + generate + if (`XLEN == 32) begin + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + MemPAdrM; + end else begin + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + MemPAdrM; + end + endgenerate + // mux between the CPU's write and the cache fetch. generate @@ -315,7 +346,7 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign FetchCountFlag = (FetchCount == FetchCountThreshold); + assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) FetchCountReg(.clk(clk), @@ -331,8 +362,8 @@ module dcache flopr #(1+4+2) SRAMWritePipeReg(.clk(clk), .reset(reset), - .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDiryM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDiryM, ClearDirtyM, AtomicW})); + .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), + .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDirtyM, ClearDirtyM, AtomicW})); // fsm state regs @@ -347,7 +378,7 @@ module dcache // next state logic and some state ouputs. always_comb begin DCacheStall = 1'b0; - SelAdrM = 2'b00; + SelAdrM = 1'b0; PreCntEn = 1'b0; SetValidM = 1'b0; ClearValidM = 1'b0; @@ -360,12 +391,13 @@ module dcache CntReset = 1'b0; AHBRead = 1'b0; AHBWrite = 1'b0; - + SelAMOWrite = 1'b0; + case (CurrState) STATE_READY: begin // sram busy if (AnyCPUReqM & SRAMWordWriteEnableW) begin - NextState = STATE_BUSY; + NextState = STATE_SRAM_BUSY; DCacheStall = 1'b1; end // TLB Miss @@ -373,7 +405,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & ~UncachedM & ~FSMReg & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; end @@ -423,7 +455,7 @@ module dcache STATE_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; - if(VictimDirt) begin + if(VictimDirty) begin NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; end else begin NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; @@ -445,7 +477,7 @@ module dcache STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; - AdrSel = 2'b01; + SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_PTW_MISS_FETCH_DONE; end else begin diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index fda8f693d..302b50756 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -35,53 +35,51 @@ package ahbliteState; endpackage module ahblite ( - input logic clk, reset, - input logic StallW, FlushW, + input logic clk, reset, + input logic StallW, // Load control - input logic UnsignedLoadM, - input logic [1:0] AtomicMaskedM, - input logic [6:0] Funct7M, + input logic UnsignedLoadM, + input logic [1:0] AtomicMaskedM, + input logic [6:0] Funct7M, // Signals from Instruction Cache - input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram - input logic InstrReadF, - output logic [`XLEN-1:0] InstrRData, - output logic InstrAckF, + input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram + input logic InstrReadF, + output logic [`XLEN-1:0] InstrRData, + output logic InstrAckF, // Signals from Data Cache - input logic [`PA_BITS-1:0] MemPAdrM, - input logic MemReadM, MemWriteM, - input logic [`XLEN-1:0] WriteDataM, - input logic [1:0] MemSizeM, - //output logic DataStall, - // Signals from MMU - // Signals from PMA checker - input logic DSquashBusAccessM, ISquashBusAccessF, - // Signals to PMA checker (metadata of proposed access) + input logic [`PA_BITS-1:0] DCtoAHBPAdrM, + input logic DCtoAHBReadM, + input logic DCtoAHBWriteM, + input logic [`XLEN-1:0] DCtoAHBWriteData, + output logic [`XLEN-1:0] DCfromAHBReadData, + input logic [1:0] MemSizeM, // *** remove + output logic DCfromAHBAck, // Return from bus - output logic [`XLEN-1:0] HRDATAW, + output logic [`XLEN-1:0] HRDATAW, // AHB-Lite external signals - input logic [`AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [31:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, + input logic [`AHBW-1:0] HRDATA, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [31:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, // Delayed signals for writes - output logic [2:0] HADDRD, - output logic [3:0] HSIZED, - output logic HWRITED, + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED, // Stalls - output logic CommitM, MemAckW + output logic CommitM ); logic GrantData; logic [31:0] AccessAddress; logic [2:0] AccessSize, PTESize, ISize; - logic [`AHBW-1:0] HRDATAMasked, ReadDataM, CapturedHRDATAMasked, HRDATANext, WriteData; + logic [`AHBW-1:0] HRDATAMasked, ReadDataM, HRDATANext, CapturedHRDATAMasked, WriteData; logic IReady, DReady; logic CaptureDataM,CapturedDataAvailable; @@ -95,7 +93,7 @@ module ahblite ( // while an instruction read is occuring, the instruction read finishes before // the data access can take place. import ahbliteState::*; - statetype BusState, ProposedNextBusState, NextBusState; + statetype BusState, NextBusState; flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); @@ -109,49 +107,32 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD; - else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions - else if (MemWriteM) ProposedNextBusState = MEMWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD; - else ProposedNextBusState = ATOMICWRITE; - ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - MEMREAD: if (~HREADY) ProposedNextBusState = MEMREAD; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - MEMWRITE: if (~HREADY) ProposedNextBusState = MEMWRITE; - else if (InstrReadF) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; - INSTRREAD: if (~HREADY) ProposedNextBusState = INSTRREAD; - else ProposedNextBusState = IDLE; // if (InstrReadF still high) - default: ProposedNextBusState = IDLE; + IDLE: if (AtomicMaskedM[1]) NextBusState = ATOMICREAD; + else if (DCtoAHBReadM) NextBusState = MEMREAD; // Memory has priority over instructions + else if (DCtoAHBWriteM) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + ATOMICREAD: if (~HREADY) NextBusState = ATOMICREAD; + else NextBusState = ATOMICWRITE; + ATOMICWRITE: if (~HREADY) NextBusState = ATOMICWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMREAD: if (~HREADY) NextBusState = MEMREAD; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; + else NextBusState = IDLE; // if (InstrReadF still high) + default: NextBusState = IDLE; endcase - // Determine access type (important for determining whether to fault) -// (ProposedNextBusState == MMUTRANSLATE); - - // The PMA and PMP checkers can decide to squash the access - // *** this probably needs to be controlled by the caches rather than EBU dh 7/2/11 - assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState; - - // stall signals - // Note that we need to extend both stalls when MMUTRANSLATE goes to idle, - // since translation might not be complete. - // *** Ross Thompson remove this datastall -/* -----\/----- EXCLUDED -----\/----- - assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || - (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE)); - -----/\----- EXCLUDED -----/\----- */ - - // bus outputs - assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) || - (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE); - assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0]; + assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || + (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE); + assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0]; //assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress; assign #1 HADDR = AccessAddress; generate @@ -180,11 +161,11 @@ module ahblite ( //assign MMUReady = (BusState == MMUTRANSLATE && HREADY); assign InstrRData = HRDATA; + assign DCfromAHBReadData = HRDATA; assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE); // *** Bracker 6/5/21: why is this W stage? - assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) || - ((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE)); + assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); //assign MMUReadPTE = HRDATA; // Carefully decide when to update ReadDataW // ReadDataMstored holds the most recent memory read. @@ -208,17 +189,20 @@ module ahblite ( flopr #(`XLEN) ReadDataOldWReg(clk, reset, HRDATANext, HRDATAW); // Extract and sign-extend subwords if necessary - subwordread swr(.*); + subwordread swr(.HRDATA(HRDATA), + .HADDRD(HADDRD), + .HSIZED(HSIZED), + .HRDATAMasked(HRDATAMasked)); // Handle AMO instructions if applicable generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), + amoalu amoalu(.srca(HRDATAW), .srcb(DCtoAHBWriteData), .funct(Funct7M), .width(MemSizeM), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData); + mux2 #(`XLEN) wdmux(DCtoAHBWriteData, AMOResult, AtomicMaskedM[1], WriteData); end else - assign WriteData = WriteDataM; + assign WriteData = DCtoAHBWriteData; endgenerate endmodule diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index f041fce63..1c8e84c82 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -50,7 +50,7 @@ module datapath ( input logic FWriteIntM, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataM, MemAdrM, + output logic [`XLEN-1:0] WriteDataM, MemAdrM, MemAdrE, // Writeback stage signals input logic StallW, FlushW, input logic FWriteIntW, @@ -120,6 +120,7 @@ module datapath ( flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM); assign MemAdrM = ALUResultM; + assign MemAdrE = ALUResultE; flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM); mux2 #(`XLEN) resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 87e21d79f..392378060 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -49,7 +49,7 @@ module ieu ( input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU - output logic [`XLEN-1:0] MemAdrM, WriteDataM, // Address and write data to LSU + output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 51fa0a4af..1afd92add 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -32,12 +32,13 @@ module lsu ( input logic clk, reset, input logic StallM, FlushM, StallW, FlushW, - output logic DCacheStall, + output logic LSUStall, // Memory Stage // connected to cpu (controls) input logic [1:0] MemRWM, input logic [2:0] Funct3M, + input logic [6:0] Funct7M, input logic [1:0] AtomicM, output logic CommittedM, output logic SquashSCW, @@ -45,6 +46,7 @@ module lsu // address and write data input logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] MemAdrE, input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, @@ -60,14 +62,12 @@ module lsu // connect to ahb input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] MemPAdrM, // to ahb - output logic MemReadM, MemWriteM, - output logic [1:0] AtomicMaskedM, - input logic MemAckW, // from ahb - input logic [`XLEN-1:0] HRDATAW, // from ahb - output logic [2:0] SizeFromLSU, - output logic StallWfromLSU, - + output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb + output logic DCtoAHBReadM, + output logic DCtoAHBWriteM, + input logic DCfromAHBAck, // from ahb + input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb + output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb // mmu management @@ -87,14 +87,9 @@ module lsu output logic DTLBHitM, // not connected - // PMA/PMP (inside mmu) signals - input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. - input logic [2:0] HSIZE, HBURST, - input logic HWRITE, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. - output logic DSquashBusAccessM // output logic [5:0] DHSELRegionsM ); @@ -119,6 +114,9 @@ module lsu logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. + + logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache + logic DTLBMissM; logic [`XLEN-1:0] PageTableEntryM; logic [1:0] PageTypeM; @@ -130,27 +128,21 @@ module lsu logic HPTWTranslate; logic HPTWRead; logic [1:0] MemRWMtoDCache; - logic [2:0] SizetoDCache; + logic [2:0] Funct3MtoDCache; logic [1:0] AtomicMtoDCache; logic [`XLEN-1:0] MemAdrMtoDCache; - logic [`XLEN-1:0] WriteDataMtoDCache; + logic [`XLEN-1:0] MemAdrEtoDCache; logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; logic CommittedMfromDCache; logic SquashSCWfromDCache; logic DataMisalignedMfromDCache; logic HPTWReady; - logic LSUStall; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. + logic DCacheStall; - - // for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the - // CPU's read data input ReadDataW. - assign ReadDataWfromDCache = HRDATAW; - - pagetablewalker pagetablewalker( .clk(clk), .reset(reset), @@ -192,32 +184,29 @@ module lsu .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), - .WriteDataM(WriteDataM), // *** Need to remove this. .StallW(StallW), .ReadDataW(ReadDataW), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), - .DCacheStall(DCacheStall), - // LSU + .LSUStall(LSUStall), + // DCACHE .DisableTranslation(DisableTranslation), .MemRWMtoDCache(MemRWMtoDCache), - .SizetoDCache(SizetoDCache), + .Funct3MtoDCache(Funct3MtoDCache), .AtomicMtoDCache(AtomicMtoDCache), .MemAdrMtoDCache(MemAdrMtoDCache), - .WriteDataMtoDCache(WriteDataMtoDCache), // *** ?????????????? .StallWtoDCache(StallWtoDCache), .CommittedMfromDCache(CommittedMfromDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), - .DataStall(LSUStall)); - - + .DCacheStall(DCacheStall)); + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.VirtualAddress(MemAdrMtoDCache), - .Size(SizetoDCache[1:0]), + .Size(Funct3MtoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), @@ -227,10 +216,11 @@ module lsu .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), - .AtomicAccessM(AtomicMaskedM[1]), + //.AtomicAccessM(AtomicMaskedM[1]), + .AtomicAccessM(1'b0), .WriteAccessM(MemRWMtoDCache[0]), .ReadAccessM(MemRWMtoDCache[1]), - .SquashBusAccess(DSquashBusAccessM), + .SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), // .SelRegions(DHSELRegionsM), @@ -242,7 +232,7 @@ module lsu // Determine if an Unaligned access is taking place always_comb - case(SizetoDCache[1:0]) + case(Funct3MtoDCache[1:0]) 2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu 2'b01: DataMisalignedMfromDCache = MemAdrMtoDCache[0]; // lh, sh, lhu 2'b10: DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu @@ -254,6 +244,10 @@ module lsu // Changed DataMisalignedMfromDCache to a larger combination of trap sources // NonBusTrapM is anything that the bus doesn't contribute to producing // By contrast, using TrapM results in circular logic errors +/* -----\/----- EXCLUDED -----\/----- + + // *** BUG for now leave this out. come back later after the d cache is working. July 09, 2021 + assign MemReadM = MemRWMtoDCache[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; assign MemWriteM = MemRWMtoDCache[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ; @@ -292,16 +286,56 @@ module lsu assign SquashSCWfromDCache = 0; end endgenerate + -----/\----- EXCLUDED -----/\----- */ + + + // *** BUG + assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. + + + dcache dcache(.clk(clk), + .reset(reset), + .StallM(StallM), + .StallW(StallW), + .FlushM(FlushM), + .FlushW(FlushW), + .MemRWM(MemRWMtoDCache), + .Funct3M(Funct3MtoDCache), + .Funct7M(Funct7M), + .AtomicM(AtomicMtoDCache), + .MemAdrE(MemAdrEtoDCache), // *** add to arb + .MemPAdrM(MemPAdrM), + .WriteDataM(WriteDataM), + .ReadDataW(ReadDataWfromDCache), + .DCacheStall(DCacheStall), + .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. + .DTLBMissM(DTLBMissM), + .UncachedM(1'b0), // ***connect to PMA + + // AHB connection + .AHBPAdr(DCtoAHBPAdrM), + .AHBRead(DCtoAHBReadM), + .AHBWrite(DCtoAHBWriteM), + .AHBAck(DCfromAHBAck), + .HWDATA(DCtoAHBWriteData), + .HRDATA(DCfromAHBReadData) + ); + +// assign AtomicMaskedM = 2'b00; // *** Remove from AHB + // Data stall //assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2); - assign HPTWReady = (CurrState == STATE_READY); + // BUG *** July 09, 2021 + //assign HPTWReady = (CurrState == STATE_READY); // Ross Thompson April 22, 2021 // for now we need to handle the issue where the data memory interface repeately // requests data from memory rather than issuing a single request. +/* -----\/----- EXCLUDED -----\/----- + // *** BUG will need to modify this so we can handle the ptw. July 09, 2021 flopenl #(.TYPE(statetype)) stateReg(.clk(clk), .load(reset), @@ -331,7 +365,7 @@ module lsu end STATE_FETCH_AMO_1: begin LSUStall = 1'b1; - if (MemAckW) begin + if (DCfromAHBAck) begin NextState = STATE_FETCH_AMO_2; end else begin NextState = STATE_FETCH_AMO_1; @@ -339,9 +373,9 @@ module lsu end STATE_FETCH_AMO_2: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoDCache) begin + if (DCfromAHBAck & ~StallWtoDCache) begin NextState = STATE_FETCH_AMO_2; - end else if (MemAckW & StallWtoDCache) begin + end else if (DCfromAHBAck & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH_AMO_2; @@ -349,9 +383,9 @@ module lsu end STATE_FETCH: begin LSUStall = 1'b1; - if (MemAckW & ~StallWtoDCache) begin + if (DCfromAHBAck & ~StallWtoDCache) begin NextState = STATE_READY; - end else if (MemAckW & StallWtoDCache) begin + end else if (DCfromAHBAck & StallWtoDCache) begin NextState = STATE_STALLED; end else begin NextState = STATE_FETCH; @@ -378,9 +412,9 @@ module lsu end STATE_PTW_FETCH : begin LSUStall = 1'b1; - if (MemAckW & ~DTLBWriteM) begin + if (DCfromAHBAck & ~DTLBWriteM) begin NextState = STATE_PTW_READY; - end else if (MemAckW & DTLBWriteM) begin + end else if (DCfromAHBAck & DTLBWriteM) begin NextState = STATE_READY; end else begin NextState = STATE_PTW_FETCH; @@ -395,11 +429,8 @@ module lsu end endcase end // always_comb + -----/\----- EXCLUDED -----/\----- */ - // *** for now just pass through size - assign SizeFromLSU = SizetoDCache; - assign StallWfromLSU = StallWtoDCache; - endmodule diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 0c7730f15..83ab93be0 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -42,29 +42,27 @@ module lsuArb input logic [2:0] Funct3M, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, - input logic [`XLEN-1:0] WriteDataM, input logic StallW, // to CPU output logic [`XLEN-1:0] ReadDataW, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, - output logic DCacheStall, + output logic LSUStall, // to LSU output logic DisableTranslation, output logic [1:0] MemRWMtoDCache, - output logic [2:0] SizetoDCache, + output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, - output logic [`XLEN-1:0] WriteDataMtoDCache, output logic StallWtoDCache, // from LSU input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, - input logic DataStall + input logic DCacheStall ); @@ -141,11 +139,10 @@ module lsuArb generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw endgenerate - mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, SizetoDCache); + mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache); assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; - assign WriteDataMtoDCache = SelPTW ? `XLEN'b0 : WriteDataM; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // demux the inputs from LSU to walker or cpu's data port. @@ -158,7 +155,7 @@ module lsuArb // *** need to rename DcacheStall and Datastall. // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). - assign HPTWStall = SelPTW ? DataStall : 1'b1; + assign HPTWStall = SelPTW ? DCacheStall : 1'b1; //assign HPTWStallD = SelPTW ? DataStall : 1'b1; /* -----\/----- EXCLUDED -----\/----- assign HPTWStallD = SelPTW ? DataStall : 1'b1; @@ -168,6 +165,6 @@ module lsuArb .q(HPTWStall)); -----/\----- EXCLUDED -----/\----- */ - assign DCacheStall = SelPTW ? 1'b1 : DataStall; // *** this is probably going to change. + assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change. endmodule diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 3b589456f..80a0b32a5 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -128,45 +128,36 @@ module wallypipelinedhart - // bus interface to dmem - logic MemReadM, MemWriteM; - logic [1:0] AtomicMaskedM; + // cpu lsu interface logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrM, WriteDataM; - logic [`PA_BITS-1:0] MemPAdrM; + logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM; logic [`XLEN-1:0] ReadDataW; + logic CommittedM; + + // AHB ifu interface logic [`PA_BITS-1:0] InstrPAdrF; logic [`XLEN-1:0] InstrRData; logic InstrReadF; - logic InstrAckF, MemAckW; - logic CommitM, CommittedM; - + logic InstrAckF; + + // AHB LSU interface + logic [`PA_BITS-1:0] DCtoAHBPAdrM; + logic DCtoAHBReadM; + logic DCtoAHBWriteM; + logic DCfromAHBAck; + logic [`XLEN-1:0] DCfromAHBReadData; + logic [`XLEN-1:0] DCtoAHBWriteData; + + logic CommitM; + logic BPPredWrongE; logic BPPredDirWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; logic BPPredClassNonCFIWrongM; - - logic [`XLEN-1:0] WriteDatatmpM; - logic [4:0] InstrClassM; - - logic [`XLEN-1:0] HRDATAW; - - // IEU vs HPTW arbitration signals to send to LSU - logic [1:0] MemRWMtoLSU; - logic [2:0] SizeToLSU; - logic [1:0] AtomicMtoLSU; - logic [`XLEN-1:0] MemAdrMtoLSU; - logic [`XLEN-1:0] WriteDataMtoLSU; - logic [`XLEN-1:0] ReadDataWFromLSU; - logic CommittedMfromLSU; - logic SquashSCWfromLSU; - logic DataMisalignedMfromLSU; - logic StallWtoLSU; - logic StallWfromLSU; - logic [2:0] SizeFromLSU; logic InstrAccessFaultF; + logic [2:0] DCtoAHBSizeM; @@ -176,43 +167,33 @@ module wallypipelinedhart ieu ieu(.*); // integer execution unit: integer register file, datapath and controller - - // mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM); - - lsu lsu(.clk(clk), .reset(reset), .StallM(StallM), .FlushM(FlushM), .StallW(StallW), .FlushW(FlushW), - // connected to arbiter (reconnect to CPU) + // CPU interface .MemRWM(MemRWM), - .Funct3M(Funct3M), + .Funct3M(Funct3M), + .Funct7M(InstrM[31:25]), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), + .MemAdrE(MemAdrE), .MemAdrM(MemAdrM), .WriteDataM(WriteDataM), .ReadDataW(ReadDataW), // connected to ahb (all stay the same) .CommitM(CommitM), - .MemPAdrM(MemPAdrM), - .MemReadM(MemReadM), - .MemWriteM(MemWriteM), - .AtomicMaskedM(AtomicMaskedM), - .MemAckW(MemAckW), - .HRDATAW(HRDATAW), - .SizeFromLSU(SizeFromLSU), // stays the same - .StallWfromLSU(StallWfromLSU), // stays the same - .DSquashBusAccessM(DSquashBusAccessM), // probalby removed after dcache implemenation? - // currently not connected (but will need to be used for lsu talking to ahb. - .HADDR(HADDR), - .HSIZE(HSIZE), - .HBURST(HBURST), - .HWRITE(HWRITE), + .DCtoAHBPAdrM(DCtoAHBPAdrM), + .DCtoAHBReadM(DCtoAHBReadM), + .DCtoAHBWriteM(DCtoAHBWriteM), + .DCfromAHBAck(DCfromAHBAck), + .DCfromAHBReadData(DCfromAHBReadData), + .DCtoAHBWriteData(DCtoAHBWriteData), // connect to csr or privilege and stay the same. .PrivilegeModeW(PrivilegeModeW), // connects to csr @@ -234,7 +215,6 @@ module wallypipelinedhart .StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege .StoreAccessFaultM(StoreAccessFaultM), // connects to privilege - // connected to hptw. Move to internal. .PCF(PCF), .ITLBMissF(ITLBMissF), .PageTableEntryF(PageTableEntryF), @@ -246,19 +226,34 @@ module wallypipelinedhart .DTLBHitM(DTLBHitM), // not connected remove - .DCacheStall(DCacheStall)) // change to DCacheStall - ; + .LSUStall(DCacheStall)); // change to DCacheStall - ahblite ebu( - //.InstrReadF(1'b0), - //.InstrRData(InstrF), // hook up InstrF later - .ISquashBusAccessF(1'b0), // *** temporary hack to disable PMP instruction fetch checking - .WriteDataM(WriteDataM), - .MemSizeM(SizeFromLSU[1:0]), .UnsignedLoadM(SizeFromLSU[2]), - .Funct7M(InstrM[31:25]), - .HRDATAW(HRDATAW), - .StallW(StallWfromLSU), + generate + if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010; + else assign DCtoAHBSizeM = 3'b011; + endgenerate; + + + ahblite ebu(// IFU connections + .InstrPAdrF(InstrPAdrF), + .InstrReadF(InstrReadF), + .InstrRData(InstrRData), + .InstrAckF(InstrAckF), + // LSU connections + .DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM + .DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM + .DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM + .DCtoAHBWriteData(DCtoAHBWriteData), + .DCfromAHBReadData(DCfromAHBReadData), + .DCfromAHBAck(DCfromAHBAck), + // remove these + .MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed + .UnsignedLoadM(1'b0), + .Funct7M(7'b0), + .HRDATAW(), + .StallW(1'b0), + .AtomicMaskedM(2'b00), .*); From 7e98610651f2d5f2c2803ba00275b19e67f63616 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 15:37:16 -0500 Subject: [PATCH 06/47] Design loads in modelsim, but trap is an X. --- wally-pipelined/src/cache/DCacheMem.sv | 2 +- wally-pipelined/src/cache/dcache.sv | 17 +++++++---------- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index 70668b5d3..326e1be2a 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -89,6 +89,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 end -endmodule; // DCacheMemWay +endmodule // DCacheMemWay diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 65a0fe8bd..3378ec56c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -88,7 +88,7 @@ module dcache logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic CacheHit; logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0]; - logic [NUMREPL_BITS-1:0] NewReplacement [NUMLINES-1:0]; + logic [NUMREPL_BITS-1:0] NewReplacement; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; @@ -184,11 +184,7 @@ module dcache end // *** TODO add replacement policy - genvar index; - generate - for(index = 0; index < NUMLINES-1; index++) - assign NewReplacement[index] = '0; - endgenerate + assign NewReplacement = '0; assign VictimWay = 4'b0001; mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), .d1(SRAMBlockWriteEnableM ? VictimWay : '0), @@ -201,12 +197,13 @@ module dcache // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. + genvar index; always_comb begin ReadDataBlockM = '0; VictimReadDataBlockM = '0; for(int index = 0; index < NUMWAYS; index++) begin - ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM; - VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM; + ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index]; + VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM[index]; end end assign VictimDirty = | VictimDirtyWay; @@ -363,7 +360,7 @@ module dcache SRAMWritePipeReg(.clk(clk), .reset(reset), .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDirtyM, ClearDirtyM, AtomicW})); + .q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW})); // fsm state regs @@ -491,4 +488,4 @@ module dcache assign CntEn = PreCntEn & AHBAck; -endmodule; // dcache +endmodule // dcache From 94b29ec418495f5c0cc3a6489499da2b3668252d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Jul 2021 17:14:54 -0500 Subject: [PATCH 07/47] Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a full cache block or a word write from the CPU. --- wally-pipelined/src/cache/dcache.sv | 66 ++++++++++++++++++++++++++--- wally-pipelined/src/lsu/lsu.sv | 6 +-- 2 files changed, 62 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3378ec56c..237057fc4 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -69,14 +69,12 @@ module dcache localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); - + localparam integer LOGXLENBYTES = $clog2(`XLEN/8); logic SelAdrM; logic [`PA_BITS-1:0] MemPAdrW; logic [INDEXLEN-1:0] SRAMAdr; - logic [NUMWAYS-1:0] WriteEnable; - logic [NUMWAYS-1:0] WriteWordEnable; logic [BLOCKLEN-1:0] SRAMWriteData; logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValidM, ClearValidM, SetValidW, ClearValidW; @@ -95,7 +93,7 @@ module dcache logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [WORDSPERLINE-1:0] SRAMWordEnable [NUMWAYS-1:0]; + logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SelMemWriteDataM, SelMemWriteDataW; logic [2:0] Funct3W; @@ -114,6 +112,7 @@ module dcache logic SelAMOWrite; logic [6:0] Funct7W; logic [INDEXLEN-1:0] AdrMuxOut; + logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -144,6 +143,13 @@ module dcache .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); + + oneHotDecoder #(LOGWPL) + oneHotDecoder(.bin(MemPAdrW[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), + .decoded(MemPAdrDecodedW)); + + + assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; genvar way; @@ -153,9 +159,9 @@ module dcache MemWay(.clk(clk), .reset(reset), .Adr(SRAMAdr), - .WAdr(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .WriteEnable(SRAMWayWriteEnable[way]), - .WriteWordEnable(SRAMWordEnable[way]), + .WriteWordEnable(SRAMWordEnable), .WriteData(SRAMWriteData), .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .SetValid(SetValidW), @@ -424,6 +430,12 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; end + // write miss valid cached + else if(MemRWM[0] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_WRITE_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end // fault else if(|MemRWM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; @@ -468,10 +480,45 @@ module dcache STATE_READ_MISS_READ_WORD: begin DCacheStall = 1'b1; - SelAdrM = 1'b1; + SelAdrM = 1'b0; NextState = STATE_READY; end + STATE_WRITE_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBRead = 1'b1; + if (FetchCountFlag & AHBAck) begin + NextState = STATE_WRITE_MISS_FETCH_DONE; + end else begin + NextState = STATE_WRITE_MISS_FETCH_WDV; + end + end + + STATE_WRITE_MISS_FETCH_DONE: begin + DCacheStall = 1'b1; + if(VictimDirty) begin + NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; + end else begin + NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + end + end + + STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_WRITE_MISS_WRITE_WORD; + SelAdrM = 1'b1; + SetValidM = 1'b1; + end + + STATE_WRITE_MISS_WRITE_WORD: begin + SRAMWordWriteEnableM = 1'b1; + DCacheStall = 1'b0; + NextState = STATE_READY; + SetDirtyM = 1'b1; + end + STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 1'b1; @@ -481,6 +528,11 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end end + + STATE_SRAM_BUSY: begin + DCacheStall = 1'b0; + NextState = STATE_READY; + end default: begin end endcase diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 1afd92add..432645f71 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -258,9 +258,6 @@ module lsu flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM); assign CommittedMfromDCache = preCommittedM | CommitM; - // Determine if address is valid - assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; - assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // Handle atomic load reserved / store conditional generate @@ -288,6 +285,9 @@ module lsu endgenerate -----/\----- EXCLUDED -----/\----- */ + // Determine if address is valid + assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; + assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; // *** BUG assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. From 0a6c86af9486ea891e64c244dc43e7001de14419 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 10:56:25 -0500 Subject: [PATCH 08/47] Write Hits and Write Misses without eviction are working correctly! The next step is to add eviction of dirty lines. --- wally-pipelined/src/cache/DCacheMem.sv | 3 +- wally-pipelined/src/cache/dcache.sv | 122 +++++++++++++++---------- 2 files changed, 74 insertions(+), 51 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index 326e1be2a..ba50f5dd1 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -33,6 +33,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only input logic WriteEnable, input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, + input logic TagWriteEnable, input logic [BLOCKLEN-1:0] WriteData, input logic [TAGLEN-1:0] WriteTag, input logic SetValid, @@ -69,7 +70,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .Addr(Adr), .ReadData(ReadTag), .WriteData(WriteTag), - .WriteEnable(WriteEnable)); + .WriteEnable(TagWriteEnable)); always_ff @(posedge clk, posedge reset) begin diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 237057fc4..b87a378d7 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -59,7 +59,7 @@ module dcache ); localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; + localparam integer NUMLINES = 64; localparam integer NUMWAYS = 4; localparam integer NUMREPL_BITS = 3; @@ -127,7 +127,7 @@ module dcache // data path flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), - .en(~StallW), + .en(1'b1), .d(MemPAdrM), .q(MemPAdrW)); @@ -137,15 +137,18 @@ module dcache .s(SelAdrM), .y(AdrMuxOut)); - + assign SRAMAdr = AdrMuxOut; +/* -----\/----- EXCLUDED -----\/----- + mux2 #(INDEXLEN) SelAdrlMux2(.d0(AdrMuxOut), .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SRAMWordWriteEnableW), .y(SRAMAdr)); + -----/\----- EXCLUDED -----/\----- */ oneHotDecoder #(LOGWPL) - oneHotDecoder(.bin(MemPAdrW[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), + oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedW)); @@ -154,7 +157,7 @@ module dcache genvar way; generate - for(way = 0; way < NUMWAYS; way = way + 1) begin + for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) MemWay(.clk(clk), .reset(reset), @@ -162,12 +165,13 @@ module dcache .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .WriteEnable(SRAMWayWriteEnable[way]), .WriteWordEnable(SRAMWordEnable), + .TagWriteEnable(SRAMBlockWriteEnableM), .WriteData(SRAMWriteData), - .WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]), - .SetValid(SetValidW), - .ClearValid(ClearValidW), - .SetDirty(SetDirtyW), - .ClearDirty(ClearDirtyW), + .WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]), + .SetValid(SetValidM), + .ClearValid(ClearValidM), + .SetDirty(SetDirtyM), + .ClearDirty(ClearDirtyM), .ReadData(ReadDataBlockWayM[way]), .ReadTag(ReadTag[way]), .Valid(Valid[way]), @@ -186,13 +190,13 @@ module dcache for(int index = 0; index < NUMLINES-1; index++) ReplacementBits[index] <= '0; end - else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; + else if (SRAMWriteEnable) ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; end // *** TODO add replacement policy assign NewReplacement = '0; assign VictimWay = 4'b0001; - mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), + mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), .d1(SRAMBlockWriteEnableM ? VictimWay : '0), .s(SRAMBlockWriteEnableM), .y(SRAMWayWriteEnable)); @@ -308,39 +312,41 @@ module dcache logic CntReset; - typedef enum {STATE_READY, - STATE_READ_MISS_FETCH_WDV, - STATE_READ_MISS_FETCH_DONE, - STATE_READ_MISS_CHECK_EVICTED_DIRTY, - STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_READ_MISS_WRITE_CACHE_BLOCK, - STATE_READ_MISS_READ_WORD, - STATE_WRITE_MISS_FETCH_WDV, - STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, - STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_WRITE_MISS_WRITE_CACHE_BLOCK, - STATE_WRITE_MISS_WRITE_WORD, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_CHECK_EVICTED_DIRTY, - STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_AMO_MISS_WRITE_CACHE_BLOCK, - STATE_AMO_MISS_READ_WORD, - STATE_AMO_MISS_UPDATE_WORD, - STATE_AMO_MISS_WRITE_WORD, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_SRAM_BUSY, - STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WDV, - STATE_UNCACHED_DONE} statetype; + typedef enum {STATE_READY, + STATE_READ_MISS_FETCH_WDV, + STATE_READ_MISS_FETCH_DONE, + STATE_READ_MISS_CHECK_EVICTED_DIRTY, + STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_READ_MISS_WRITE_CACHE_BLOCK, + STATE_READ_MISS_READ_WORD, + STATE_WRITE_MISS_FETCH_WDV, + STATE_WRITE_MISS_FETCH_DONE, + STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_WRITE_MISS_WRITE_CACHE_BLOCK, + STATE_WRITE_MISS_READ_WORD, + STATE_WRITE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_SRAM_BUSY, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WDV, + STATE_UNCACHED_DONE, + STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -360,7 +366,7 @@ module dcache assign NextFetchCount = FetchCount + 1'b1; - assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableW; + assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; flopr #(1+4+2) SRAMWritePipeReg(.clk(clk), @@ -419,10 +425,12 @@ module dcache end // write hit valid cached else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin - NextState = STATE_READY; + SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // read miss valid cached else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin @@ -488,6 +496,7 @@ module dcache DCacheStall = 1'b1; PreCntEn = 1'b1; AHBRead = 1'b1; + SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin NextState = STATE_WRITE_MISS_FETCH_DONE; end else begin @@ -497,6 +506,7 @@ module dcache STATE_WRITE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; + SelAdrM = 1'b1; if(VictimDirty) begin NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; end else begin @@ -507,16 +517,23 @@ module dcache STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; - NextState = STATE_WRITE_MISS_WRITE_WORD; + NextState = STATE_WRITE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; end + STATE_WRITE_MISS_READ_WORD: begin + NextState = STATE_WRITE_MISS_WRITE_WORD; + DCacheStall = 1'b1; + SelAdrM = 1'b1; + end + STATE_WRITE_MISS_WRITE_WORD: begin - SRAMWordWriteEnableM = 1'b1; DCacheStall = 1'b0; - NextState = STATE_READY; + SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + NextState = STATE_READY; + SelAdrM = 1'b1; end STATE_PTW_MISS_FETCH_WDV: begin @@ -533,6 +550,11 @@ module dcache DCacheStall = 1'b0; NextState = STATE_READY; end + + STATE_CPU_BUSY : begin + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end default: begin end endcase From ee72178eec68e34671412429d919fe9c24904e97 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 15:17:40 -0500 Subject: [PATCH 09/47] Write miss with eviction works. --- wally-pipelined/src/cache/dcache.sv | 45 ++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b87a378d7..c3c6079c2 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -89,6 +89,7 @@ module dcache logic [NUMREPL_BITS-1:0] NewReplacement; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; + logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; logic [BLOCKLEN-1:0] FinalWriteDataWordsW; @@ -113,8 +114,11 @@ module dcache logic [6:0] Funct7W; logic [INDEXLEN-1:0] AdrMuxOut; logic [2**LOGWPL-1:0] MemPAdrDecodedW; - - + + logic [`PA_BITS-1:0] BasePAdrM; + logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; + logic [TAGLEN-1:0] VictimTag; + flopenr #(7) Funct7WReg(.clk(clk), .reset(reset), @@ -180,8 +184,11 @@ module dcache assign ReadDataBlockWayMaskedM[way] = Valid[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. // the cache block candiate for eviction + // *** this should be sharable with the read data muxing, but for now i'm doing the simple + // thing and makign them separate. assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; + assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0; end endgenerate @@ -211,24 +218,30 @@ module dcache always_comb begin ReadDataBlockM = '0; VictimReadDataBlockM = '0; + VictimTag = '0; for(int index = 0; index < NUMWAYS; index++) begin ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index]; VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM[index]; + VictimTag = VictimTag | VictimTagWay[index]; end end assign VictimDirty = | VictimDirtyWay; - + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can // easily build a variable input mux. generate for (index = 0; index < WORDSPERLINE; index++) begin assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; + assign VictimReadDataBlockSetsM[index] = VictimReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate // variable input mux assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; + + assign HWDATA = VictimReadDataBlockSetsM[FetchCount]; + // finally swr // *** BUG fix HSIZED? why was it this way? subwordread subwordread(.HRDATA(ReadDataWordM), @@ -281,11 +294,17 @@ module dcache // *** Coding style. this is just awful. The purpose is to align FetchCount to the // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. + + mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), + .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .s(AHBWrite), + .y(BasePAdrM)); + generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + MemPAdrM; + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrM; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + MemPAdrM; + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrM; end endgenerate @@ -321,7 +340,7 @@ module dcache STATE_READ_MISS_READ_WORD, STATE_WRITE_MISS_FETCH_WDV, STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_CHECK_EVICTED_DIRTY, + STATE_WRITE_MISS_EVICT_DIRTY, STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_WRITE_MISS_WRITE_CACHE_BLOCK, STATE_WRITE_MISS_READ_WORD, @@ -507,8 +526,9 @@ module dcache STATE_WRITE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; + CntReset = 1'b1; if(VictimDirty) begin - NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY; + NextState = STATE_WRITE_MISS_EVICT_DIRTY; end else begin NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; end @@ -536,6 +556,17 @@ module dcache SelAdrM = 1'b1; end + STATE_WRITE_MISS_EVICT_DIRTY: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBWrite = 1'b1; + if( FetchCountFlag & AHBAck) begin + NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + end else begin + NextState = STATE_WRITE_MISS_EVICT_DIRTY; + end + end + STATE_PTW_MISS_FETCH_WDV: begin DCacheStall = 1'b1; SelAdrM = 1'b1; From a82c4c99c2d8e07df02b60cab3c0dd366982cd40 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 17:48:47 -0500 Subject: [PATCH 10/47] Actually writes the correct data now on stores. --- wally-pipelined/regression/wave.do | 220 +++++++++++++++++----------- wally-pipelined/src/cache/dcache.sv | 64 +++----- 2 files changed, 152 insertions(+), 132 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 946e2d283..501f71e41 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -20,14 +20,14 @@ add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPa add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -105,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -213,13 +213,8 @@ add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState -add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState -add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM -add wave -noupdate -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK @@ -240,19 +235,77 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HRDATAW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/StallW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW +add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW +add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -280,45 +333,40 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUTranslate -add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/MMUReadPTE -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -divider data -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE -add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/lsu/arbiter/MemAdrMtoLSU +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -divider data +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -343,17 +391,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/PCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {16658 ns} 1} {{Cursor 4} {16655 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0} +quietly wave cursor active 6 configure wave -namecolwidth 250 -configure wave -valuecolwidth 189 +configure wave -valuecolwidth 273 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -366,4 +412,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {16565 ns} {16719 ns} +WaveRestoreZoom {57593 ns} {57969 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index c3c6079c2..41138d15b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -73,12 +73,11 @@ module dcache logic SelAdrM; - logic [`PA_BITS-1:0] MemPAdrW; logic [INDEXLEN-1:0] SRAMAdr; logic [BLOCKLEN-1:0] SRAMWriteData; logic [BLOCKLEN-1:0] DCacheMemWriteData; - logic SetValidM, ClearValidM, SetValidW, ClearValidW; - logic SetDirtyM, ClearDirtyM, SetDirtyW, ClearDirtyW; + logic SetValidM, ClearValidM; + logic SetDirtyM, ClearDirtyM; logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0]; logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; logic [BLOCKLEN-1:0] VictimReadDataBLockWayMaskedM [NUMWAYS-1:0]; @@ -91,11 +90,11 @@ module dcache logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; - logic [`XLEN-1:0] WriteDataW, FinalWriteDataW, FinalAMOWriteDataW; - logic [BLOCKLEN-1:0] FinalWriteDataWordsW; + logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; + logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [LOGWPL:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SelMemWriteDataM, SelMemWriteDataW; + logic SelMemWriteDataM; logic [2:0] Funct3W; logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; @@ -112,7 +111,6 @@ module dcache logic VictimDirty; logic SelAMOWrite; logic [6:0] Funct7W; - logic [INDEXLEN-1:0] AdrMuxOut; logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; @@ -130,26 +128,12 @@ module dcache // data path - flopen #(`PA_BITS) MemPAdrWReg(.clk(clk), - .en(1'b1), - .d(MemPAdrM), - .q(MemPAdrW)); - mux2 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .s(SelAdrM), - .y(AdrMuxOut)); + .y(SRAMAdr)); - assign SRAMAdr = AdrMuxOut; -/* -----\/----- EXCLUDED -----\/----- - - mux2 #(INDEXLEN) - SelAdrlMux2(.d0(AdrMuxOut), - .d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .s(SRAMWordWriteEnableW), - .y(SRAMAdr)); - -----/\----- EXCLUDED -----/\----- */ oneHotDecoder #(LOGWPL) oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), @@ -185,7 +169,7 @@ module dcache // the cache block candiate for eviction // *** this should be sharable with the read data muxing, but for now i'm doing the simple - // thing and makign them separate. + // thing and making them separate. assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0; assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0; @@ -255,30 +239,20 @@ module dcache .q(ReadDataW)); // write path - flopen #(`XLEN) WriteDataWReg(.clk(clk), - .en(~StallW), - .d(WriteDataM), - .q(WriteDataW)); - - flopr #(3) Funct3WReg(.clk(clk), - .reset(reset), - .d(Funct3M), - .q(Funct3W)); - - subwordwrite subwordwrite(.HRDATA(ReadDataW), + subwordwrite subwordwrite(.HRDATA(FinalReadDataWordM), .HADDRD(MemPAdrM[2:0]), - .HSIZED({Funct3W[2], 1'b0, Funct3W[1:0]}), - .HWDATAIN(WriteDataW), - .HWDATA(FinalWriteDataW)); + .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), + .HWDATAIN(WriteDataM), + .HWDATA(FinalWriteDataM)); generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; - amoalu amoalu(.srca(ReadDataW), .srcb(WriteDataW), .funct(Funct7W), .width(Funct3W[1:0]), + amoalu amoalu(.srca(FinalReadDataWordM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(FinalWriteDataW, AMOResult, SelAMOWrite & AtomicW[1], FinalAMOWriteDataW); + mux2 #(`XLEN) wdmux(FinalWriteDataM, AMOResult, SelAMOWrite & AtomicM[1], FinalAMOWriteDataM); end else - assign FinalAMOWriteDataW = FinalWriteDataW; + assign FinalAMOWriteDataM = FinalWriteDataM; endgenerate @@ -312,11 +286,11 @@ module dcache // mux between the CPU's write and the cache fetch. generate for(index = 0; index < WORDSPERLINE; index++) begin - assign FinalWriteDataWordsW[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataW; + assign FinalWriteDataWordsM[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalAMOWriteDataM; end endgenerate - mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsW), + mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsM), .d1(DCacheMemWriteData), .s(SRAMBlockWriteEnableM), .y(SRAMWriteData)); @@ -387,11 +361,11 @@ module dcache assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; - flopr #(1+4+2) + flopr #(1) SRAMWritePipeReg(.clk(clk), .reset(reset), - .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), - .q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW})); + .d({SRAMWordWriteEnableM}), + .q({SRAMWordWriteEnableW})); // fsm state regs From d9fa3af94d999ee1e26ac62497c51bbd6b6270ea Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 22:15:44 -0500 Subject: [PATCH 11/47] Loads are working. There is a bug when the icache stalls 1 cycle before the d cache. --- wally-pipelined/src/cache/dcache.sv | 101 ++++++++++------------------ 1 file changed, 37 insertions(+), 64 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 41138d15b..9b2365966 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -312,13 +312,14 @@ module dcache STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_READ_MISS_WRITE_CACHE_BLOCK, STATE_READ_MISS_READ_WORD, - STATE_WRITE_MISS_FETCH_WDV, - STATE_WRITE_MISS_FETCH_DONE, - STATE_WRITE_MISS_EVICT_DIRTY, - STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_WRITE_MISS_WRITE_CACHE_BLOCK, - STATE_WRITE_MISS_READ_WORD, - STATE_WRITE_MISS_WRITE_WORD, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_MISS_WRITE_CACHE_BLOCK, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, STATE_AMO_MISS_FETCH_WDV, STATE_AMO_MISS_FETCH_DONE, STATE_AMO_MISS_CHECK_EVICTED_DIRTY, @@ -425,15 +426,9 @@ module dcache if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end - // read miss valid cached - else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_READ_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - end - // write miss valid cached - else if(MemRWM[0] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_WRITE_MISS_FETCH_WDV; + // read or write miss valid cached + else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end @@ -452,77 +447,55 @@ module dcache SelAMOWrite = 1'b1; end - STATE_READ_MISS_FETCH_WDV: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; - if (FetchCountFlag & AHBAck) begin - NextState = STATE_READ_MISS_FETCH_DONE; - end else begin - NextState = STATE_READ_MISS_FETCH_WDV; - end - end - - STATE_READ_MISS_FETCH_DONE: begin - DCacheStall = 1'b1; - if(VictimDirty) begin - NextState = STATE_READ_MISS_CHECK_EVICTED_DIRTY; - end else begin - NextState = STATE_READ_MISS_WRITE_CACHE_BLOCK; - end - end - - STATE_READ_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_READ_MISS_READ_WORD; - SelAdrM = 1'b1; - end - - STATE_READ_MISS_READ_WORD: begin - DCacheStall = 1'b1; - SelAdrM = 1'b0; - NextState = STATE_READY; - end - - STATE_WRITE_MISS_FETCH_WDV: begin + STATE_MISS_FETCH_WDV: begin DCacheStall = 1'b1; PreCntEn = 1'b1; AHBRead = 1'b1; SelAdrM = 1'b1; if (FetchCountFlag & AHBAck) begin - NextState = STATE_WRITE_MISS_FETCH_DONE; + NextState = STATE_MISS_FETCH_DONE; end else begin - NextState = STATE_WRITE_MISS_FETCH_WDV; + NextState = STATE_MISS_FETCH_WDV; end end - STATE_WRITE_MISS_FETCH_DONE: begin + STATE_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; CntReset = 1'b1; if(VictimDirty) begin - NextState = STATE_WRITE_MISS_EVICT_DIRTY; + NextState = STATE_MISS_EVICT_DIRTY; end else begin - NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_BLOCK; end end - STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin + STATE_MISS_WRITE_CACHE_BLOCK: begin SRAMBlockWriteEnableM = 1'b1; DCacheStall = 1'b1; - NextState = STATE_WRITE_MISS_READ_WORD; + NextState = STATE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; end - STATE_WRITE_MISS_READ_WORD: begin - NextState = STATE_WRITE_MISS_WRITE_WORD; - DCacheStall = 1'b1; + STATE_MISS_READ_WORD: begin SelAdrM = 1'b1; + DCacheStall = 1'b1; + if (MemRWM[1]) begin + NextState = STATE_MISS_READ_WORD_DELAY; + // delay state is required as the read signal MemRWM[1] is still high when we + // return to the ready state because the cache is stalling the cpu. + end else begin + NextState = STATE_MISS_WRITE_WORD; + end end - STATE_WRITE_MISS_WRITE_WORD: begin + STATE_MISS_READ_WORD_DELAY: begin + SelAdrM = 1'b1; + NextState = STATE_READY; + end + + STATE_MISS_WRITE_WORD: begin DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; @@ -530,14 +503,14 @@ module dcache SelAdrM = 1'b1; end - STATE_WRITE_MISS_EVICT_DIRTY: begin + STATE_MISS_EVICT_DIRTY: begin DCacheStall = 1'b1; PreCntEn = 1'b1; AHBWrite = 1'b1; if( FetchCountFlag & AHBAck) begin - NextState = STATE_WRITE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin - NextState = STATE_WRITE_MISS_EVICT_DIRTY; + NextState = STATE_MISS_EVICT_DIRTY; end end From 282bde72055741d4e407b3f74a1b0f3d79b3b5dc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 10 Jul 2021 22:34:47 -0500 Subject: [PATCH 12/47] Fixed the spurious AHB requests to address 0. Somehow by not having a default (else) in the fsm branch selection for STATE_READY in the d cache it was possible to take an invalid branch through the fsm. --- wally-pipelined/src/cache/dcache.sv | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9b2365966..2b199609c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -370,6 +370,7 @@ module dcache // fsm state regs +/* -----\/----- EXCLUDED -----\/----- flopenl #(.TYPE(statetype)) FSMReg(.clk(clk), .load(reset), @@ -377,6 +378,12 @@ module dcache .val(STATE_READY), .d(NextState), .q(CurrState)); + -----/\----- EXCLUDED -----/\----- */ + + always_ff @(posedge clk, posedge reset) + if (reset) CurrState <= #1 STATE_READY; + else CurrState <= #1 NextState; + // next state logic and some state ouputs. always_comb begin @@ -436,7 +443,9 @@ module dcache else if(|MemRWM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; end + else NextState = STATE_READY; end + STATE_AMO_UPDATE: begin NextState = STATE_AMO_WRITE; SaveSRAMRead = 1'b1; From 8ca8b9075d680e10b7b326165ff589fb9e12ff8a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jul 2021 14:22:13 -0500 Subject: [PATCH 13/47] Progress towards the test bench flush. --- wally-pipelined/regression/wave.do | 97 ++++--- wally-pipelined/src/cache/DCacheMem.sv | 2 +- .../testbench/testbench-imperas.sv | 242 +++++++++++++++++- 3 files changed, 278 insertions(+), 63 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 501f71e41..68705908d 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -250,25 +250,25 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM @@ -280,7 +280,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall @@ -295,8 +294,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -396,8 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0} -quietly wave cursor active 6 +WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 273 configure wave -justifyvalue left @@ -412,4 +409,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {57593 ns} {57969 ns} +WaveRestoreZoom {57704 ns} {58248 ns} diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index ba50f5dd1..17591abe3 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -53,7 +53,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 genvar words; generate - for(words = 0; words < BLOCKLEN/`XLEN; words++) begin + for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES)) CacheDataMem(.clk(clk), diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index a4daf7f31..cec962f5e 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -44,14 +44,14 @@ module testbench(); logic [31:0] InstrW; logic [`XLEN-1:0] meminit; - //string tests32mmu[] = '{ - //"rv32mmu/WALLY-MMU-SV32", "3000" - // }; + string tests32mmu[] = '{ + "rv32mmu/WALLY-MMU-SV32", "3000" + }; - //string tests64mmu[] = '{ - //"rv64mmu/WALLY-MMU-SV48", "3000", - //"rv64mmu/WALLY-MMU-SV39", "3000" - //}; + string tests64mmu[] = '{ + "rv64mmu/WALLY-MMU-SV48", "3000", + "rv64mmu/WALLY-MMU-SV39", "3000" + }; string tests32f[] = '{ @@ -216,6 +216,7 @@ string tests32f[] = '{ string tests64i[] = '{ //"rv64i/WALLY-PIPELINE-100K", "f7ff0", + //"rv64i/WALLY-LOAD", "11bf0", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -286,7 +287,7 @@ string tests32f[] = '{ "rv64i/WALLY-SLLI", "3000", "rv64i/WALLY-SRLI", "3000", "rv64i/WALLY-SRAI", "3000", - "rv64i/WALLY-LOAD", "11bf0", + "rv64i/WALLY-JAL", "4000", "rv64i/WALLY-JALR", "3000", "rv64i/WALLY-STORE", "3000", @@ -513,6 +514,9 @@ string tests32f[] = '{ logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + logic DCacheFlushDone, DCacheFlushStart; + + logic [`XLEN-1:0] debug; assign debug = dut.uncore.dtim.RAM[536872960]; @@ -540,9 +544,10 @@ string tests32f[] = '{ else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; if (`A_SUPPORTED) tests = {tests, tests64a}; - //if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; + if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + tests = {tests64i, tests}; end //tests = {tests64a, tests}; end else begin // RV32 @@ -625,9 +630,9 @@ string tests32f[] = '{ // check results always @(negedge clk) begin - if (dut.hart.priv.EcallFaultM && - (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin + if (DCacheFlushDone) begin $display("Code ended with ecall with gp = 1"); + #60; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests for(i=0; i Date: Mon, 12 Jul 2021 15:13:27 -0500 Subject: [PATCH 14/47] Now updates the dtim with the dirty data in the dcache. Simulation is showing issues. It lookslike the cache is not evicting the correct data. --- .../testbench/testbench-imperas.sv | 46 +++++++++++-------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index cec962f5e..061e5a6c7 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -1022,12 +1022,35 @@ module DCacheFlushFSM else CurrState = NextState; end + integer adr; + integer tag; + integer index; + integer way; + integer word; + logic dirty, valid; + logic [`XLEN-1:0] data; + always_comb begin case (CurrState) IDLE: if(start) NextState = READ; else NextState = IDLE; READ: begin force testbench.dut.hart.lsu.dcache.SRAMAdr = count; + index = count / numways; + way = count % numways; + tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; + dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; + valid = testbench.dut.hart.lsu.dcache.Valid[way]; + adr = (tag << tagstart) + (index << logblockbytelen); + data = testbench.dut.hart.lsu.dcache.FinalReadDataWordM; + if (valid & dirty) begin + $display("Index Way Tag V D %03x %d %016x %d %d %016x %016x", index, way, tag, valid, dirty, adr, data); + force dut.uncore.dtim.A = adr; + force dut.uncore.dtim.HWDATA = data; + force dut.uncore.dtim.memwrite = 1; + force dut.uncore.dtim.risingHREADYTim = 1; + end + if(CountFlag) begin NextState = DONE; end else begin @@ -1036,6 +1059,10 @@ module DCacheFlushFSM end DONE: begin release testbench.dut.hart.lsu.dcache.SRAMAdr; + release dut.uncore.dtim.A; + release dut.uncore.dtim.HWDATA; + release dut.uncore.dtim.memwrite; + release dut.uncore.dtim.risingHREADYTim; NextState = DONE; end default: NextState = IDLE; @@ -1046,26 +1073,7 @@ module DCacheFlushFSM assign CntEn = CurrState == READ; - integer adr; - integer tag; - integer index; - integer way; - integer word; - - logic dirty, valid; - always_comb begin - if (CurrState == READ) begin - assign index = count / numways; - assign way = count % numways; - assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - assign valid = testbench.dut.hart.lsu.dcache.Valid[way]; - assign adr = tag << (tagstart) + index; - - $display("Index Way Tag V D %03x %d %016x %d %d %016x", index, way, tag, valid, dirty, adr); - end - end endmodule From 9fe6190763fa45ec93d7f6cb68b10abc4cf61a00 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jul 2021 23:46:32 -0500 Subject: [PATCH 15/47] Team work on solving the dcache data inconsistency problem. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- wally-pipelined/regression/wave.do | 153 ++++++++++-------- wally-pipelined/src/cache/dcache.sv | 1 + .../testbench/testbench-imperas.sv | 143 +++++++--------- 4 files changed, 146 insertions(+), 153 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 44a90e1c2..745196890 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF +`define TIM_RANGE 56'h0007FFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 68705908d..b2b477ba9 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu -divider internals +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -258,31 +258,29 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -392,11 +390,34 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436996]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436997]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436998]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436999]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437000]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437011]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437012]} +add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437268]} +add wave -noupdate /testbench/dut/uncore/dtim/RAM +add wave -noupdate /testbench/dut/uncore/dtim/A +add wave -noupdate /testbench/dut/uncore/dtim/HWDATA +add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/memread +add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate /testbench/dut/uncore/dtim/HCLK +add wave -noupdate /testbench/dut/hart/clk +add wave -noupdate /testbench/DCacheFlushFSM/CacheData +add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM +add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr +add wave -noupdate /testbench/DCacheFlushFSM/CacheData +add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty +add wave -noupdate /testbench/DCacheFlushFSM/CacheTag +add wave -noupdate /testbench/DCacheFlushFSM/CacheValid TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0} +WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 -configure wave -valuecolwidth 273 +configure wave -valuecolwidth 297 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -409,4 +430,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {57704 ns} {58248 ns} +WaveRestoreZoom {0 ns} {67394 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 2b199609c..a5443417b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -516,6 +516,7 @@ module dcache DCacheStall = 1'b1; PreCntEn = 1'b1; AHBWrite = 1'b1; + SelAdrM = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 061e5a6c7..b9b145581 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -630,10 +630,14 @@ string tests32f[] = '{ // check results always @(negedge clk) begin - if (DCacheFlushDone) begin + if (dut.hart.priv.EcallFaultM && + (dut.hart.ieu.dp.regf.rf[3] == 1 || + (dut.hart.ieu.dp.regf.we3 && + dut.hart.ieu.dp.regf.a3 == 3 && + dut.hart.ieu.dp.regf.wd3 == 1))) begin $display("Code ended with ecall with gp = 1"); - #60; // give time for instructions in pipeline to finish + #600; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests for(i=0; i>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)]; - logic [lognumways + lognumlines - 1 : 0] count, countNext; - - flopenr #(lognumlines + lognumways) - FetchCountReg(.clk(clk), - .reset(reset), - .en(CntEn), - .d(countNext), - .q(count)); - - assign countNext = count + 1; - assign CountFlag = count == '1; - - always_ff @(posedge clk, posedge reset) begin - if(reset) CurrState = IDLE; - else CurrState = NextState; - end - - integer adr; - integer tag; - integer index; - integer way; - integer word; - logic dirty, valid; - logic [`XLEN-1:0] data; - - always_comb begin - case (CurrState) - IDLE: if(start) NextState = READ; - else NextState = IDLE; - READ: begin - force testbench.dut.hart.lsu.dcache.SRAMAdr = count; - index = count / numways; - way = count % numways; - tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - valid = testbench.dut.hart.lsu.dcache.Valid[way]; - adr = (tag << tagstart) + (index << logblockbytelen); - data = testbench.dut.hart.lsu.dcache.FinalReadDataWordM; - if (valid & dirty) begin - $display("Index Way Tag V D %03x %d %016x %d %d %016x %016x", index, way, tag, valid, dirty, adr, data); - force dut.uncore.dtim.A = adr; - force dut.uncore.dtim.HWDATA = data; - force dut.uncore.dtim.memwrite = 1; - force dut.uncore.dtim.risingHREADYTim = 1; - end - - if(CountFlag) begin - NextState = DONE; - end else begin - NextState = READ; + generate + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + assign CacheTag[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]; + assign CacheValid[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]; + assign CacheDirty[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]; + for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin + assign CacheData[way][index][cacheWord] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]; + assign CacheAdr[way][index][cacheWord] = ((CacheTag[way][index] << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8))); end end - DONE: begin - release testbench.dut.hart.lsu.dcache.SRAMAdr; - release dut.uncore.dtim.A; - release dut.uncore.dtim.HWDATA; - release dut.uncore.dtim.memwrite; - release dut.uncore.dtim.risingHREADYTim; - NextState = DONE; - end - default: NextState = IDLE; - endcase - end - - assign done = CurrState == DONE; - assign CntEn = CurrState == READ; + end + endgenerate + integer i, j, k; - + always @(posedge clk) begin + if (start) begin #1 + for(i = 0; i < numlines; i++) begin + for(j = 0; j < numways; j++) begin + for(k = 0; k < numwords; k++) begin + $display("Help me!") + ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k]; + end + end + end + end + end + + endmodule @@ -1167,20 +1138,20 @@ task FlushDCache; logic [`XLEN-1:0] CacheData; assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0]; - - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(word = 0; word < numwords; word++) begin - assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index]; - - path = $sformatf(GenericCacheDataMem, way, word, index); - // I guess you cannot do this conversion. - //assign CacheData = path; - $display("%x", path); - $display(CacheData); + + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + for(word = 0; word < numwords; word++) begin + assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index]; + + path = $sformatf(GenericCacheDataMem, way, word, index); + // I guess you cannot do this conversion. + //assign CacheData = path; + $display("%x", path); + $display(CacheData); + end end end - end $display("%x", value); From 17dc488010ab494bcaf6784685d228db7ac3d946 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 10:03:47 -0500 Subject: [PATCH 16/47] Got the shadow ram cache flush working. --- wally-pipelined/regression/wave.do | 9 ++++++--- .../testbench/testbench-imperas.sv | 19 +++++++++++++------ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index b2b477ba9..753e51958 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -402,19 +402,22 @@ add wave -noupdate /testbench/dut/uncore/dtim/RAM add wave -noupdate /testbench/dut/uncore/dtim/A add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memread add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate /testbench/dut/uncore/dtim/HCLK add wave -noupdate /testbench/dut/hart/clk add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr add wave -noupdate /testbench/DCacheFlushFSM/CacheData add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty add wave -noupdate /testbench/DCacheFlushFSM/CacheTag add wave -noupdate /testbench/DCacheFlushFSM/CacheValid +add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk +add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start +add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} +WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -430,4 +433,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {67394 ns} +WaveRestoreZoom {63529 ns} {63661 ns} diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b9b145581..fa43c560a 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -630,11 +630,14 @@ string tests32f[] = '{ // check results always @(negedge clk) begin +/* -----\/----- EXCLUDED -----\/----- if (dut.hart.priv.EcallFaultM && (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin + -----/\----- EXCLUDED -----/\----- */ + if (DCacheFlushDone) begin $display("Code ended with ecall with gp = 1"); #600; // give time for instructions in pipeline to finish @@ -1035,16 +1038,20 @@ module DCacheFlushFSM if (start) begin #1 for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - $display("Help me!") - ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k]; - end + if (CacheValid[j][i] && CacheDirty[j][i]) begin + for(k = 0; k < numwords; k++) begin + ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k]; + end + end end end end end - - + + + flop #(1) doneReg(.clk(clk), + .d(start), + .q(done)); endmodule From d3ffbe0e5d265e6ff723a7f1439156f1eb3202a5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 10:55:57 -0500 Subject: [PATCH 17/47] Modularized the shadow memory to reduce performance hit. --- .../testbench/testbench-imperas.sv | 161 +++++------------- 1 file changed, 44 insertions(+), 117 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index fa43c560a..25cb1ef62 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -1009,10 +1009,9 @@ module DCacheFlushFSM genvar index, way, cacheWord; logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0]; - + logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; + logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; + logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; genvar adr; @@ -1021,26 +1020,37 @@ module DCacheFlushFSM generate for(index = 0; index < numlines; index++) begin for(way = 0; way < numways; way++) begin - assign CacheTag[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]; - assign CacheValid[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]; - assign CacheDirty[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]; for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - assign CacheData[way][index][cacheWord] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]; - assign CacheAdr[way][index][cacheWord] = ((CacheTag[way][index] << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8))); + copyShadow #(.tagstart(tagstart)) + copyShadow(.clk, + .start, + .tag(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]), + .valid(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]), + .dirty(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]), + .data(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]), + .Adr(((testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index] << tagstart) + + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)))), + .CacheData(CacheData[way][index][cacheWord]), + .CacheAdr(CacheAdr[way][index][cacheWord]), + .CacheTag(CacheTag[way][index][cacheWord]), + .CacheValid(CacheValid[way][index][cacheWord]), + .CacheDirty(CacheDirty[way][index][cacheWord])); end end end endgenerate + integer i, j, k; always @(posedge clk) begin if (start) begin #1 + #1 for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin - if (CacheValid[j][i] && CacheDirty[j][i]) begin - for(k = 0; k < numwords; k++) begin - ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k]; + for(k = 0; k < numwords; k++) begin + if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin + ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; end end end @@ -1054,114 +1064,31 @@ module DCacheFlushFSM .q(done)); endmodule - -task FlushDCache; - // takes no inputs or ouptuts but controls logics in the d cache. - - // two possible implementations. - // 1) Can directly read/set the cache SRAM and the dtim. - // The problem here is the structure of the cache is - // not really easily known. - // 2) Use the cache's interface to read out blocks. - // The problem is we must do this over clock cycles. - // Honestly not sure which is easier. - // I don't think method 1 is possible because verilog cannot convert a string into - // an object's hierarchy or it is not possible because verilog cannot use - // variable index inside a generate block. - - // path to d cache parameterization - //sim:/testbench/dut/hart/lsu/dcache/NUMLINES - //sim:/testbench/dut/hart/lsu/dcache/NUMWAYS - //sim:/testbench/dut/hart/lsu/dcache/BLOCKBYTELEN - - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits - //sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits - - static string GenericCacheDataMem = "testbench.dut.hart.lsu.dcache.CacheWays[%0d].MemWay.word[%0d].CacheDataMem.StoredData[%0d]"; - static string GenericCacheTagMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.CacheTagMem.StoredData[%d]"; - static string GenericCacheValidMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.ValidBits[%d]"; - static string GenericCacheDirtyMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.DirtyBits[%d]"; - +module copyShadow + #(parameter tagstart) + (input logic clk, + input logic start, + input logic [`PA_BITS-1:tagstart] tag, + input logic valid, dirty, + input logic [`XLEN-1:0] data, + input logic [`PA_BITS-1:tagstart] Adr, + output logic [`XLEN-1:0] CacheData, + output logic [`PA_BITS-1:0] CacheAdr, + output logic [`XLEN-1:0] CacheTag, + output logic CacheValid, + output logic CacheDirty); - const integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES; - const integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS; - const integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN; - const integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN; - const integer lognumlines = $clog2(numlines); - const integer logblockbytelen = $clog2(blockbytelen); - const integer tagstart = lognumlines + logblockbytelen; - - - - // drive SRAMAdr - //sim:/testbench/dut/hart/lsu/dcache/SRAMAdr - // Read ReadTag and then mux out on the NUMWAYS - //sim:/testbench/dut/hart/lsu/dcache/ReadTag - //sim:/testbench/dut/hart/lsu/dcache/Valid - //sim:/testbench/dut/hart/lsu/dcache/Dirty - - // if Valid and Dirty we write to dtim - - logic [`PA_BITS-1:0] FullAdr; - - integer adr; - integer tag; - integer index; - integer way; - integer word; - - logic dirty, valid; - - logic [`XLEN-1:0] value; - - - - -/* -----\/----- EXCLUDED -----\/----- - $display("%d %d", tagstart, logblockbytelen); - - - for(adr = 0; adr < numways * numlines; adr++) begin - assign way = adr % numways; - assign index = adr / numways; - force testbench.dut.hart.lsu.dcache.SRAMAdr = index; - assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way]; - assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way]; - assign valid = testbench.dut.hart.lsu.dcache.Valid[way]; - assign FullAdr = tag< Date: Tue, 13 Jul 2021 11:18:54 -0500 Subject: [PATCH 18/47] restored rv64ic config back to full sized dtim. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 745196890..44a90e1c2 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h0007FFFF +`define TIM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF From 40922cf0645b7dcb5a5923d4c94dc3ae6a17eaa4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 11:21:44 -0500 Subject: [PATCH 19/47] Fixed subword write. subword read should not feed into subword write. --- wally-pipelined/src/cache/dcache.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index a5443417b..f36a962cc 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -239,7 +239,7 @@ module dcache .q(ReadDataW)); // write path - subwordwrite subwordwrite(.HRDATA(FinalReadDataWordM), + subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HWDATAIN(WriteDataM), From 2004b2e0447caed6d0e0fb7692a1f28c144975de Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 12:46:20 -0500 Subject: [PATCH 20/47] Fixed back to back store issue. Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals. --- wally-pipelined/src/cache/dcache.sv | 15 ++++++++++++--- wally-pipelined/src/ieu/controller.sv | 3 ++- wally-pipelined/src/ieu/ieu.sv | 3 ++- wally-pipelined/src/lsu/lsu.sv | 4 ++++ wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++++ 5 files changed, 24 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index f36a962cc..d4391cc61 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -34,9 +34,11 @@ module dcache input logic FlushW, // cpu side + input logic [1:0] MemRWE, input logic [1:0] MemRWM, input logic [2:0] Funct3M, input logic [6:0] Funct7M, + input logic [1:0] AtomicE, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address @@ -299,6 +301,7 @@ module dcache // control path *** eventually move to own module. logic AnyCPUReqM; + logic AnyCPUReqE; logic FetchCountFlag; logic PreCntEn; logic CntEn; @@ -349,6 +352,7 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); + assign AnyCPUReqE = |MemRWE | (|AtomicE); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) @@ -406,7 +410,7 @@ module dcache case (CurrState) STATE_READY: begin // sram busy - if (AnyCPUReqM & SRAMWordWriteEnableW) begin + if (AnyCPUReqE & SRAMWordWriteEnableM) begin NextState = STATE_SRAM_BUSY; DCacheStall = 1'b1; end @@ -505,11 +509,16 @@ module dcache end STATE_MISS_WRITE_WORD: begin - DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; - NextState = STATE_READY; SelAdrM = 1'b1; + if (AnyCPUReqE & SRAMWordWriteEnableM) begin + NextState = STATE_SRAM_BUSY; + DCacheStall = 1'b1; + end else begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end end STATE_MISS_EVICT_DIRTY: begin diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 16fd5a8fb..09715a4b7 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -52,6 +52,7 @@ module controller( output logic [1:0] MemRWM, output logic CSRReadM, CSRWriteM, PrivilegedM, output logic SCE, + output logic [1:0] AtomicE, output logic [1:0] AtomicM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit @@ -84,7 +85,7 @@ module controller( logic TargetSrcD, W64D, MulDivD; logic CSRZeroSrcD; logic CSRReadD; - logic [1:0] AtomicD, AtomicE; + logic [1:0] AtomicD; logic CSRWriteD, CSRWriteE; logic InstrValidD, InstrValidE; logic PrivilegedD, PrivilegedE; diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 392378060..8cac09375 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -47,7 +47,9 @@ module ieu ( // Memory stage interface input logic DataMisalignedM, // from LSU input logic SquashSCW, // from LSU + output logic [1:0] MemRWE, // read/write control goes to LSU output logic [1:0] MemRWM, // read/write control goes to LSU + output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU @@ -86,7 +88,6 @@ module ieu ( logic RegWriteM, RegWriteW; logic MemReadE, CSRReadE; logic JumpE; - logic [1:0] MemRWE; controller c(.*); datapath dp(.*); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 432645f71..29190c3c6 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -37,9 +37,11 @@ module lsu // connected to cpu (controls) input logic [1:0] MemRWM, + input logic [1:0] MemRWE, input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, + input logic [1:0] AtomicE, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -299,10 +301,12 @@ module lsu .StallW(StallW), .FlushM(FlushM), .FlushW(FlushW), + .MemRWE(MemRWE), // *** add to arb .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), + .AtomicE(AtomicE), // *** add to arb .MemAdrE(MemAdrEtoDCache), // *** add to arb .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 80a0b32a5..5bcd4697b 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -63,6 +63,7 @@ module wallypipelinedhart // new signals that must connect through DP logic MulDivE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicE; logic [1:0] AtomicM; logic [`XLEN-1:0] SrcAE, SrcBE; logic [`XLEN-1:0] SrcAM; @@ -73,6 +74,7 @@ module wallypipelinedhart logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; + logic [1:0] MemRWE; logic [1:0] MemRWM; logic InstrValidM, InstrValidW; logic InstrMisalignedFaultM; @@ -174,9 +176,11 @@ module wallypipelinedhart .StallW(StallW), .FlushW(FlushW), // CPU interface + .MemRWE(MemRWE), .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), + .AtomicE(AtomicE), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), From ee09fa5f5856ed1b7ccf06f78b6e4ee3be44ac8b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 13:20:50 -0500 Subject: [PATCH 21/47] Moved StoreStall into the hazard unit instead of in the d cache. --- wally-pipelined/regression/wave.do | 69 +++++++------------ wally-pipelined/src/cache/dcache.sv | 40 ++--------- wally-pipelined/src/hazard/hazard.sv | 4 +- wally-pipelined/src/ieu/controller.sv | 7 +- wally-pipelined/src/ieu/ieu.sv | 3 +- wally-pipelined/src/lsu/lsu.sv | 4 -- .../src/wally/wallypipelinedhart.sv | 4 +- 7 files changed, 38 insertions(+), 93 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 753e51958..eba2ff090 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -239,6 +239,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testben add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/AnyCPUReqE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM @@ -258,12 +259,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay @@ -390,34 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436996]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436997]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436998]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436999]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437000]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437011]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437012]} -add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437268]} -add wave -noupdate /testbench/dut/uncore/dtim/RAM -add wave -noupdate /testbench/dut/uncore/dtim/A -add wave -noupdate /testbench/dut/uncore/dtim/HWDATA -add wave -noupdate /testbench/dut/uncore/dtim/memwrite -add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim -add wave -noupdate /testbench/dut/uncore/dtim/memread -add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate /testbench/dut/uncore/dtim/HCLK -add wave -noupdate /testbench/dut/hart/clk -add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr -add wave -noupdate /testbench/DCacheFlushFSM/CacheData -add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty -add wave -noupdate /testbench/DCacheFlushFSM/CacheTag -add wave -noupdate /testbench/DCacheFlushFSM/CacheValid -add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk -add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start -add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} +WaveRestoreCursors {{Cursor 12} {1053664 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -433,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {63529 ns} {63661 ns} +WaveRestoreZoom {1053586 ns} {1053736 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index d4391cc61..64ed53670 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -34,11 +34,9 @@ module dcache input logic FlushW, // cpu side - input logic [1:0] MemRWE, input logic [1:0] MemRWM, input logic [2:0] Funct3M, input logic [6:0] Funct7M, - input logic [1:0] AtomicE, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address @@ -301,7 +299,6 @@ module dcache // control path *** eventually move to own module. logic AnyCPUReqM; - logic AnyCPUReqE; logic FetchCountFlag; logic PreCntEn; logic CntEn; @@ -333,7 +330,6 @@ module dcache STATE_AMO_MISS_WRITE_WORD, STATE_AMO_UPDATE, STATE_AMO_WRITE, - STATE_SRAM_BUSY, STATE_PTW_READY, STATE_PTW_MISS_FETCH_WDV, STATE_PTW_MISS_FETCH_DONE, @@ -352,7 +348,6 @@ module dcache assign AnyCPUReqM = |MemRWM | (|AtomicM); - assign AnyCPUReqE = |MemRWE | (|AtomicE); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); flopenr #(LOGWPL+1) @@ -373,17 +368,6 @@ module dcache .q({SRAMWordWriteEnableW})); - // fsm state regs -/* -----\/----- EXCLUDED -----\/----- - flopenl #(.TYPE(statetype)) - FSMReg(.clk(clk), - .load(reset), - .en(1'b1), - .val(STATE_READY), - .d(NextState), - .q(CurrState)); - -----/\----- EXCLUDED -----/\----- */ - always_ff @(posedge clk, posedge reset) if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; @@ -409,13 +393,8 @@ module dcache case (CurrState) STATE_READY: begin - // sram busy - if (AnyCPUReqE & SRAMWordWriteEnableM) begin - NextState = STATE_SRAM_BUSY; - DCacheStall = 1'b1; - end // TLB Miss - else if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit @@ -434,6 +413,7 @@ module dcache DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end @@ -444,7 +424,7 @@ module dcache DCacheStall = 1'b1; end // fault - else if(|MemRWM & FaultM & ~DTLBMissM) begin + else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; end else NextState = STATE_READY; @@ -512,13 +492,8 @@ module dcache SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; SelAdrM = 1'b1; - if (AnyCPUReqE & SRAMWordWriteEnableM) begin - NextState = STATE_SRAM_BUSY; - DCacheStall = 1'b1; - end else begin - NextState = STATE_READY; - DCacheStall = 1'b0; - end + NextState = STATE_READY; + DCacheStall = 1'b0; end STATE_MISS_EVICT_DIRTY: begin @@ -543,11 +518,6 @@ module dcache end end - STATE_SRAM_BUSY: begin - DCacheStall = 1'b0; - NextState = STATE_READY; - end - STATE_CPU_BUSY : begin if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index f55521061..331fc3267 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -30,7 +30,7 @@ module hazard( input logic reset, // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, - input logic LoadStallD, MulDivStallD, CSRRdStallD, + input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, input logic DCacheStall, ICacheStallF, input logic FPUStallD, FStallD, input logic DivBusyE,FDivBusyE, @@ -56,7 +56,7 @@ module hazard( // If any stages are stalled, the first stage that isn't stalled must flush. assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE); - assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous + assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; assign StallWCause = DCacheStall | ICacheStallF; diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 09715a4b7..879767365 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -63,7 +63,8 @@ module controller( output logic [2:0] ResultSrcW, output logic InstrValidW, // Stall during CSRs - output logic CSRWritePendingDEM + output logic CSRWritePendingDEM, + output logic StoreStallD ); logic [6:0] OpD; @@ -219,5 +220,7 @@ module controller( {RegWriteM, ResultSrcM, InstrValidM}, {RegWriteW, ResultSrcW, InstrValidW}); - assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; + assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM; + + assign StoreStallD = MemRWE[0] & (|MemRWD | |AtomicD); endmodule diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 8cac09375..95761c36e 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -71,7 +71,8 @@ module ieu ( input logic DivDoneE, input logic DivBusyE, output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic CSRWritePendingDEM + output logic CSRWritePendingDEM, + output logic StoreStallD ); logic [2:0] ImmSrcD; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 29190c3c6..432645f71 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -37,11 +37,9 @@ module lsu // connected to cpu (controls) input logic [1:0] MemRWM, - input logic [1:0] MemRWE, input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, - input logic [1:0] AtomicE, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -301,12 +299,10 @@ module lsu .StallW(StallW), .FlushM(FlushM), .FlushW(FlushW), - .MemRWE(MemRWE), // *** add to arb .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), - .AtomicE(AtomicE), // *** add to arb .MemAdrE(MemAdrEtoDCache), // *** add to arb .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 5bcd4697b..f094df60a 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -91,7 +91,7 @@ module wallypipelinedhart logic DivDoneE; logic DivBusyE; logic RegWriteD; - logic LoadStallD, MulDivStallD, CSRRdStallD; + logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD; logic SquashSCM, SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; @@ -176,11 +176,9 @@ module wallypipelinedhart .StallW(StallW), .FlushW(FlushW), // CPU interface - .MemRWE(MemRWE), .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), - .AtomicE(AtomicE), .AtomicM(AtomicM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), From 2034a6584f638fcb6304f4ebb2929cec63e7cf07 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:19:04 -0500 Subject: [PATCH 22/47] Dcache AHB address generation was wrong. Needed to zero the offset. --- wally-pipelined/regression/wave.do | 65 ++++++++++++++--------------- wally-pipelined/src/cache/dcache.sv | 7 ++-- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index eba2ff090..da660f1c2 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -209,9 +209,6 @@ add wave -noupdate -group icache -expand -group memory -group {tag write} /testb add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked -add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM @@ -220,7 +217,6 @@ add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/har add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA -add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATANext add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR @@ -239,7 +235,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testben add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/AnyCPUReqE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM @@ -259,42 +254,41 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -393,9 +387,14 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate /testbench/dut/uncore/dtim/HWADDR +add wave -noupdate /testbench/dut/uncore/dtim/A +add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim +add wave -noupdate /testbench/dut/uncore/dtim/memwrite +add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1053664 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 12} {1303660 ns} 0} {{Cursor 4} {1303875 ns} 0} {{Cursor 5} {1304387 ns} 0} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +409,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1053586 ns} {1053736 ns} +WaveRestoreZoom {1304315 ns} {1304659 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 64ed53670..dee05b12f 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -268,7 +268,7 @@ module dcache // *** Coding style. this is just awful. The purpose is to align FetchCount to the // size of XLEN so we can fetch XLEN bits. FetchCount needs to be padded to PA_BITS length. - + // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .s(AHBWrite), @@ -276,9 +276,9 @@ module dcache generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrM; + assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrM; + assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; end endgenerate @@ -469,6 +469,7 @@ module dcache NextState = STATE_MISS_READ_WORD; SelAdrM = 1'b1; SetValidM = 1'b1; + ClearDirtyM = 1'b1; end STATE_MISS_READ_WORD: begin From 51249a0e04de2aec2b692673fb3501e78dd61d32 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:21:29 -0500 Subject: [PATCH 23/47] Fixed the fetch buffer accidental overwrite on eviction. --- wally-pipelined/regression/wave.do | 23 ++++++++++++----------- wally-pipelined/src/cache/dcache.sv | 2 +- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index da660f1c2..bc290a92a 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -238,6 +238,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} @@ -254,14 +255,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay @@ -393,8 +394,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1303660 ns} 0} {{Cursor 4} {1303875 ns} 0} {{Cursor 5} {1304387 ns} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 12} {1303743 ns} 0} {{Cursor 4} {1304324 ns} 0} {{Cursor 5} {1303977 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -409,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1304315 ns} {1304659 ns} +WaveRestoreZoom {1303670 ns} {1304014 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index dee05b12f..9fe98b74c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -260,7 +260,7 @@ module dcache generate for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer flopen #(`XLEN) fb(.clk(clk), - .en(AHBAck & (index == FetchCount)), + .en(AHBAck & AHBRead & (index == FetchCount)), .d(HRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); end From b780e471b4d65f94b449f47889fac431c99355bc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 14:51:42 -0500 Subject: [PATCH 24/47] Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. --- wally-pipelined/regression/wave.do | 6 +++--- wally-pipelined/src/cache/dcache.sv | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index bc290a92a..807eacbaa 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -394,8 +394,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1303743 ns} 0} {{Cursor 4} {1304324 ns} 0} {{Cursor 5} {1303977 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0} +quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +410,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1303670 ns} {1304014 ns} +WaveRestoreZoom {1979564 ns} {1979828 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9fe98b74c..3bcd4719f 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -401,11 +401,17 @@ module dcache else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // read hit valid cached else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end // write hit valid cached else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin From 278bbfbe3cb54ba491dbf46d7cc88d4679ff290f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 17:24:59 -0500 Subject: [PATCH 25/47] Partially working changes to support uncached memory access. Not sure what CommitedM is. --- wally-pipelined/regression/wave.do | 77 ++++++++++--------- wally-pipelined/src/cache/dcache.sv | 47 ++++++++--- wally-pipelined/src/ifu/ifu.sv | 3 + wally-pipelined/src/lsu/lsu.sv | 25 ++++-- wally-pipelined/src/mmu/mmu.sv | 2 +- .../src/wally/wallypipelinedhart.sv | 5 +- .../testbench/testbench-imperas.sv | 1 - 7 files changed, 103 insertions(+), 57 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 807eacbaa..f53880fd3 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -239,22 +239,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -272,8 +272,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM @@ -290,6 +288,15 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM @@ -312,20 +319,20 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn +add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR @@ -394,8 +401,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -410,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1979564 ns} {1979828 ns} +WaveRestoreZoom {4642 ns} {4816 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3bcd4719f..f33385df3 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -48,7 +48,7 @@ module dcache // inputs from TLB and PMA/P input logic FaultM, input logic DTLBMissM, - input logic UncachedM, + input logic CacheableM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -114,6 +114,8 @@ module dcache logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; + logic [OFFSETLEN-1:0] BasePAdrOffsetM; + logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; @@ -224,7 +226,7 @@ module dcache // variable input mux assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - assign HWDATA = VictimReadDataBlockSetsM[FetchCount]; + assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; // finally swr // *** BUG fix HSIZED? why was it this way? @@ -271,14 +273,17 @@ module dcache // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(AHBWrite), + .s(AHBWrite & CacheableM), .y(BasePAdrM)); + + assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; + assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM}; generate if (`XLEN == 32) begin - assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM; end else begin - assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; + assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM; end endgenerate @@ -339,6 +344,8 @@ module dcache STATE_PTW_MISS_READ_SRAM, STATE_UNCACHED_WDV, STATE_UNCACHED_DONE, + STATE_UNCACHED_WRITE, + STATE_UNCACHED_WRITE_DONE, STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -398,7 +405,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; @@ -406,7 +413,7 @@ module dcache else NextState = STATE_READY; end // read hit valid cached - else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -414,7 +421,7 @@ module dcache else NextState = STATE_READY; end // write hit valid cached - else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -424,11 +431,19 @@ module dcache else NextState = STATE_READY; end // read or write miss valid cached - else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end + // uncached write + else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_WRITE; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBWrite = 1'b1; + + end // fault else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin NextState = STATE_READY; @@ -529,6 +544,20 @@ module dcache if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end + + STATE_UNCACHED_WRITE : begin + DCacheStall = 1'b1; + AHBWrite = 1'b1; + if(AHBAck) begin + NextState = STATE_UNCACHED_WRITE_DONE; + end else begin + NextState = STATE_UNCACHED_WRITE; + end + end + + STATE_UNCACHED_WRITE_DONE: begin + NextState = STATE_READY; + end default: begin end endcase diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index e306efa40..af5686d5c 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -136,6 +136,9 @@ module ifu ( .LoadAccessFaultM(), .StoreAccessFaultM(), .DisableTranslation(1'b0), + .Cacheable(), + .Idempotent(), + .AtomicAllowed(), .*); diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 432645f71..9ed573a9d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -62,12 +62,13 @@ module lsu // connect to ahb input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb + output logic [`PA_BITS-1:0] DCtoAHBPAdrM, output logic DCtoAHBReadM, output logic DCtoAHBWriteM, - input logic DCfromAHBAck, // from ahb - input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb - output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb + input logic DCfromAHBAck, + input logic [`XLEN-1:0] DCfromAHBReadData, + output logic [`XLEN-1:0] DCtoAHBWriteData, + output logic [2:0] DCtoAHBSizeM, // mmu management @@ -140,8 +141,8 @@ module lsu logic HPTWReady; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. logic DCacheStall; - - + + logic CacheableM; pagetablewalker pagetablewalker( .clk(clk), @@ -223,9 +224,19 @@ module lsu .SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), + .Cacheable(CacheableM), + .Idempotent(), + .AtomicAllowed(), // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + + generate + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache; + else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache; + endgenerate; + + // Specify which type of page fault is occurring assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1]; assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0]; @@ -310,7 +321,7 @@ module lsu .DCacheStall(DCacheStall), .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. .DTLBMissM(DTLBMissM), - .UncachedM(1'b0), // ***connect to PMA + .CacheableM(CacheableM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 9372f473d..d71cbe81f 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -60,6 +60,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries output logic [`PA_BITS-1:0] PhysicalAddress, output logic TLBMiss, output logic TLBHit, + output logic Cacheable, Idempotent, AtomicAllowed, // Faults output logic TLBPageFault, @@ -76,7 +77,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries ); logic PMPSquashBusAccess, PMASquashBusAccess; - logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here. // Translation lookaside buffer logic PMAInstrAccessFaultF, PMPInstrAccessFaultF; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index f094df60a..55c8959f4 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -196,6 +196,7 @@ module wallypipelinedhart .DCfromAHBAck(DCfromAHBAck), .DCfromAHBReadData(DCfromAHBReadData), .DCtoAHBWriteData(DCtoAHBWriteData), + .DCtoAHBSizeM(DCtoAHBSizeM), // connect to csr or privilege and stay the same. .PrivilegeModeW(PrivilegeModeW), // connects to csr @@ -231,10 +232,6 @@ module wallypipelinedhart .LSUStall(DCacheStall)); // change to DCacheStall - generate - if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010; - else assign DCtoAHBSizeM = 3'b011; - endgenerate; ahblite ebu(// IFU connections diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 25cb1ef62..654c34fb4 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -547,7 +547,6 @@ string tests32f[] = '{ if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - tests = {tests64i, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From b6e5670bc39878622f238845633a59b306c24fc1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 22:43:42 -0500 Subject: [PATCH 26/47] Added CommitedM to data cache output. --- wally-pipelined/src/cache/dcache.sv | 20 +++++++++++++------- wally-pipelined/src/lsu/lsu.sv | 6 +++--- wally-pipelined/src/lsu/lsuArb.sv | 3 --- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index f33385df3..9f2c06521 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -44,6 +44,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, output logic DCacheStall, + output logic CommittedM, // inputs from TLB and PMA/P input logic FaultM, @@ -311,12 +312,6 @@ module dcache typedef enum {STATE_READY, - STATE_READ_MISS_FETCH_WDV, - STATE_READ_MISS_FETCH_DONE, - STATE_READ_MISS_CHECK_EVICTED_DIRTY, - STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_READ_MISS_WRITE_CACHE_BLOCK, - STATE_READ_MISS_READ_WORD, STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, @@ -397,7 +392,8 @@ module dcache AHBRead = 1'b0; AHBWrite = 1'b0; SelAMOWrite = 1'b0; - + CommittedM = 1'b0; + case (CurrState) STATE_READY: begin // TLB Miss @@ -466,6 +462,8 @@ module dcache PreCntEn = 1'b1; AHBRead = 1'b1; SelAdrM = 1'b1; + CommittedM = 1'b1; + if (FetchCountFlag & AHBAck) begin NextState = STATE_MISS_FETCH_DONE; end else begin @@ -477,6 +475,7 @@ module dcache DCacheStall = 1'b1; SelAdrM = 1'b1; CntReset = 1'b1; + CommittedM = 1'b1; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; end else begin @@ -491,11 +490,13 @@ module dcache SelAdrM = 1'b1; SetValidM = 1'b1; ClearDirtyM = 1'b1; + CommittedM = 1'b1; end STATE_MISS_READ_WORD: begin SelAdrM = 1'b1; DCacheStall = 1'b1; + CommittedM = 1'b1; if (MemRWM[1]) begin NextState = STATE_MISS_READ_WORD_DELAY; // delay state is required as the read signal MemRWM[1] is still high when we @@ -508,6 +509,7 @@ module dcache STATE_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; NextState = STATE_READY; + CommittedM = 1'b1; end STATE_MISS_WRITE_WORD: begin @@ -516,6 +518,7 @@ module dcache SelAdrM = 1'b1; NextState = STATE_READY; DCacheStall = 1'b0; + CommittedM = 1'b1; end STATE_MISS_EVICT_DIRTY: begin @@ -523,6 +526,7 @@ module dcache PreCntEn = 1'b1; AHBWrite = 1'b1; SelAdrM = 1'b1; + CommittedM = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin @@ -548,6 +552,7 @@ module dcache STATE_UNCACHED_WRITE : begin DCacheStall = 1'b1; AHBWrite = 1'b1; + CommittedM = 1'b1; if(AHBAck) begin NextState = STATE_UNCACHED_WRITE_DONE; end else begin @@ -556,6 +561,7 @@ module dcache end STATE_UNCACHED_WRITE_DONE: begin + CommittedM = 1'b1; NextState = STATE_READY; end default: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 9ed573a9d..7a02ff2fa 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -99,7 +99,9 @@ module lsu logic DTLBPageFaultM; logic MemAccessM; +/* -----\/----- EXCLUDED -----\/----- logic preCommittedM; + -----/\----- EXCLUDED -----/\----- */ typedef enum {STATE_READY, STATE_FETCH, @@ -135,7 +137,6 @@ module lsu logic [`XLEN-1:0] MemAdrEtoDCache; logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; - logic CommittedMfromDCache; logic SquashSCWfromDCache; logic DataMisalignedMfromDCache; logic HPTWReady; @@ -187,7 +188,6 @@ module lsu .MemAdrM(MemAdrM), .StallW(StallW), .ReadDataW(ReadDataW), - .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), .LSUStall(LSUStall), @@ -198,7 +198,6 @@ module lsu .AtomicMtoDCache(AtomicMtoDCache), .MemAdrMtoDCache(MemAdrMtoDCache), .StallWtoDCache(StallWtoDCache), - .CommittedMfromDCache(CommittedMfromDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), @@ -319,6 +318,7 @@ module lsu .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), + .CommittedM(CommittedM), .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 83ab93be0..62d8b35af 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -45,7 +45,6 @@ module lsuArb input logic StallW, // to CPU output logic [`XLEN-1:0] ReadDataW, - output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, output logic LSUStall, @@ -58,7 +57,6 @@ module lsuArb output logic [`XLEN-1:0] MemAdrMtoDCache, output logic StallWtoDCache, // from LSU - input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, @@ -149,7 +147,6 @@ module lsuArb assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux - assign CommittedM = SelPTW ? 1'b0 : CommittedMfromDCache; assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. From ef598d0e79989ca2f22723de4d1781ebcd2a3152 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jul 2021 23:03:09 -0500 Subject: [PATCH 27/47] Implemented uncached reads. --- wally-pipelined/regression/wave.do | 4 +-- wally-pipelined/src/cache/dcache.sv | 42 +++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index f53880fd3..f0bba8078 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -401,7 +401,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4642 ns} {4816 ns} +WaveRestoreZoom {5566 ns} {5750 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 9f2c06521..ba73f73a6 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -90,7 +90,7 @@ module dcache logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; + logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM, ReadDataWordMuxM; logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [LOGWPL:0] FetchCount, NextFetchCount; @@ -111,6 +111,7 @@ module dcache logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; logic SelAMOWrite; + logic SelUncached; logic [6:0] Funct7W; logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -229,12 +230,18 @@ module dcache assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM; + mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), + .d1(DCacheMemWriteData[`XLEN-1:0]), + .s(SelUncached), + .y(ReadDataWordMuxM)); + // finally swr // *** BUG fix HSIZED? why was it this way? - subwordread subwordread(.HRDATA(ReadDataWordM), + subwordread subwordread(.HRDATA(ReadDataWordMuxM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HRDATAMasked(FinalReadDataWordM)); + flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(~StallW), @@ -337,10 +344,10 @@ module dcache STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, STATE_PTW_MISS_WRITE_CACHE_BLOCK, STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WDV, - STATE_UNCACHED_DONE, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, + STATE_UNCACHED_READ, + STATE_UNCACHED_READ_DONE, STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -393,6 +400,7 @@ module dcache AHBWrite = 1'b0; SelAMOWrite = 1'b0; CommittedM = 1'b0; + SelUncached = 1'b0; case (CurrState) STATE_READY: begin @@ -438,7 +446,13 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; AHBWrite = 1'b1; - + end + // uncached read + else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_READ; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBRead = 1'b1; end // fault else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin @@ -560,10 +574,28 @@ module dcache end end + STATE_UNCACHED_READ : begin + DCacheStall = 1'b1; + AHBRead = 1'b1; + CommittedM = 1'b1; + if(AHBAck) begin + NextState = STATE_UNCACHED_READ_DONE; + end else begin + NextState = STATE_UNCACHED_READ; + end + end + STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; NextState = STATE_READY; end + + STATE_UNCACHED_READ_DONE: begin + CommittedM = 1'b1; + SelUncached = 1'b1; + NextState = STATE_READY; + end + default: begin end endcase From e17de4eb11f11cb735b0bbe09694e42bd13d86ce Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:00:33 -0500 Subject: [PATCH 28/47] Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. This solves the committedM issue. --- wally-pipelined/src/cache/dcache.sv | 19 +++++---- wally-pipelined/src/lsu/lsu.sv | 5 ++- wally-pipelined/src/privileged/privileged.sv | 2 + wally-pipelined/src/privileged/trap.sv | 42 +++++++++++-------- .../src/wally/wallypipelinedhart.sv | 6 ++- 5 files changed, 45 insertions(+), 29 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ba73f73a6..0efbcf41b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -44,10 +44,11 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, output logic DCacheStall, - output logic CommittedM, + output logic CommittedM, // inputs from TLB and PMA/P - input logic FaultM, + input logic ExceptionM, + input logic PendingInterruptM, input logic DTLBMissM, input logic CacheableM, // ahb side @@ -409,7 +410,7 @@ module dcache NextState = STATE_PTW_MISS_FETCH_WDV; end // amo hit - else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin NextState = STATE_AMO_UPDATE; DCacheStall = 1'b1; @@ -417,7 +418,7 @@ module dcache else NextState = STATE_READY; end // read hit valid cached - else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -425,7 +426,7 @@ module dcache else NextState = STATE_READY; end // write hit valid cached - else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin + else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin SelAdrM = 1'b1; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -435,27 +436,27 @@ module dcache else NextState = STATE_READY; end // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin + else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin NextState = STATE_MISS_FETCH_WDV; CntReset = 1'b1; DCacheStall = 1'b1; end // uncached write - else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin NextState = STATE_UNCACHED_WRITE; CntReset = 1'b1; DCacheStall = 1'b1; AHBWrite = 1'b1; end // uncached read - else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin + else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin NextState = STATE_UNCACHED_READ; CntReset = 1'b1; DCacheStall = 1'b1; AHBRead = 1'b1; end // fault - else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin + else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin NextState = STATE_READY; end else NextState = STATE_READY; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 7a02ff2fa..71113fbd2 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -40,6 +40,8 @@ module lsu input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic [1:0] AtomicM, + input logic ExceptionM, + input logic PendingInterruptM, output logic CommittedM, output logic SquashSCW, output logic DataMisalignedM, @@ -319,7 +321,8 @@ module lsu .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), .CommittedM(CommittedM), - .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults. + .ExceptionM(ExceptionM), + .PendingInterruptM(PendingInterruptM), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index e80c0b851..fcc225db2 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -64,6 +64,8 @@ module privileged ( input logic LoadAccessFaultM, input logic StoreAccessFaultM, + output logic ExceptionM, + output logic PendingInterruptM, output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 9eec51c26..7462353db 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -27,23 +27,26 @@ `include "wally-config.vh" module trap ( - input logic clk, reset, - input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, - input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, - input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, - input logic LoadPageFaultM, StorePageFaultM, - input logic mretM, sretM, uretM, - input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, - input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, - input logic [31:0] InstrM, - input logic StallW, - input logic InstrValidM, CommittedM, - output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, - output logic InterruptM, + input logic clk, reset, + input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, + input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, + input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, + input logic LoadPageFaultM, StorePageFaultM, + input logic mretM, sretM, uretM, + input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, + input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, + input logic STATUS_MIE, STATUS_SIE, + input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, + input logic [31:0] InstrM, + input logic StallW, + input logic InstrValidM, CommittedM, + output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, + output logic InterruptM, + output logic ExceptionM, + output logic PendingInterruptM, + output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM @@ -59,7 +62,10 @@ module trap ( assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222)); - assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM; + assign PendingInterruptM = (|PendingIntsM) & InstrValidM; + assign InterruptM = PendingInterruptM & ~CommittedM; + assign ExceptionM = BusTrapM | NonBusTrapM; + // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 55c8959f4..e0337bc39 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -161,6 +161,8 @@ module wallypipelinedhart logic InstrAccessFaultF; logic [2:0] DCtoAHBSizeM; + logic ExceptionM; + logic PendingInterruptM; ifu ifu(.InstrInF(InstrRData), @@ -179,7 +181,9 @@ module wallypipelinedhart .MemRWM(MemRWM), .Funct3M(Funct3M), .Funct7M(InstrM[31:25]), - .AtomicM(AtomicM), + .AtomicM(AtomicM), + .ExceptionM(ExceptionM), + .PendingInterruptM(PendingInterruptM), .CommittedM(CommittedM), .SquashSCW(SquashSCW), .DataMisalignedM(DataMisalignedM), From 3092e5acdffc22ad3340eb75a4c9afbd591d7dcb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:46:52 -0500 Subject: [PATCH 29/47] Forgot to include one hot decoder. --- wally-pipelined/src/generic/oneHotDecoder.sv | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 wally-pipelined/src/generic/oneHotDecoder.sv diff --git a/wally-pipelined/src/generic/oneHotDecoder.sv b/wally-pipelined/src/generic/oneHotDecoder.sv new file mode 100644 index 000000000..08bd2e01c --- /dev/null +++ b/wally-pipelined/src/generic/oneHotDecoder.sv @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// oneHotDecoder.sv +// +// Written: ross1728@gmail.com July 09, 2021 +// Modified: +// +// Purpose: Bin to one hot decoder. Power of 2 only. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module oneHotDecoder + #(parameter WIDTH = 2) + (input logic [WIDTH-1:0] bin, + output logic [2**WIDTH-1:0] decoded + ); + + always_comb begin + decoded = '0; + decoded[bin] = 1'b1; + end + +endmodule From 1d7aa2731654de71fa75ce4feb7c14ca90738a6b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 15:47:38 -0500 Subject: [PATCH 30/47] Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. --- wally-pipelined/src/cache/dcache.sv | 97 ++++++++++++++++------------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 0efbcf41b..b7665fa83 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -121,6 +121,50 @@ module dcache logic [`PA_BITS-1:0] BasePAdrMaskedM; logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; + + logic ReadDataWEn; + + logic AnyCPUReqM; + logic FetchCountFlag; + logic PreCntEn; + logic CntEn; + logic CntReset; + logic CPUBusy, PreviousCPUBusy; + + + typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_MISS_WRITE_CACHE_BLOCK, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, + STATE_AMO_MISS_FETCH_DONE, + STATE_AMO_MISS_CHECK_EVICTED_DIRTY, + STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_AMO_MISS_WRITE_CACHE_BLOCK, + STATE_AMO_MISS_READ_WORD, + STATE_AMO_MISS_UPDATE_WORD, + STATE_AMO_MISS_WRITE_WORD, + STATE_AMO_UPDATE, + STATE_AMO_WRITE, + STATE_PTW_READY, + STATE_PTW_MISS_FETCH_WDV, + STATE_PTW_MISS_FETCH_DONE, + STATE_PTW_MISS_CHECK_EVICTED_DIRTY, + STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, + STATE_PTW_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_MISS_READ_SRAM, + STATE_UNCACHED_WRITE, + STATE_UNCACHED_WRITE_DONE, + STATE_UNCACHED_READ, + STATE_UNCACHED_READ_DONE, + STATE_CPU_BUSY} statetype; + + statetype CurrState, NextState; flopenr #(7) Funct7WReg(.clk(clk), @@ -242,10 +286,19 @@ module dcache .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HRDATAMasked(FinalReadDataWordM)); - + // This is a confusing point. + // The final read data should be updated only if the CPU's StallW is low + // which means the CPU is ready to take data. Or if the CPU just became + // busy. Then when we exit CPU_BUSY we want to ensure the data is not + // updated, this is ~PreviousCPUBusy. + assign CPUBusy = CurrState == STATE_CPU_BUSY; + flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); + + assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY); + flopen #(`XLEN) ReadDataWReg(.clk(clk), - .en(~StallW), + .en(ReadDataWEn), .d(FinalReadDataWordM), .q(ReadDataW)); @@ -312,46 +365,6 @@ module dcache // control path *** eventually move to own module. - logic AnyCPUReqM; - logic FetchCountFlag; - logic PreCntEn; - logic CntEn; - logic CntReset; - - - typedef enum {STATE_READY, - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_MISS_WRITE_CACHE_BLOCK, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - STATE_AMO_MISS_FETCH_WDV, - STATE_AMO_MISS_FETCH_DONE, - STATE_AMO_MISS_CHECK_EVICTED_DIRTY, - STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_AMO_MISS_WRITE_CACHE_BLOCK, - STATE_AMO_MISS_READ_WORD, - STATE_AMO_MISS_UPDATE_WORD, - STATE_AMO_MISS_WRITE_WORD, - STATE_AMO_UPDATE, - STATE_AMO_WRITE, - STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, - STATE_UNCACHED_WRITE, - STATE_UNCACHED_WRITE_DONE, - STATE_UNCACHED_READ, - STATE_UNCACHED_READ_DONE, - STATE_CPU_BUSY} statetype; - - statetype CurrState, NextState; localparam FetchCountThreshold = WORDSPERLINE - 1; From 771c7ff130093fd4c28b6e71b15ba688c2ecffd4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 16:18:09 -0500 Subject: [PATCH 31/47] Routed CommittedM and PendingInterruptM through the lsu arb. --- wally-pipelined/regression/wave.do | 147 ++++++++++-------- wally-pipelined/src/lsu/lsu.sv | 12 +- wally-pipelined/src/lsu/lsuArb.sv | 24 +-- .../testbench/testbench-imperas.sv | 4 +- 4 files changed, 102 insertions(+), 85 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index f0bba8078..e34eb866f 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,44 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -130,6 +137,7 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -147,12 +155,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/hart/PCF -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/hart/PCE -add wave -noupdate -group PCS /testbench/dut/hart/PCM -add wave -noupdate -group PCS /testbench/PCW +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -239,22 +247,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -278,6 +286,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -333,20 +342,20 @@ add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPi add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead @@ -401,7 +410,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0} +WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +426,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {5566 ns} {5750 ns} +WaveRestoreZoom {718645 ns} {719057 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 71113fbd2..882c2dcd8 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -146,6 +146,10 @@ module lsu logic DCacheStall; logic CacheableM; + + logic CommittedMfromDCache; + logic PendingInterruptMtoDCache; + pagetablewalker pagetablewalker( .clk(clk), @@ -188,6 +192,8 @@ module lsu .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), + .CommittedM(CommittedM), + .PendingInterruptM(PendingInterruptM), .StallW(StallW), .ReadDataW(ReadDataW), .SquashSCW(SquashSCW), @@ -203,6 +209,8 @@ module lsu .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), + .CommittedMfromDCache(CommittedMfromDCache), + .PendingInterruptMtoDCache(PendingInterruptMtoDCache), .DCacheStall(DCacheStall)); @@ -320,9 +328,9 @@ module lsu .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), .DCacheStall(DCacheStall), - .CommittedM(CommittedM), + .CommittedM(CommittedMfromDCache), .ExceptionM(ExceptionM), - .PendingInterruptM(PendingInterruptM), + .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 62d8b35af..08024d0b8 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -43,20 +43,25 @@ module lsuArb input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, input logic StallW, + input logic PendingInterruptM, // to CPU output logic [`XLEN-1:0] ReadDataW, output logic SquashSCW, output logic DataMisalignedM, + output logic CommittedM, output logic LSUStall, - // to LSU + // to D Cache output logic DisableTranslation, output logic [1:0] MemRWMtoDCache, output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, output logic StallWtoDCache, - // from LSU + output logic PendingInterruptMtoDCache, + + // from D Cache + input logic CommittedMfromDCache, input logic SquashSCWfromDCache, input logic DataMisalignedMfromDCache, input logic [`XLEN-1:0] ReadDataWfromDCache, @@ -82,7 +87,6 @@ module lsuArb statetype CurrState, NextState; logic SelPTW; - logic HPTWStallD; logic [2:0] PTWSize; @@ -142,6 +146,8 @@ module lsuArb assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; + // always block interrupts when using the hardware page table walker. + assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; // demux the inputs from LSU to walker or cpu's data port. @@ -153,15 +159,9 @@ module lsuArb // not clear at all. I think it should be LSUStall from the LSU, // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one). assign HPTWStall = SelPTW ? DCacheStall : 1'b1; - //assign HPTWStallD = SelPTW ? DataStall : 1'b1; -/* -----\/----- EXCLUDED -----\/----- - assign HPTWStallD = SelPTW ? DataStall : 1'b1; - flopr #(1) HPTWStallReg (.clk(clk), - .reset(reset), - .d(HPTWStallD), - .q(HPTWStall)); - -----/\----- EXCLUDED -----/\----- */ - + + assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM; + assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change. endmodule diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 654c34fb4..d2cd6dcb7 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -539,11 +539,11 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64p,tests64i,tests64periph}; + tests = {tests64p,tests64i}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`A_SUPPORTED) tests = {tests, tests64a}; + //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; From d3a1a2c90a78803877db05fedab6ce90ca8af1e3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 17:23:28 -0500 Subject: [PATCH 32/47] Fixed d cache not honoring StallW for uncache writes and reads. --- wally-pipelined/regression/wave.do | 123 ++++++++---------- wally-pipelined/src/cache/dcache.sv | 97 +++++++++++--- wally-pipelined/src/lsu/lsu.sv | 1 + .../testbench/testbench-imperas.sv | 2 +- 4 files changed, 138 insertions(+), 85 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index e34eb866f..bda6f4141 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,10 +7,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM @@ -27,14 +27,14 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -306,15 +306,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/ReadDataW -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/StallW -add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/LSUStall +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -328,34 +323,34 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn -add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead @@ -370,12 +365,12 @@ add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/ add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -399,18 +394,14 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate /testbench/dut/uncore/dtim/HWADDR -add wave -noupdate /testbench/dut/uncore/dtim/A -add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim -add wave -noupdate /testbench/dut/uncore/dtim/memwrite -add wave -noupdate /testbench/dut/uncore/dtim/HWDATA +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE +add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0} +WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -426,4 +417,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {718645 ns} {719057 ns} +WaveRestoreZoom {4026 ns} {4254 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b7665fa83..3397bedb9 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -48,9 +48,10 @@ module dcache // inputs from TLB and PMA/P input logic ExceptionM, - input logic PendingInterruptM, + input logic PendingInterruptM, input logic DTLBMissM, input logic CacheableM, + input logic DTLBWriteM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -133,6 +134,7 @@ module dcache typedef enum {STATE_READY, + STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, @@ -141,6 +143,7 @@ module dcache STATE_MISS_READ_WORD, STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, + STATE_AMO_MISS_FETCH_WDV, STATE_AMO_MISS_FETCH_DONE, STATE_AMO_MISS_CHECK_EVICTED_DIRTY, @@ -151,17 +154,19 @@ module dcache STATE_AMO_MISS_WRITE_WORD, STATE_AMO_UPDATE, STATE_AMO_WRITE, + STATE_PTW_READY, - STATE_PTW_MISS_FETCH_WDV, - STATE_PTW_MISS_FETCH_DONE, - STATE_PTW_MISS_CHECK_EVICTED_DIRTY, - STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK, - STATE_PTW_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_MISS_READ_SRAM, + STATE_PTW_READ_MISS_FETCH_WDV, + STATE_PTW_READ_MISS_FETCH_DONE, + STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, + STATE_PTW_READ_MISS_READ_WORD, + STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, STATE_UNCACHED_READ, STATE_UNCACHED_READ_DONE, + STATE_CPU_BUSY} statetype; statetype CurrState, NextState; @@ -420,7 +425,7 @@ module dcache STATE_READY: begin // TLB Miss if(AnyCPUReqM & DTLBMissM) begin - NextState = STATE_PTW_MISS_FETCH_WDV; + NextState = STATE_PTW_READY; end // amo hit else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin @@ -428,11 +433,10 @@ module dcache DCacheStall = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; + else NextState = STATE_AMO_UPDATE; end // read hit valid cached else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - NextState = STATE_READY; DCacheStall = 1'b0; if(StallW) NextState = STATE_CPU_BUSY; @@ -562,14 +566,69 @@ module dcache end end - STATE_PTW_MISS_FETCH_WDV: begin + STATE_PTW_READY: begin + CommittedM = 1'b1; + // return to ready if page table walk completed. + if(DTLBWriteM) begin + NextState = STATE_READY; + + // read hit valid cached + end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin + NextState = STATE_PTW_READY; + DCacheStall = 1'b0; + end + + // read miss valid cached + else if((MemRWM[1]) & CacheableM & ~ExceptionM & ~CacheHit) begin + NextState = STATE_PTW_READ_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + end + + STATE_PTW_READ_MISS_FETCH_WDV: begin + DCacheStall = 1'b1; + PreCntEn = 1'b1; + AHBRead = 1'b1; + SelAdrM = 1'b1; + CommittedM = 1'b1; + + if (FetchCountFlag & AHBAck) begin + NextState = STATE_PTW_READ_MISS_FETCH_DONE; + end else begin + NextState = STATE_PTW_READ_MISS_FETCH_WDV; + end + end + + STATE_PTW_READ_MISS_FETCH_DONE: begin DCacheStall = 1'b1; SelAdrM = 1'b1; - if (FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_MISS_FETCH_DONE; - end else begin - NextState = STATE_PTW_MISS_FETCH_WDV; - end + CntReset = 1'b1; + CommittedM = 1'b1; + NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; + end + + STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin + SRAMBlockWriteEnableM = 1'b1; + DCacheStall = 1'b1; + NextState = STATE_PTW_READ_MISS_READ_WORD; + SelAdrM = 1'b1; + SetValidM = 1'b1; + ClearDirtyM = 1'b1; + CommittedM = 1'b1; + end + + STATE_PTW_READ_MISS_READ_WORD: begin + SelAdrM = 1'b1; + DCacheStall = 1'b1; + CommittedM = 1'b1; + NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY; + end + + STATE_PTW_READ_MISS_READ_WORD_DELAY: begin + SelAdrM = 1'b1; + NextState = STATE_PTW_READY; + CommittedM = 1'b1; end STATE_CPU_BUSY : begin @@ -601,13 +660,15 @@ module dcache STATE_UNCACHED_WRITE_DONE: begin CommittedM = 1'b1; - NextState = STATE_READY; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_UNCACHED_READ_DONE: begin CommittedM = 1'b1; SelUncached = 1'b1; - NextState = STATE_READY; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end default: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 882c2dcd8..8f739822e 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -333,6 +333,7 @@ module lsu .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), .CacheableM(CacheableM), + .DTLBWriteM(DTLBWriteM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index d2cd6dcb7..56a019e83 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -544,9 +544,9 @@ string tests32f[] = '{ else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; //if (`A_SUPPORTED) tests = {tests, tests64a}; - if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From d41c9d5ad9b0d6c183187bb09356462c805a43f3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 17:25:50 -0500 Subject: [PATCH 33/47] Added d cache StallW checks for any time the cache wants to go to STATE_READY. --- wally-pipelined/src/cache/dcache.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3397bedb9..a22c5d9b8 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -485,8 +485,9 @@ module dcache SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle end STATE_AMO_WRITE: begin - NextState = STATE_READY; SelAMOWrite = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_FETCH_WDV: begin @@ -540,17 +541,19 @@ module dcache STATE_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_READY; CommittedM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_WRITE_WORD: begin SRAMWordWriteEnableM = 1'b1; SetDirtyM = 1'b1; SelAdrM = 1'b1; - NextState = STATE_READY; DCacheStall = 1'b0; CommittedM = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; end STATE_MISS_EVICT_DIRTY: begin From 616362920421f355eddca5f207baa4e7a2cb0871 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 22:26:07 -0500 Subject: [PATCH 34/47] Finally have the ptw correctly walking through the dcache to update the itlb. Still not working fully. --- wally-pipelined/regression/wave.do | 179 ++-- wally-pipelined/src/cache/dcache.sv | 14 +- wally-pipelined/src/lsu/lsu.sv | 45 +- wally-pipelined/src/lsu/lsuArb.sv | 19 +- wally-pipelined/src/mmu/pagetablewalker.sv | 784 +++++++++--------- .../testbench/testbench-imperas.sv | 2 +- 6 files changed, 551 insertions(+), 492 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index bda6f4141..4205be707 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -3,48 +3,49 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename +add wave -noupdate /testbench/dut/hart/SATP_REGW add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -112,7 +113,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -155,12 +156,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/hart/PCF +add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/hart/PCE +add wave -noupdate -group PCS /testbench/dut/hart/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -239,6 +240,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -271,18 +278,23 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall @@ -297,6 +309,9 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed @@ -306,6 +321,10 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress @@ -351,26 +370,28 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -divider data -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -group {LSU ARB} -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -group {LSU ARB} -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group ptwalker -divider data +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM +add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -395,13 +416,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HCLK -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HSELUART -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HADDR -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWRITE -add wave -noupdate -expand -group UART /testbench/dut/uncore/genblk4/uart/HWDATA +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE +add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA +add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN +add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 12} {4076 ns} 0} {{Cursor 4} {8790617 ns} 0} +WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -417,4 +440,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4026 ns} {4254 ns} +WaveRestoreZoom {21597 ns} {21891 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index a22c5d9b8..b0ac33281 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -43,6 +43,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, + output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, @@ -131,6 +132,7 @@ module dcache logic CntEn; logic CntReset; logic CPUBusy, PreviousCPUBusy; + logic SelEvict; typedef enum {STATE_READY, @@ -297,16 +299,22 @@ module dcache // which means the CPU is ready to take data. Or if the CPU just became // busy. Then when we exit CPU_BUSY we want to ensure the data is not // updated, this is ~PreviousCPUBusy. + // also must update if cpu stalled and processing a read miss + // which occurs if in state miss read word delay. assign CPUBusy = CurrState == STATE_CPU_BUSY; flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy)); - assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | (NextState == STATE_CPU_BUSY & CurrState == STATE_READY); + assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) | + (NextState == STATE_CPU_BUSY & CurrState == STATE_READY) | + (CurrState == STATE_MISS_READ_WORD_DELAY); flopen #(`XLEN) ReadDataWReg(.clk(clk), .en(ReadDataWEn), .d(FinalReadDataWordM), .q(ReadDataW)); + assign ReadDataM = FinalReadDataWordM; + // write path subwordwrite subwordwrite(.HRDATA(ReadDataWordM), .HADDRD(MemPAdrM[2:0]), @@ -340,7 +348,7 @@ module dcache // *** optimize this mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM), .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(AHBWrite & CacheableM), + .s(SelEvict), .y(BasePAdrM)); assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0]; @@ -420,6 +428,7 @@ module dcache SelAMOWrite = 1'b0; CommittedM = 1'b0; SelUncached = 1'b0; + SelEvict = 1'b0; case (CurrState) STATE_READY: begin @@ -562,6 +571,7 @@ module dcache AHBWrite = 1'b1; SelAdrM = 1'b1; CommittedM = 1'b1; + SelEvict = 1'b1; if( FetchCountFlag & AHBAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 8f739822e..f8fa87a02 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -129,9 +129,10 @@ module lsu logic [`XLEN-1:0] HPTWReadPTE; logic MMUReady; logic HPTWStall; - logic [`XLEN-1:0] HPTWPAdr; + logic [`XLEN-1:0] HPTWPAdrE; + logic [`XLEN-1:0] HPTWPAdrM; logic HPTWTranslate; - logic HPTWRead; + logic HPTWReadM; logic [1:0] MemRWMtoDCache; logic [2:0] Funct3MtoDCache; logic [1:0] AtomicMtoDCache; @@ -146,6 +147,8 @@ module lsu logic DCacheStall; logic CacheableM; + logic CacheableMtoDCache; + logic SelPTW; logic CommittedMfromDCache; logic PendingInterruptMtoDCache; @@ -169,9 +172,10 @@ module lsu .HPTWReadPTE(HPTWReadPTE), .MMUReady(HPTWReady), .HPTWStall(HPTWStall), - .HPTWPAdr(HPTWPAdr), + .HPTWPAdrE(HPTWPAdrE), + .HPTWPAdrM(HPTWPAdrM), .HPTWTranslate(HPTWTranslate), - .HPTWRead(HPTWRead), + .HPTWReadM(HPTWReadM), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); @@ -183,15 +187,17 @@ module lsu .reset(reset), // HPTW connection .HPTWTranslate(HPTWTranslate), - .HPTWRead(HPTWRead), - .HPTWPAdr(HPTWPAdr), - .HPTWReadPTE(HPTWReadPTE), + .HPTWReadM(HPTWReadM), + .HPTWPAdrE(HPTWPAdrE), + .HPTWPAdrM(HPTWPAdrM), + //.HPTWReadPTE(HPTWReadPTE), .HPTWStall(HPTWStall), // CPU connection .MemRWM(MemRWM), .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), + .MemAdrE(MemAdrE), .CommittedM(CommittedM), .PendingInterruptM(PendingInterruptM), .StallW(StallW), @@ -204,14 +210,16 @@ module lsu .MemRWMtoDCache(MemRWMtoDCache), .Funct3MtoDCache(Funct3MtoDCache), .AtomicMtoDCache(AtomicMtoDCache), - .MemAdrMtoDCache(MemAdrMtoDCache), + .MemAdrMtoDCache(MemAdrMtoDCache), + .MemAdrEtoDCache(MemAdrEtoDCache), .StallWtoDCache(StallWtoDCache), .SquashSCWfromDCache(SquashSCWfromDCache), .DataMisalignedMfromDCache(DataMisalignedMfromDCache), .ReadDataWfromDCache(ReadDataWfromDCache), .CommittedMfromDCache(CommittedMfromDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache), - .DCacheStall(DCacheStall)); + .DCacheStall(DCacheStall), + .SelPTW(SelPTW)); mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) @@ -239,10 +247,10 @@ module lsu // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? - + assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; generate - if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache; - else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache; + if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache; + else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache; endgenerate; @@ -309,30 +317,27 @@ module lsu assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1]; assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0]; - // *** BUG - assign MemAdrEtoDCache = MemAdrE; // needs to be muxed in lsuarb. - - dcache dcache(.clk(clk), .reset(reset), .StallM(StallM), - .StallW(StallW), + .StallW(StallWtoDCache), .FlushM(FlushM), - .FlushW(FlushW), + .FlushW(FlushWtoDCache), .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), .AtomicM(AtomicMtoDCache), - .MemAdrE(MemAdrEtoDCache), // *** add to arb + .MemAdrE(MemAdrEtoDCache), .MemPAdrM(MemPAdrM), .WriteDataM(WriteDataM), .ReadDataW(ReadDataWfromDCache), + .ReadDataM(HPTWReadPTE), .DCacheStall(DCacheStall), .CommittedM(CommittedMfromDCache), .ExceptionM(ExceptionM), .PendingInterruptM(PendingInterruptMtoDCache), .DTLBMissM(DTLBMissM), - .CacheableM(CacheableM), + .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), // AHB connection diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 08024d0b8..3b3ad94f9 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -31,10 +31,11 @@ module lsuArb // from page table walker input logic HPTWTranslate, - input logic HPTWRead, - input logic [`XLEN-1:0] HPTWPAdr, + input logic HPTWReadM, + input logic [`XLEN-1:0] HPTWPAdrE, + input logic [`XLEN-1:0] HPTWPAdrM, // to page table walker. - output logic [`XLEN-1:0] HPTWReadPTE, + //output logic [`XLEN-1:0] HPTWReadPTE, output logic HPTWStall, // from CPU @@ -42,6 +43,7 @@ module lsuArb input logic [2:0] Funct3M, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] MemAdrE, input logic StallW, input logic PendingInterruptM, // to CPU @@ -57,8 +59,11 @@ module lsuArb output logic [2:0] Funct3MtoDCache, output logic [1:0] AtomicMtoDCache, output logic [`XLEN-1:0] MemAdrMtoDCache, + output logic [`XLEN-1:0] MemAdrEtoDCache, output logic StallWtoDCache, output logic PendingInterruptMtoDCache, + output logic SelPTW, + // from D Cache input logic CommittedMfromDCache, @@ -86,7 +91,6 @@ module lsuArb statetype CurrState, NextState; - logic SelPTW; logic [2:0] PTWSize; @@ -136,7 +140,7 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); - assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw @@ -144,7 +148,8 @@ module lsuArb mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache); assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; - assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM; + assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; + assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; @@ -152,7 +157,7 @@ module lsuArb // demux the inputs from LSU to walker or cpu's data port. assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux - assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux + //assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache; assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache; // *** need to rename DcacheStall and Datastall. diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 83d15f9b9..334ef2b26 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -59,9 +59,10 @@ module pagetablewalker input logic HPTWStall, // *** modify to send to LSU - output logic [`XLEN-1:0] HPTWPAdr, // this probalby should be `PA_BITS wide + output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide + output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide output logic HPTWTranslate, // *** rename to HPTWReq - output logic HPTWRead, + output logic HPTWReadM, // Faults @@ -70,52 +71,63 @@ module pagetablewalker output logic WalkerStorePageFaultM ); + logic HPTWReadE; + generate if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests logic [`XLEN-1:0] TranslationVAdrQ; - logic ITLBMissFQ, DTLBMissMQ; + logic ITLBMissFQ, DTLBMissMQ; - logic [`PPN_BITS-1:0] BasePageTablePPN; + logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`XLEN-1:0] TranslationVAdr; logic [`XLEN-1:0] SavedPTE, CurrentPTE; logic [`PA_BITS-1:0] TranslationPAdr; - logic [`PPN_BITS-1:0] CurrentPPN; - logic [`SVMODE_BITS-1:0] SvMode; - logic MemStore; + logic [`PPN_BITS-1:0] CurrentPPN; + logic [`SVMODE_BITS-1:0] SvMode; + logic MemStore; // PTE Control Bits - logic Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid; + logic Dirty, Accessed, Global, User, + Executable, Writable, Readable, Valid; // PTE descriptions - logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; + logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker logic [`XLEN-1:0] PageTableEntry; logic [1:0] PageType; - logic StartWalk; - logic EndWalk; + logic StartWalk; + logic EndWalk; typedef enum {LEVEL0_WDV, - LEVEL0, - LEVEL1_WDV, - LEVEL1, - LEVEL2_WDV, - LEVEL2, - LEVEL3_WDV, - LEVEL3, - LEAF, - IDLE, - START, - FAULT} statetype; + LEVEL0, + LEVEL1_WDV, + LEVEL1, + LEVEL2_WDV, + LEVEL2, + LEVEL3_WDV, + LEVEL3, + LEAF, + IDLE, + START, + FAULT} statetype; statetype WalkerState, NextWalkerState; - logic PRegEn; - logic SelDataTranslation; + logic PRegEn; + logic SelDataTranslation; + flop #(`XLEN) HPTWPAdrMReg(.clk(clk), + .d(HPTWPAdrE), + .q(HPTWPAdrM)); + + flop #(1) HPTWReadMReg(.clk(clk), + .d(HPTWReadE), + .q(HPTWReadM)); + + assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; @@ -128,35 +140,35 @@ module pagetablewalker flopenr #(`XLEN) TranslationVAdrReg(.clk(clk), - .reset(reset), - .en(StartWalk), - .d(TranslationVAdr), - .q(TranslationVAdrQ)); + .reset(reset), + .en(StartWalk), + .d(TranslationVAdr), + .q(TranslationVAdrQ)); flopenrc #(1) DTLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(DTLBMissM), - .q(DTLBMissMQ)); + .reset(reset), + .en(StartWalk | EndWalk), + .clear(EndWalk), + .d(DTLBMissM), + .q(DTLBMissMQ)); flopenrc #(1) ITLBMissMReg(.clk(clk), - .reset(reset), - .en(StartWalk | EndWalk), - .clear(EndWalk), - .d(ITLBMissF), - .q(ITLBMissFQ)); + .reset(reset), + .en(StartWalk | EndWalk), + .clear(EndWalk), + .d(ITLBMissF), + .q(ITLBMissFQ)); assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); assign EndWalk = WalkerState == LEAF || - //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == FAULT); + //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == FAULT); assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; //assign HPTWTranslate = DTLBMissM | ITLBMissF; @@ -177,385 +189,389 @@ module pagetablewalker assign PageTypeM = PageType; -// generate - if (`XLEN == 32) begin - logic [9:0] VPN1, VPN0; + // generate + if (`XLEN == 32) begin + logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - // State transition logic - always_comb begin - PRegEn = 1'b0; - TranslationPAdr = '0; - HPTWRead = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + // State transition logic + always_comb begin + PRegEn = 1'b0; + TranslationPAdr = '0; + HPTWReadE = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + case (WalkerState) + IDLE: begin + if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode + NextWalkerState = START; + end else begin + NextWalkerState = IDLE; + end + end - START: begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWRead = 1'b1; - end - - LEVEL1_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end - end - - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]}; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL0_WDV: begin + START: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + end + + LEVEL1_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_WDV; TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; + end + end + + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; + end + end + + LEVEL0: begin + if (ValidPTE & LeafPTE & ~AccessAlert) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end else begin + NextWalkerState = FAULT; + end + end + + LEAF: begin + NextWalkerState = IDLE; + end + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end + + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; + endcase end - LEVEL0: begin - if (ValidPTE & LeafPTE & ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdrQ[31:0]}; - end else begin - NextWalkerState = FAULT; - end - end + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[9:0]); + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; + - LEAF: begin - NextWalkerState = IDLE; - end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + + // Capture page table entry from data cache + // *** may need to delay reading this value until the next clock cycle. + // The clk to q latency of the SRAM in the data cache will be long. + // I cannot see directly using this value. This is no different than + // a load delay hazard. This will require rewriting the walker fsm. + // also need a new signal to save. Should be a mealy output of the fsm + // request followed by ~stall. + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = TranslationPAdr[31:0]; + + end else begin - // Default case should never happen, but is included for linter. - default: NextWalkerState = IDLE; - endcase - end + logic [8:0] VPN3, VPN2, VPN1, VPN0; - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - assign VPN1 = TranslationVAdrQ[31:22]; - assign VPN0 = TranslationVAdrQ[21:12]; + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || + WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - // Capture page table entry from data cache - // *** may need to delay reading this value until the next clock cycle. - // The clk to q latency of the SRAM in the data cache will be long. - // I cannot see directly using this value. This is no different than - // a load delay hazard. This will require rewriting the walker fsm. - // also need a new signal to save. Should be a mealy output of the fsm - // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || + // WalkerState == LEVEL2 || WalkerState == LEVEL1; + - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdr = TranslationPAdr[31:0]; + always_comb begin + PRegEn = 1'b0; + TranslationPAdr = '0; + HPTWReadE = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - end else begin - - logic [8:0] VPN3, VPN2, VPN1, VPN0; + case (WalkerState) + IDLE: begin + if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin + NextWalkerState = START; + end else begin + NextWalkerState = IDLE; + end + end - logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ - - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - - - always_comb begin - PRegEn = 1'b0; - TranslationPAdr = '0; - HPTWRead = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; - - case (WalkerState) - IDLE: begin - if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end - - START: begin - if (HPTWTranslate && SvMode == `SV48) begin - NextWalkerState = LEVEL3_WDV; - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWRead = 1'b1; - end else if (HPTWTranslate && SvMode == `SV39) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; - HPTWRead = 1'b1; - end else begin // *** should not get here - NextWalkerState = IDLE; - TranslationPAdr = '0; - end - end - - LEVEL3_WDV: begin + START: begin + if (HPTWTranslate && SvMode == `SV48) begin + NextWalkerState = LEVEL3_WDV; TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - if (HPTWStall) begin - NextWalkerState = LEVEL3_WDV; - end else begin - NextWalkerState = LEVEL3; - PRegEn = 1'b1; - end - end - - LEVEL3: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadTerapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - + HPTWReadE = 1'b1; + end else if (HPTWTranslate && SvMode == `SV39) begin + NextWalkerState = LEVEL2_WDV; + TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + end else begin // *** should not get here + NextWalkerState = IDLE; + TranslationPAdr = '0; end + end - LEVEL2_WDV: begin + LEVEL3_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL3_WDV; + end else begin + NextWalkerState = LEVEL3; + PRegEn = 1'b1; + end + end + + LEVEL3: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadTerapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL2_WDV; TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - //HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL2_WDV; - end else begin - NextWalkerState = LEVEL2; - PRegEn = 1'b1; - end - end - - LEVEL2: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadGigapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end - LEVEL1_WDV: begin + end + + LEVEL2_WDV: begin + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL2_WDV; + end else begin + NextWalkerState = LEVEL2; + PRegEn = 1'b1; + end + end + + LEVEL2: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadGigapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL1_WDV; TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - //HPTWRead = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWRead = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end + end - LEVEL0_WDV: begin + LEVEL1_WDV: begin + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_WDV; TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end + HPTWReadE = 1'b1; + end else begin + NextWalkerState = FAULT; end + end - LEVEL0: begin - if (ValidPTE && LeafPTE && ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdrQ[`PA_BITS-1:0]; - end else begin - NextWalkerState = FAULT; - end + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; end - - LEAF: begin - NextWalkerState = IDLE; + end + + LEVEL0: begin + if (ValidPTE && LeafPTE && ~AccessAlert) begin + NextWalkerState = LEAF; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end else begin + NextWalkerState = FAULT; end + end + + LEAF: begin + NextWalkerState = IDLE; + end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end - // Default case should never happen - default: begin - NextWalkerState = IDLE; - end + // Default case should never happen + default: begin + NextWalkerState = IDLE; + end - endcase - end - - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); - - assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - - assign VPN3 = TranslationVAdrQ[47:39]; - assign VPN2 = TranslationVAdrQ[38:30]; - assign VPN1 = TranslationVAdrQ[29:21]; - assign VPN0 = TranslationVAdrQ[20:12]; - - - // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + endcase end + + // A terapage is a level 3 leaf page. This page must have zero PPN[2], + // zero PPN[1], and zero PPN[0] + assign TerapageMisaligned = |(CurrentPPN[26:0]); + // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and + // zero PPN[0] + assign GigapageMisaligned = |(CurrentPPN[17:0]); + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[8:0]); + + assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; + + + // Capture page table entry from ahblite + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + end //endgenerate end else begin - assign HPTWPAdr = 0; + assign HPTWPAdrE = 0; assign HPTWTranslate = 0; - assign HPTWRead = 0; + assign HPTWReadE = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 56a019e83..b33b9ca40 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -546,7 +546,7 @@ string tests32f[] = '{ //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - if (`MEM_VIRTMEM) tests = {tests64periph, tests64mmu, tests}; + if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From f234875779cc36b2c2c524c493db333be550016d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jul 2021 23:08:07 -0500 Subject: [PATCH 35/47] dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. --- wally-pipelined/regression/wave.do | 131 +++++++++--------- wally-pipelined/src/cache/dcache.sv | 1 + .../testbench/testbench-imperas.sv | 4 +- 3 files changed, 68 insertions(+), 68 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 4205be707..915444831 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -12,40 +12,40 @@ add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrVali add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -group {Memory Stage} /testbench/InstrMName add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -321,14 +321,14 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -370,28 +370,27 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group ptwalker -divider data -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM -add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group ptwalker -divider data +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM +add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -424,7 +423,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 3} {21755 ns} 0} {{Cursor 4} {15501 ns} 0} +WaveRestoreCursors {{Cursor 4} {48736 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -440,4 +439,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {21597 ns} {21891 ns} +WaveRestoreZoom {48440 ns} {48880 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index b0ac33281..6e5c95d20 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -645,6 +645,7 @@ module dcache end STATE_CPU_BUSY : begin + CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; else NextState = STATE_READY; end diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b33b9ca40..b6a206023 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -539,14 +539,14 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64p,tests64i}; + tests = {tests64periph, tests64p,tests64i}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; + if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; - if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From c954fb510b9e367f5381ebb16ef3993ebe812772 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 10:16:16 -0500 Subject: [PATCH 36/47] Renamed DCacheStall to LSUStall in hart and hazard. Added missing logic in lsu. --- wally-pipelined/src/cache/dcache.sv | 2 +- wally-pipelined/src/hazard/hazard.sv | 4 ++-- wally-pipelined/src/lsu/lsu.sv | 1 + wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++-- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6e5c95d20..6c3ae803e 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -433,7 +433,7 @@ module dcache case (CurrState) STATE_READY: begin // TLB Miss - if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin NextState = STATE_PTW_READY; end // amo hit diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 331fc3267..e54802866 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -31,7 +31,7 @@ module hazard( // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, - input logic DCacheStall, ICacheStallF, + input logic LSUStall, ICacheStallF, input logic FPUStallD, FStallD, input logic DivBusyE,FDivBusyE, // Stall & flush outputs @@ -59,7 +59,7 @@ module hazard( assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; - assign StallWCause = DCacheStall | ICacheStallF; + assign StallWCause = LSUStall | ICacheStallF; assign StallF = StallFCause | StallD; assign StallD = StallDCause | StallE; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f8fa87a02..345e3514f 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -152,6 +152,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; + logic FlushWtoDCache; pagetablewalker pagetablewalker( diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index e0337bc39..b8d7af579 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -126,7 +126,7 @@ module wallypipelinedhart // IMem stalls logic ICacheStallF; - logic DCacheStall; + logic LSUStall; @@ -233,7 +233,7 @@ module wallypipelinedhart .DTLBHitM(DTLBHitM), // not connected remove - .LSUStall(DCacheStall)); // change to DCacheStall + .LSUStall(LSUStall)); // change to LSUStall From c39a2282661012497e96d110b8fc3889dd6ec4a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:00:42 -0500 Subject: [PATCH 37/47] Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. --- wally-pipelined/src/cache/dcache.sv | 10 +++++++++- wally-pipelined/src/mmu/pagetablewalker.sv | 10 +--------- wally-pipelined/testbench/testbench-imperas.sv | 2 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6c3ae803e..d6915666d 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -433,7 +433,14 @@ module dcache case (CurrState) STATE_READY: begin // TLB Miss - if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin + // the LSU arbiter has not yet selected the PTW. + // The CPU needs to be stalled until that happens. + // If we set DCacheStall for 1 cycle before going to + // PTW ready the CPU will stall. + // The page table walker asserts it's control 1 cycle + // after the TLBs miss. + DCacheStall = 1'b1; NextState = STATE_PTW_READY; end // amo hit @@ -580,6 +587,7 @@ module dcache end STATE_PTW_READY: begin + // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. if(DTLBWriteM) begin diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 334ef2b26..5beddf487 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -77,7 +77,6 @@ module pagetablewalker if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests - logic [`XLEN-1:0] TranslationVAdrQ; logic ITLBMissFQ, DTLBMissMQ; logic [`PPN_BITS-1:0] BasePageTablePPN; @@ -138,13 +137,6 @@ module pagetablewalker assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr assign SelDataTranslation = DTLBMissMQ | DTLBMissM; - flopenr #(`XLEN) - TranslationVAdrReg(.clk(clk), - .reset(reset), - .en(StartWalk), - .d(TranslationVAdr), - .q(TranslationVAdrQ)); - flopenrc #(1) DTLBMissMReg(.clk(clk), .reset(reset), @@ -170,7 +162,7 @@ module pagetablewalker (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); - assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; + assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); //assign HPTWTranslate = DTLBMissM | ITLBMissF; // unswizzle PTE bits diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index b6a206023..418ddc424 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -543,10 +543,10 @@ string tests32f[] = '{ if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`MEM_VIRTMEM) tests = {tests, tests64mmu}; //if (`A_SUPPORTED) tests = {tests, tests64a}; if (`F_SUPPORTED) tests = {tests64f, tests}; if (`D_SUPPORTED) tests = {tests64d, tests}; + if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; end else begin // RV32 From 5fb5ac3d5abdbb91805699a2e61016aa2b62f95d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:04:49 -0500 Subject: [PATCH 38/47] Updated wave file. --- wally-pipelined/regression/wave.do | 177 +++++++++++++---------------- 1 file changed, 82 insertions(+), 95 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 915444831..697bc5679 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -8,33 +8,34 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -expand -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD @@ -113,7 +114,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -126,19 +127,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu -add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu -divider internals +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -240,12 +240,9 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrE -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrE -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HPTWPAdrM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrMtoDCache -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrEtoDCache +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -254,22 +251,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM @@ -298,7 +295,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW @@ -308,10 +304,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed @@ -321,14 +321,24 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWTranslate +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM +add wave -noupdate -expand -group lsu -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -group ptwalker -divider data +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -370,27 +380,6 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -group ptwalker -divider data -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/MemAdrM -add wave -noupdate -group {LSU ARB} /testbench/dut/hart/lsu/MemPAdrM -add wave -noupdate -group {LSU ARB} -expand -group lsu -color Gold /testbench/dut/hart/lsu/arbiter/CurrState -add wave -noupdate -group {LSU ARB} -expand -group lsu -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -group {LSU ARB} -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -420,10 +409,8 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA -add wave -noupdate /testbench/dut/hart/lsu/dcache/OFFSETLEN -add wave -noupdate /testbench/dut/hart/lsu/dcache/INDEXLEN TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {48736 ns} 0} +WaveRestoreCursors {{Cursor 4} {25841 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -439,4 +426,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {48440 ns} {48880 ns} +WaveRestoreZoom {25409 ns} {26369 ns} From 96aa106852b19295935a26feb73aac8690891500 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 11:56:35 -0500 Subject: [PATCH 39/47] Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. --- wally-pipelined/regression/wave.do | 177 +++++++++--------- wally-pipelined/src/ifu/ifu.sv | 4 - wally-pipelined/src/lsu/lsu.sv | 2 +- wally-pipelined/src/mmu/pmachecker.sv | 2 +- .../testbench/testbench-imperas.sv | 2 +- 5 files changed, 95 insertions(+), 92 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 697bc5679..6c4b1d79a 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -29,14 +29,15 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -243,81 +244,87 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM @@ -410,7 +417,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {25841 ns} 0} +WaveRestoreCursors {{Cursor 4} {10516 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -426,4 +433,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {25409 ns} {26369 ns} +WaveRestoreZoom {10473 ns} {10589 ns} diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index ff2545b7a..a0728a1ad 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -101,10 +101,6 @@ module ifu ( logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; - logic PMALoadAccessFaultM, PMAStoreAccessFaultM; - logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage - // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. - logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. generate diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 9bb991efe..0f38b8292 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -219,7 +219,7 @@ module lsu mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) - dmmu(.VirtualAddress(MemAdrMtoDCache), + dmmu(.Address(MemAdrMtoDCache), .Size(Funct3MtoDCache[1:0]), .PTE(PageTableEntryM), .PageTypeWriteVal(PageTypeM), diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index 86abcb3f6..a95252f3b 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -61,7 +61,7 @@ module pmachecker ( assign AtomicAllowed = SelRegions[4]; // Detect access faults - assign PMAAccessFault = (~|SelRegions) & AccessRWX; + assign PMAAccessFault = SelRegions[6] & AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault; assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 2d41efd9f..67140aa0c 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -535,7 +535,7 @@ string tests32f[] = '{ else if (TESTSPRIV) tests = tests64p; else begin - tests = {tests64periph, tests64p,tests64i}; + tests = {tests64p,tests64i, tests64periph}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; From ba5bb12e2638ae971a5749eefaddedc569708518 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Thu, 15 Jul 2021 18:30:29 -0400 Subject: [PATCH 41/47] Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. --- wally-pipelined/src/cache/dcache.sv | 63 ++++++++++++++++++++-- wally-pipelined/src/mmu/pagetablewalker.sv | 40 +++++++++----- 2 files changed, 86 insertions(+), 17 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index d6915666d..dc66043c1 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -162,7 +162,9 @@ module dcache STATE_PTW_READ_MISS_FETCH_DONE, STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, STATE_PTW_READ_MISS_READ_WORD, - STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_PTW_READ_MISS_READ_WORD_DELAY, + STATE_PTW_ACCESS_AFTER_WALK, + STATE_PTW_UPDATE_TLB, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, @@ -590,8 +592,8 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if(DTLBWriteM) begin - NextState = STATE_READY; + if (DTLBWriteM) begin + NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin @@ -648,10 +650,63 @@ module dcache STATE_PTW_READ_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_PTW_READY; + NextState = STATE_PTW_READY; CommittedM = 1'b1; end + + STATE_PTW_ACCESS_AFTER_WALK: begin + SelAdrM = 1'b1; + // amo hit + if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + NextState = STATE_AMO_UPDATE; + DCacheStall = 1'b1; + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_AMO_UPDATE; + end + // read hit valid cached + else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + DCacheStall = 1'b0; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end + // write hit valid cached + else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin + DCacheStall = 1'b0; + SRAMWordWriteEnableM = 1'b1; + SetDirtyM = 1'b1; + + if(StallW) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + end + // read or write miss valid cached + else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin + NextState = STATE_MISS_FETCH_WDV; + CntReset = 1'b1; + DCacheStall = 1'b1; + end + // uncached write + else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_WRITE; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBWrite = 1'b1; + end + // uncached read + else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin + NextState = STATE_UNCACHED_READ; + CntReset = 1'b1; + DCacheStall = 1'b1; + AHBRead = 1'b1; + end + // fault + else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin + NextState = STATE_READY; + end + else NextState = STATE_READY; + end + STATE_CPU_BUSY : begin CommittedM = 1'b1; if(StallW) NextState = STATE_CPU_BUSY; diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 5beddf487..282d5bf25 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -86,6 +86,7 @@ module pagetablewalker logic [`PPN_BITS-1:0] CurrentPPN; logic [`SVMODE_BITS-1:0] SvMode; logic MemStore; + logic DTLBWriteM_d; // PTE Control Bits logic Dirty, Accessed, Global, User, @@ -122,6 +123,18 @@ module pagetablewalker .d(HPTWPAdrE), .q(HPTWPAdrM)); + flop #(2) PageTypeReg(.clk(clk), + .d(PageType), + .q(PageTypeM)); + + flop #(`XLEN) PageTableEntryReg(.clk(clk), + .d(PageTableEntry), + .q(PageTableEntryM)); + + flop #(1) DTLBWriteReg(.clk(clk), + .d(DTLBWriteM_d), + .q(DTLBWriteM)); + flop #(1) HPTWReadMReg(.clk(clk), .d(HPTWReadE), .q(HPTWReadM)); @@ -157,9 +170,9 @@ module pagetablewalker assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); assign EndWalk = WalkerState == LEAF || //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || + //(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || (WalkerState == FAULT); assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); @@ -176,9 +189,9 @@ module pagetablewalker // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; - assign PageTableEntryM = PageTableEntry; + //assign PageTableEntryM = PageTableEntry; assign PageTypeF = PageType; - assign PageTypeM = PageType; + //assign PageTypeM = PageType; // generate @@ -198,7 +211,7 @@ module pagetablewalker HPTWReadE = 1'b0; PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; + DTLBWriteM_d = '0; ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; @@ -240,7 +253,7 @@ module pagetablewalker NextWalkerState = LEAF; PageTableEntry = CurrentPTE; PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end @@ -270,7 +283,7 @@ module pagetablewalker NextWalkerState = LEAF; PageTableEntry = CurrentPTE; PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; end else begin @@ -281,6 +294,7 @@ module pagetablewalker LEAF: begin NextWalkerState = IDLE; end + FAULT: begin NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; @@ -342,7 +356,7 @@ module pagetablewalker HPTWReadE = 1'b0; PageTableEntry = '0; PageType = '0; - DTLBWriteM = '0; + DTLBWriteM_d = '0; ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; @@ -395,7 +409,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -432,7 +446,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end @@ -469,7 +483,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; @@ -502,7 +516,7 @@ module pagetablewalker PageType = (WalkerState == LEVEL3) ? 2'b11 : ((WalkerState == LEVEL2) ? 2'b10 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; + DTLBWriteM_d = DTLBMissMQ; ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; end else begin From 5ca7dc619ce4bd5cf9f20582e63578083cfad9c2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 11:12:57 -0500 Subject: [PATCH 44/47] Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. --- wally-pipelined/src/cache/dcache.sv | 67 +- wally-pipelined/src/lsu/lsu.sv | 13 +- wally-pipelined/src/lsu/lsuArb.sv | 65 +- wally-pipelined/src/mmu/pagetablewalker.sv | 778 ++++++++++----------- 4 files changed, 399 insertions(+), 524 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index dc66043c1..e5ef5f352 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -43,7 +43,7 @@ module dcache input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataW, - output logic [`XLEN-1:0] ReadDataM, + output logic [`XLEN-1:0] ReadDataM, output logic DCacheStall, output logic CommittedM, @@ -53,6 +53,7 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, + input logic SelPTW, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -443,7 +444,13 @@ module dcache // The page table walker asserts it's control 1 cycle // after the TLBs miss. DCacheStall = 1'b1; + NextState = STATE_READY; + end + else if(SelPTW) begin + // Now we have activated the ptw. + // Do not assert Stall as we are now directing the stall the ptw. NextState = STATE_PTW_READY; + CommittedM = 1'b1; end // amo hit else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin @@ -592,7 +599,7 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if (DTLBWriteM) begin + if (~SelPTW) begin NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached @@ -650,61 +657,15 @@ module dcache STATE_PTW_READ_MISS_READ_WORD_DELAY: begin SelAdrM = 1'b1; - NextState = STATE_PTW_READY; + NextState = STATE_PTW_READY; CommittedM = 1'b1; end STATE_PTW_ACCESS_AFTER_WALK: begin - SelAdrM = 1'b1; - // amo hit - if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - NextState = STATE_AMO_UPDATE; - DCacheStall = 1'b1; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_AMO_UPDATE; - end - // read hit valid cached - else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - end - // write hit valid cached - else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - SRAMWordWriteEnableM = 1'b1; - SetDirtyM = 1'b1; - - if(StallW) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - end - // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - end - // uncached write - else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin - NextState = STATE_UNCACHED_WRITE; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBWrite = 1'b1; - end - // uncached read - else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin - NextState = STATE_UNCACHED_READ; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBRead = 1'b1; - end - // fault - else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin - NextState = STATE_READY; - end - else NextState = STATE_READY; + DCacheStall = 1'b1; + SelAdrM = 1'b1; + CommittedM = 1'b1; + NextState = STATE_READY; end STATE_CPU_BUSY : begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 0f38b8292..56d0cb9cc 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -126,7 +126,6 @@ module lsu logic HPTWStall; logic [`XLEN-1:0] HPTWPAdrE; logic [`XLEN-1:0] HPTWPAdrM; - logic HPTWTranslate; logic HPTWReadM; logic [1:0] MemRWMtoDCache; logic [2:0] Funct3MtoDCache; @@ -170,8 +169,8 @@ module lsu .HPTWStall(HPTWStall), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), - .HPTWTranslate(HPTWTranslate), .HPTWReadM(HPTWReadM), + .SelPTW(SelPTW), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); @@ -182,7 +181,7 @@ module lsu lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection - .HPTWTranslate(HPTWTranslate), + .SelPTW(SelPTW), .HPTWReadM(HPTWReadM), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), @@ -214,8 +213,9 @@ module lsu .ReadDataWfromDCache(ReadDataWfromDCache), .CommittedMfromDCache(CommittedMfromDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache), - .DCacheStall(DCacheStall), - .SelPTW(SelPTW)); + .DCacheStall(DCacheStall)); + + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) @@ -243,7 +243,9 @@ module lsu // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + // *** BUG, this is most likely wrong assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM; + generate if (`XLEN == 32) assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b010 : Funct3MtoDCache; else assign DCtoAHBSizeM = CacheableMtoDCache ? 3'b011 : Funct3MtoDCache; @@ -335,6 +337,7 @@ module lsu .DTLBMissM(DTLBMissM), .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), + .SelPTW(SelPTW), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 3b3ad94f9..4feec6557 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -30,7 +30,7 @@ module lsuArb (input logic clk, reset, // from page table walker - input logic HPTWTranslate, + input logic SelPTW, input logic HPTWReadM, input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrM, @@ -62,7 +62,6 @@ module lsuArb output logic [`XLEN-1:0] MemAdrEtoDCache, output logic StallWtoDCache, output logic PendingInterruptMtoDCache, - output logic SelPTW, // from D Cache @@ -73,73 +72,11 @@ module lsuArb input logic DCacheStall ); - - // HPTWTranslate is the request for memory by the page table walker. When - // this is high the page table walker gains priority over the CPU's data - // input. Note the ptw only makes a request after an instruction or data - // tlb miss. It is entirely possible the dcache is currently processing - // a data cache miss when an instruction tlb miss occurs. If an instruction - // in the E stage causes a d cache miss, the d cache will immediately start - // processing the request. Simultaneously the ITLB misses. By the time - // the TLB miss causes the page table walker to issue the first request - // to data memory the d cache is already busy. We can interlock by - // leveraging Stall as a d cache busy. We will need an FSM to handle this. - typedef enum{StateReady, - StatePTWPending, - StatePTWActive} statetype; - - - statetype CurrState, NextState; logic [2:0] PTWSize; - - flopenl #(.TYPE(statetype)) StateReg(.clk(clk), - .load(reset), - .en(1'b1), - .d(NextState), - .val(StateReady), - .q(CurrState)); - - always_comb begin - case(CurrState) - StateReady: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - StatePTWActive: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - default: NextState = StateReady; - endcase - end - -/* -----\/----- EXCLUDED -----\/----- - - always_comb begin - case(CurrState) - StateReady: - /-* -----\/----- EXCLUDED -----\/----- - if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else - -----/\----- EXCLUDED -----/\----- *-/ - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - StatePTWPending: - if (HPTWTranslate & ~DataStall) NextState = StatePTWActive; - else if (HPTWTranslate & DataStall) NextState = StatePTWPending; - else NextState = StateReady; - StatePTWActive: - if (HPTWTranslate) NextState = StatePTWActive; - else NextState = StateReady; - default: NextState = StateReady; - endcase - end - - -----/\----- EXCLUDED -----/\----- */ - // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. - assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; generate diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 282d5bf25..8948badfa 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -9,21 +9,21 @@ // // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) -// +// // A component of the Wally configurable RISC-V project. -// +// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software // is furnished to do so, subject to the following conditions: // // The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// @@ -37,107 +37,94 @@ module pagetablewalker ( // Control signals - input logic clk, reset, + input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // Signals from TLBs (addresses to translate) input logic [`XLEN-1:0] PCF, MemAdrM, - input logic ITLBMissF, DTLBMissM, - input logic [1:0] MemRWM, + input logic ITLBMissF, DTLBMissM, + input logic [1:0] MemRWM, // Outputs to the TLBs (PTEs to write) output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM, - output logic [1:0] PageTypeF, PageTypeM, - output logic ITLBWriteF, DTLBWriteM, - - + output logic [1:0] PageTypeF, PageTypeM, + output logic ITLBWriteF, DTLBWriteM, + output logic SelPTW, // *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU input logic [`XLEN-1:0] HPTWReadPTE, - input logic MMUReady, - input logic HPTWStall, + input logic MMUReady, + input logic HPTWStall, // *** modify to send to LSU output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide - output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide - output logic HPTWTranslate, // *** rename to HPTWReq - output logic HPTWReadM, + output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide + output logic HPTWReadM, // Faults - output logic WalkerInstrPageFaultF, - output logic WalkerLoadPageFaultM, - output logic WalkerStorePageFaultM + output logic WalkerInstrPageFaultF, + output logic WalkerLoadPageFaultM, + output logic WalkerStorePageFaultM ); - logic HPTWReadE; + logic HPTWReadE; generate if (`MEM_VIRTMEM) begin // Internal signals // register TLBs translation miss requests - logic ITLBMissFQ, DTLBMissMQ; - - logic [`PPN_BITS-1:0] BasePageTablePPN; - logic [`XLEN-1:0] TranslationVAdr; - logic [`XLEN-1:0] SavedPTE, CurrentPTE; - logic [`PA_BITS-1:0] TranslationPAdr; - logic [`PPN_BITS-1:0] CurrentPPN; - logic [`SVMODE_BITS-1:0] SvMode; - logic MemStore; - logic DTLBWriteM_d; + logic ITLBMissFQ, DTLBMissMQ; + + logic [`PPN_BITS-1:0] BasePageTablePPN; + logic [`XLEN-1:0] TranslationVAdr; + logic [`XLEN-1:0] SavedPTE, CurrentPTE; + logic [`PA_BITS-1:0] TranslationPAdr; + logic [`PPN_BITS-1:0] CurrentPPN; + logic [`SVMODE_BITS-1:0] SvMode; + logic MemStore; // PTE Control Bits - logic Dirty, Accessed, Global, User, + logic Dirty, Accessed, Global, User, Executable, Writable, Readable, Valid; // PTE descriptions - logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; + logic ValidPTE, AccessAlert, MegapageMisaligned, BadMegapage, LeafPTE; // Outputs of walker - logic [`XLEN-1:0] PageTableEntry; - logic [1:0] PageType; - logic StartWalk; - logic EndWalk; - - typedef enum {LEVEL0_WDV, + logic [`XLEN-1:0] PageTableEntry; + logic [1:0] PageType; + logic StartWalk; + logic EndWalk; + + typedef enum {LEVEL0_SET_ADRE, + LEVEL0_WDV, LEVEL0, + LEVEL1_SET_ADRE, LEVEL1_WDV, LEVEL1, + LEVEL2_SET_ADRE, LEVEL2_WDV, LEVEL2, + LEVEL3_SET_ADRE, LEVEL3_WDV, LEVEL3, LEAF, IDLE, - START, FAULT} statetype; - statetype WalkerState, NextWalkerState; + statetype WalkerState, NextWalkerState, PreviousWalkerState; - logic PRegEn; - logic SelDataTranslation; - - - flop #(`XLEN) HPTWPAdrMReg(.clk(clk), - .d(HPTWPAdrE), - .q(HPTWPAdrM)); + logic PRegEn; + logic SelDataTranslation; + logic AnyTLBMissM; - flop #(2) PageTypeReg(.clk(clk), - .d(PageType), - .q(PageTypeM)); - flop #(`XLEN) PageTableEntryReg(.clk(clk), - .d(PageTableEntry), - .q(PageTableEntryM)); - - flop #(1) DTLBWriteReg(.clk(clk), - .d(DTLBWriteM_d), - .q(DTLBWriteM)); - flop #(1) HPTWReadMReg(.clk(clk), - .d(HPTWReadE), - .q(HPTWReadM)); + flop #(`XLEN) HPTWPAdrMReg(.clk(clk), + .d(HPTWPAdrE), + .q(HPTWPAdrM)); + assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; @@ -147,7 +134,7 @@ module pagetablewalker assign MemStore = MemRWM[0]; // Prefer data address translations over instruction address translations - assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr + assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; assign SelDataTranslation = DTLBMissMQ | DTLBMissM; flopenrc #(1) @@ -157,7 +144,7 @@ module pagetablewalker .clear(EndWalk), .d(DTLBMissM), .q(DTLBMissMQ)); - + flopenrc #(1) ITLBMissMReg(.clk(clk), .reset(reset), @@ -165,22 +152,16 @@ module pagetablewalker .clear(EndWalk), .d(ITLBMissF), .q(ITLBMissFQ)); - - assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); - assign EndWalk = WalkerState == LEAF || - //(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || - //(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || - (WalkerState == FAULT); - - assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ); - //assign HPTWTranslate = DTLBMissM | ITLBMissF; + + assign AnyTLBMissM = DTLBMissM | ITLBMissF; + + assign StartWalk = WalkerState == IDLE & AnyTLBMissM; + assign EndWalk = WalkerState == LEAF || WalkerState == FAULT; // unswizzle PTE bits assign {Dirty, Accessed, Global, User, - Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; + Executable, Writable, Readable, Valid} = CurrentPTE[7:0]; // Assign PTE descriptors common across all XLEN values assign LeafPTE = Executable | Writable | Readable; @@ -189,398 +170,391 @@ module pagetablewalker // Assign specific outputs to general outputs assign PageTableEntryF = PageTableEntry; - //assign PageTableEntryM = PageTableEntry; + assign PageTableEntryM = PageTableEntry; assign PageTypeF = PageType; - //assign PageTypeM = PageType; + assign PageTypeM = PageType; // generate if (`XLEN == 32) begin - logic [9:0] VPN1, VPN0; + logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ - // State transition logic - always_comb begin + // State transition logic + always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; HPTWReadE = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM_d = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && SvMode == `SV32) begin // *** Added SvMode - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - START: begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; - end - - LEVEL1_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; + SelPTW = 1'b1; + + case (WalkerState) + IDLE: begin + SelPTW = 1'b0; + if (AnyTLBMissM & SvMode == `SV32) begin + NextWalkerState = LEVEL1_SET_ADRE; + end else begin + NextWalkerState = IDLE; + end + end + + LEVEL1_SET_ADRE: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + end + + LEVEL1_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; PRegEn = 1'b1; - end - end - - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin + end + end + + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end - - LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; - if (HPTWStall) begin + end else begin + NextWalkerState = FAULT; + end + end + + LEVEL0_SET_ADRE: begin + NextWalkerState = LEVEL0_WDV; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + end + + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + HPTWReadE = 1'b1; + if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; - end else begin + end else begin NextWalkerState = LEVEL0; PRegEn = 1'b1; - end - end + end + end - LEVEL0: begin - if (ValidPTE & LeafPTE & ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; - end else begin - NextWalkerState = FAULT; - end - end - - LEAF: begin - NextWalkerState = IDLE; - end + LEVEL0: begin + if (ValidPTE & LeafPTE & ~AccessAlert) begin + NextWalkerState = LEAF; + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end else begin + NextWalkerState = FAULT; + end + end - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end - - // Default case should never happen, but is included for linter. - default: NextWalkerState = IDLE; - endcase - end + LEAF: begin + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; + end - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[9:0]); - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end - assign VPN1 = TranslationVAdr[31:22]; - assign VPN0 = TranslationVAdr[21:12]; + // Default case should never happen, but is included for linter. + default: NextWalkerState = IDLE; + endcase + end - + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[9:0]); + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - // Capture page table entry from data cache - // *** may need to delay reading this value until the next clock cycle. - // The clk to q latency of the SRAM in the data cache will be long. - // I cannot see directly using this value. This is no different than - // a load delay hazard. This will require rewriting the walker fsm. - // also need a new signal to save. Should be a mealy output of the fsm - // request followed by ~stall. - flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + assign VPN1 = TranslationVAdr[31:22]; + assign VPN0 = TranslationVAdr[21:12]; - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdrE = TranslationPAdr[31:0]; + + + // Capture page table entry from data cache + // *** may need to delay reading this value until the next clock cycle. + // The clk to q latency of the SRAM in the data cache will be long. + // I cannot see directly using this value. This is no different than + // a load delay hazard. This will require rewriting the walker fsm. + // also need a new signal to save. Should be a mealy output of the fsm + // request followed by ~stall. + flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + + // Assign outputs to ahblite + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = TranslationPAdr[31:0]; end else begin - - logic [8:0] VPN3, VPN2, VPN1, VPN0; - logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; + logic [8:0] VPN3, VPN2, VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ + flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - + /* -----\/----- EXCLUDED -----\/----- + assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || + WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; + -----/\----- EXCLUDED -----/\----- */ - always_comb begin + //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || + // WalkerState == LEVEL2 || WalkerState == LEVEL1; + + + always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; HPTWReadE = 1'b0; - PageTableEntry = '0; - PageType = '0; - DTLBWriteM_d = '0; - ITLBWriteF = '0; - - WalkerInstrPageFaultF = 1'b0; - WalkerLoadPageFaultM = 1'b0; - WalkerStorePageFaultM = 1'b0; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; - case (WalkerState) - IDLE: begin - if (HPTWTranslate && (SvMode == `SV48 || SvMode == `SV39)) begin - NextWalkerState = START; - end else begin - NextWalkerState = IDLE; - end - end + WalkerInstrPageFaultF = 1'b0; + WalkerLoadPageFaultM = 1'b0; + WalkerStorePageFaultM = 1'b0; - START: begin - if (HPTWTranslate && SvMode == `SV48) begin + SelPTW = 1'b1; + + case (WalkerState) + IDLE: begin + SelPTW = 1'b0; + if (AnyTLBMissM & SvMode == `SV48) begin + NextWalkerState = LEVEL3_SET_ADRE; + end else if (AnyTLBMissM & SvMode == `SV39) begin + NextWalkerState = LEVEL2_SET_ADRE; + end else begin + NextWalkerState = IDLE; + end + end + + LEVEL3_SET_ADRE: begin + NextWalkerState = LEVEL3_WDV; + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + end + + LEVEL3_WDV: begin + TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin NextWalkerState = LEVEL3_WDV; - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; - end else if (HPTWTranslate && SvMode == `SV39) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - end else begin // *** should not get here - NextWalkerState = IDLE; - TranslationPAdr = '0; - end - end - - LEVEL3_WDV: begin - TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL3_WDV; - end else begin + end else begin NextWalkerState = LEVEL3; PRegEn = 1'b1; - end - end - - LEVEL3: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadTerapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL2_WDV; - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end + end + end - end + LEVEL3: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadTerapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL2_SET_ADRE; + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - LEVEL2_WDV: begin - TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL2_WDV; - end else begin - NextWalkerState = LEVEL2; - PRegEn = 1'b1; - end - end - - LEVEL2: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadGigapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL1_WDV; - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end + LEVEL2_SET_ADRE: begin + NextWalkerState = LEVEL2_WDV; + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + end - end + LEVEL2_WDV: begin + TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL2_WDV; + end else begin + NextWalkerState = LEVEL2; + PRegEn = 1'b1; + end + end - LEVEL1_WDV: begin - TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL1_WDV; - end else begin - NextWalkerState = LEVEL1; - PRegEn = 1'b1; - end - end + LEVEL2: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadGigapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL1_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - LEVEL1: begin - // *** According to the architecture, we should - // fault upon finding a superpage that is misaligned or has 0 - // access bit. The following commented line of code is - // supposed to perform that check. However, it is untested. - if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - - end - // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. - else if (ValidPTE && ~LeafPTE) begin - NextWalkerState = LEVEL0_WDV; - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; - end else begin - NextWalkerState = FAULT; - end - end + LEVEL1_SET_ADRE: begin + NextWalkerState = LEVEL1_WDV; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + end - LEVEL0_WDV: begin - TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; - if (HPTWStall) begin - NextWalkerState = LEVEL0_WDV; - end else begin - NextWalkerState = LEVEL0; - PRegEn = 1'b1; - end - end + LEVEL1_WDV: begin + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL1_WDV; + end else begin + NextWalkerState = LEVEL1; + PRegEn = 1'b1; + end + end - LEVEL0: begin - if (ValidPTE && LeafPTE && ~AccessAlert) begin - NextWalkerState = LEAF; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM_d = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions - TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - end else begin - NextWalkerState = FAULT; - end - end - - LEAF: begin - NextWalkerState = IDLE; - end + LEVEL1: begin + // *** According to the architecture, we should + // fault upon finding a superpage that is misaligned or has 0 + // access bit. The following commented line of code is + // supposed to perform that check. However, it is untested. + if (ValidPTE && LeafPTE && ~BadMegapage) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; - FAULT: begin - NextWalkerState = IDLE; - WalkerInstrPageFaultF = ~DTLBMissMQ; - WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; - WalkerStorePageFaultM = DTLBMissMQ && MemStore; - end + end + // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. + else if (ValidPTE && ~LeafPTE) begin + NextWalkerState = LEVEL0_SET_ADRE; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + end else begin + NextWalkerState = FAULT; + end + end - // Default case should never happen - default: begin - NextWalkerState = IDLE; - end + LEVEL0_SET_ADRE: begin + NextWalkerState = LEVEL0_WDV; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + end - endcase - end + LEVEL0_WDV: begin + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + HPTWReadE = 1'b1; + if (HPTWStall) begin + NextWalkerState = LEVEL0_WDV; + end else begin + NextWalkerState = LEVEL0; + PRegEn = 1'b1; + end + end - // A terapage is a level 3 leaf page. This page must have zero PPN[2], - // zero PPN[1], and zero PPN[0] - assign TerapageMisaligned = |(CurrentPPN[26:0]); - // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and - // zero PPN[0] - assign GigapageMisaligned = |(CurrentPPN[17:0]); - // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. - assign MegapageMisaligned = |(CurrentPPN[8:0]); + LEVEL0: begin + if (ValidPTE && LeafPTE && ~AccessAlert) begin + NextWalkerState = LEAF; + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + end else begin + NextWalkerState = FAULT; + end + end - assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme - assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + LEAF: begin + PageTableEntry = CurrentPTE; + PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? + ((PreviousWalkerState == LEVEL2) ? 2'b10 : + ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + TranslationPAdr = TranslationVAdr[`PA_BITS-1:0]; + NextWalkerState = IDLE; + end - assign VPN3 = TranslationVAdr[47:39]; - assign VPN2 = TranslationVAdr[38:30]; - assign VPN1 = TranslationVAdr[29:21]; - assign VPN0 = TranslationVAdr[20:12]; + FAULT: begin + NextWalkerState = IDLE; + WalkerInstrPageFaultF = ~DTLBMissMQ; + WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; + WalkerStorePageFaultM = DTLBMissMQ && MemStore; + end + + // Default case should never happen + default: begin + NextWalkerState = IDLE; + end + + endcase + end + + // A terapage is a level 3 leaf page. This page must have zero PPN[2], + // zero PPN[1], and zero PPN[0] + assign TerapageMisaligned = |(CurrentPPN[26:0]); + // A gigapage is a Level 2 leaf page. This page must have zero PPN[1] and + // zero PPN[0] + assign GigapageMisaligned = |(CurrentPPN[17:0]); + // A megapage is a Level 1 leaf page. This page must have zero PPN[0]. + assign MegapageMisaligned = |(CurrentPPN[8:0]); + + assign BadTerapage = TerapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadGigapage = GigapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + assign BadMegapage = MegapageMisaligned || AccessAlert; // *** Implement better access/dirty scheme + + assign VPN3 = TranslationVAdr[47:39]; + assign VPN2 = TranslationVAdr[38:30]; + assign VPN1 = TranslationVAdr[29:21]; + assign VPN0 = TranslationVAdr[20:12]; - // Capture page table entry from ahblite - flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); - //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); - assign CurrentPTE = SavedPTE; - assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; + // Capture page table entry from ahblite + flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE); + //mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE); + assign CurrentPTE = SavedPTE; + assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10]; - // Assign outputs to ahblite - // *** Currently truncate address to 32 bits. This must be changed if - // we support larger physical address spaces - assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; + // *** Major issue. We need the full virtual address here. + // When the TLB's are update it use use the orignal address + // *** Currently truncate address to 32 bits. This must be changed if + // we support larger physical address spaces + assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; end //endgenerate end else begin assign HPTWPAdrE = 0; - assign HPTWTranslate = 0; assign HPTWReadE = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; + assign SelPTW = 0; end endgenerate From d3715acf2d516d6a3bf3929c3187739b180338a6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:22:13 -0500 Subject: [PATCH 45/47] Fixed walker fault interaction with dcache. --- wally-pipelined/regression/wave.do | 231 +++++++++++---------- wally-pipelined/src/cache/dcache.sv | 16 +- wally-pipelined/src/lsu/lsu.sv | 8 +- wally-pipelined/src/lsu/lsuArb.sv | 4 +- wally-pipelined/src/mmu/mmu.sv | 7 +- wally-pipelined/src/mmu/pagetablewalker.sv | 33 +-- 6 files changed, 163 insertions(+), 136 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 6c4b1d79a..73b6f9fb9 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -13,19 +13,19 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM @@ -241,81 +241,83 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/HPTWTranslate -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/CurrState add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/SVMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -expand -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable @@ -325,27 +327,36 @@ add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWTranslate -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadM -add wave -noupdate -expand -group lsu -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -group ptwalker -divider data -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -417,7 +428,7 @@ add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {10516 ns} 0} +WaveRestoreCursors {{Cursor 4} {29656 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -433,4 +444,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {10473 ns} {10589 ns} +WaveRestoreZoom {29565 ns} {29803 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index e5ef5f352..85a341584 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -53,7 +53,9 @@ module dcache input logic DTLBMissM, input logic CacheableM, input logic DTLBWriteM, - input logic SelPTW, + // from ptw + input logic SelPTW, + input logic WalkerPageFaultM, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic AHBRead, @@ -164,8 +166,8 @@ module dcache STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, STATE_PTW_READ_MISS_READ_WORD, STATE_PTW_READ_MISS_READ_WORD_DELAY, - STATE_PTW_ACCESS_AFTER_WALK, - STATE_PTW_UPDATE_TLB, + STATE_PTW_ACCESS_AFTER_WALK, + STATE_PTW_UPDATE_TLB, STATE_UNCACHED_WRITE, STATE_UNCACHED_WRITE_DONE, @@ -599,7 +601,7 @@ module dcache // now all output connect to PTW instead of CPU. CommittedM = 1'b1; // return to ready if page table walk completed. - if (~SelPTW) begin + if (~SelPTW & ~WalkerPageFaultM) begin NextState = STATE_PTW_ACCESS_AFTER_WALK; // read hit valid cached @@ -614,6 +616,12 @@ module dcache CntReset = 1'b1; DCacheStall = 1'b1; end + + // walker has issue abort back to ready + else if(~SelPTW & WalkerPageFaultM) begin + NextState = STATE_READY; + DCacheStall = 1'b0; + end end STATE_PTW_READ_MISS_FETCH_WDV: begin diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 56d0cb9cc..30971c13b 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -147,6 +147,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; logic FlushWtoDCache; + logic WalkerPageFaultM; pagetablewalker pagetablewalker( @@ -169,20 +170,20 @@ module lsu .HPTWStall(HPTWStall), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), - .HPTWReadM(HPTWReadM), + .HPTWRead(HPTWRead), .SelPTW(SelPTW), .WalkerInstrPageFaultF(WalkerInstrPageFaultF), .WalkerLoadPageFaultM(WalkerLoadPageFaultM), .WalkerStorePageFaultM(WalkerStorePageFaultM)); - + assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM; // arbiter between IEU and pagetablewalker lsuArb arbiter(.clk(clk), .reset(reset), // HPTW connection .SelPTW(SelPTW), - .HPTWReadM(HPTWReadM), + .HPTWRead(HPTWRead), .HPTWPAdrE(HPTWPAdrE), .HPTWPAdrM(HPTWPAdrM), //.HPTWReadPTE(HPTWReadPTE), @@ -338,6 +339,7 @@ module lsu .CacheableM(CacheableMtoDCache), .DTLBWriteM(DTLBWriteM), .SelPTW(SelPTW), + .WalkerPageFaultM(WalkerPageFaultM), // AHB connection .AHBPAdr(DCtoAHBPAdrM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 4feec6557..13a772435 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -31,7 +31,7 @@ module lsuArb // from page table walker input logic SelPTW, - input logic HPTWReadM, + input logic HPTWRead, input logic [`XLEN-1:0] HPTWPAdrE, input logic [`XLEN-1:0] HPTWPAdrM, // to page table walker. @@ -77,7 +77,7 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. - assign MemRWMtoDCache = SelPTW ? {HPTWReadM, 1'b0} : MemRWM; + assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index b836218c1..72abc7bae 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -117,9 +117,10 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries pmpchecker pmpchecker(.*); + // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess; - assign InstrAccessFaultF = PMAInstrAccessFaultF | PMPInstrAccessFaultF; - assign LoadAccessFaultM = PMALoadAccessFaultM | PMPLoadAccessFaultM; - assign StoreAccessFaultM = PMAStoreAccessFaultM | PMPStoreAccessFaultM; + assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); + assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); + assign StoreAccessFaultM = (PMAStoreAccessFaultM | PMPStoreAccessFaultM) & ~(Translate & ~TLBHit); endmodule diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index 8948badfa..a41f5ca0d 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -60,7 +60,7 @@ module pagetablewalker // *** modify to send to LSU output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide - output logic HPTWReadM, + output logic HPTWRead, // Faults @@ -69,7 +69,6 @@ module pagetablewalker output logic WalkerStorePageFaultM ); - logic HPTWReadE; generate if (`MEM_VIRTMEM) begin @@ -179,8 +178,10 @@ module pagetablewalker if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); + /* -----\/----- EXCLUDED -----\/----- assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; -----/\----- EXCLUDED -----/\----- */ @@ -189,7 +190,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; - HPTWReadE = 1'b0; + HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; @@ -218,7 +219,7 @@ module pagetablewalker LEVEL1_WDV: begin TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; end else begin @@ -240,7 +241,7 @@ module pagetablewalker else if (ValidPTE && ~LeafPTE) begin NextWalkerState = LEVEL0_SET_ADRE; TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; end else begin NextWalkerState = FAULT; end @@ -253,7 +254,7 @@ module pagetablewalker LEVEL0_WDV: begin TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; end else begin @@ -281,6 +282,7 @@ module pagetablewalker end FAULT: begin + SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -324,7 +326,9 @@ module pagetablewalker logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); /* -----\/----- EXCLUDED -----\/----- assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || @@ -338,7 +342,7 @@ module pagetablewalker always_comb begin PRegEn = 1'b0; TranslationPAdr = '0; - HPTWReadE = 1'b0; + HPTWRead = 1'b0; PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; @@ -369,7 +373,7 @@ module pagetablewalker LEVEL3_WDV: begin TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL3_WDV; end else begin @@ -403,7 +407,7 @@ module pagetablewalker LEVEL2_WDV: begin TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL2_WDV; end else begin @@ -437,7 +441,7 @@ module pagetablewalker LEVEL1_WDV: begin TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL1_WDV; end else begin @@ -472,7 +476,7 @@ module pagetablewalker LEVEL0_WDV: begin TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - HPTWReadE = 1'b1; + HPTWRead = 1'b1; if (HPTWStall) begin NextWalkerState = LEVEL0_WDV; end else begin @@ -502,6 +506,7 @@ module pagetablewalker end FAULT: begin + SelPTW = 1'b0; NextWalkerState = IDLE; WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; @@ -550,7 +555,7 @@ module pagetablewalker //endgenerate end else begin assign HPTWPAdrE = 0; - assign HPTWReadE = 0; + assign HPTWRead = 0; assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0; From bebc7cc5e37a4e7891a102bfabecf1efd4896853 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:34:37 -0500 Subject: [PATCH 46/47] Updated wave file. --- wally-pipelined/regression/wave.do | 385 +++++++++++++++-------------- 1 file changed, 194 insertions(+), 191 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 73b6f9fb9..33839c983 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -13,41 +13,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -182,43 +182,43 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0 -add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState -add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState -add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF -add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit -add wave -noupdate -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn -add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN -add wave -noupdate -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF +add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF +add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit +add wave -noupdate -expand -group icache -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn +add wave -noupdate -expand -group icache -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN +add wave -noupdate -expand -group icache -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM @@ -241,122 +241,122 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW -add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -expand -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead -add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM +add wave -noupdate -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty +add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -group lsu -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW +add wave -noupdate -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/EndWalk +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/PreviousWalkerState +add wave -noupdate -group lsu -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWReadPTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTableEntryM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/PageTypeM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWPAdrM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -group lsu -expand -group ptwalker -divider data +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -421,14 +421,17 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb -add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/Address add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {29656 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} +WaveRestoreCursors {{Cursor 4} {37704 ns} 0} {{Cursor 2} {28907 ns} 0} {{Cursor 3} {27874 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -444,4 +447,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {29565 ns} {29803 ns} +WaveRestoreZoom {37554 ns} {37770 ns} From 6ab7cd0f4d36012a6da853907a531db312183e1a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jul 2021 12:35:00 -0500 Subject: [PATCH 47/47] Updated the config so the tim has a bigger range. --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 44a90e1c2..56bfade59 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIM_RANGE 56'h00000FFF `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF +`define TIM_RANGE 56'h7FFFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF