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Fixed lint errors for alignment.

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This commit is contained in:
Rose Thompson 2024-02-23 14:00:19 -06:00
parent a2d5618d88
commit ab750e150f
2 changed files with 13 additions and 9 deletions
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18
src/lsu/align.sv
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@ -37,6 +37,7 @@ module align import cvw::*; #(parameter cvw_t P) (
input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage
input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM
input logic [2:0] Funct3M, // Size of memory operation input logic [2:0] Funct3M, // Size of memory operation
input logic FpLoadStoreM, // Floating point Load or Store
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [P.LLEN*2-1:0] DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed input logic [P.LLEN*2-1:0] DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
@ -69,7 +70,8 @@ module align import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] IEUAdrIncrementM; logic [P.XLEN-1:0] IEUAdrIncrementM;
logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; localparam OFFSET_LEN = $clog2(LLENINBYTES);
logic [OFFSET_LEN-1:0] AccessByteOffsetM;
logic PotentialSpillM; logic PotentialSpillM;
/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHEXPAND */
@ -89,12 +91,14 @@ module align import cvw::*; #(parameter cvw_t P) (
// compute misalignement // compute misalignement
always_comb begin always_comb begin
case (Funct3M[1:0]) case (Funct3M & {FpLoadStoreM, 2'b11})
2'b00: AccessByteOffsetM = '0; // byte access 3'b000: AccessByteOffsetM = '0; // byte access
2'b01: AccessByteOffsetM = {2'b00, IEUAdrM[0]}; // half access 3'b001: AccessByteOffsetM = {{OFFSET_LEN-1{1'b0}}, IEUAdrM[0]}; // half access
2'b10: AccessByteOffsetM = {1'b0, IEUAdrM[1:0]}; // word access 3'b010: AccessByteOffsetM = {{OFFSET_LEN-2{1'b0}}, IEUAdrM[1:0]}; // word access
2'b11: AccessByteOffsetM = IEUAdrM[2:0]; // double access 3'b011: AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access
default: AccessByteOffsetM = IEUAdrM[2:0]; 3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access
else AccessByteOffsetM = '0; // invalid
default: AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0];
endcase endcase
case (Funct3M[1:0]) case (Funct3M[1:0])
2'b00: PotentialSpillM = '0; // byte access 2'b00: PotentialSpillM = '0; // byte access

2
src/lsu/lsu.sv
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@ -164,7 +164,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
if(MISALIGN_SUPPORT) begin : ziccslm_align if(MISALIGN_SUPPORT) begin : ziccslm_align
logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM,
.MemRWM, .MemRWM,
.DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM(LSUWriteDataM[P.LLEN-1:0]), .ByteMaskSpillM, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM(LSUWriteDataM[P.LLEN-1:0]), .ByteMaskSpillM,