mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
added top-level dsru.sv (divsqrtrem unit)
This commit is contained in:
Kevin Kim
parent
a43ce92478
commit
ab4fbcdf79
@ -28,7 +28,7 @@
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`include "wally-config.vh"
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module fdivsqrt(
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module divremsqrt(
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input logic clk,
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input logic reset,
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input logic [`FMTBITS-1:0] FmtE,
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@ -28,13 +28,13 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module flags(
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module divremsqrtflags(
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input logic Xs, // X sign
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input logic [`FMTBITS-1:0] OutFmt, // output format
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input logic InfIn, // is a Inf input being used
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic XInf, YInf, // inputs are infinity
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input logic NaNIn, // is a NaN input being used
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic XSNaN, YSNaN, // inputs are signaling NaNs
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input logic XZero, YZero, // inputs are zero
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input logic [`NE+1:0] FullRe, // Re with bits to determine sign and overflow
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input logic [`NE+1:0] Me, // exponent of the normalized sum
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@ -49,7 +49,6 @@ module flags(
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output logic DivByZero, // divide by zero flag
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output logic Overflow, // overflow flag to select result
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output logic Invalid, // invalid flag to select the result
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output logic IntInvalid, // invalid integer result to select
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output logic [4:0] PostProcFlg // flags
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);
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@ -31,39 +31,23 @@
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module divremsqrtpostprocess (
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// general signals
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input logic Xs, Ys, // input signs
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input logic [`NF:0] Xm, Ym, Zm, // input mantissas
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input logic [`NF:0] Xm, Ym, // input mantissas
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input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
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input logic [2:0] OpCtrl, // choose which opperation (look below for values)
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input logic XZero, YZero, // inputs are zero
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input logic XInf, YInf, ZInf, // inputs are infinity
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input logic XNaN, YNaN, ZNaN, // inputs are NaN
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input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
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input logic XInf, YInf, // inputs are infinity
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input logic XNaN, YNaN, // inputs are NaN
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input logic XSNaN, YSNaN, // inputs are signaling NaNs
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input logic [1:0] PostProcSel, // select result to be written to fp register
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//fma signals
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input logic FmaAs, // the modified Z sign - depends on instruction
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input logic FmaPs, // the product's sign
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input logic FmaSs, // Sum sign
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input logic [`NE+1:0] FmaSe, // the sum's exponent
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input logic [3*`NF+3:0] FmaSm, // the positive sum
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input logic FmaASticky, // sticky bit that is calculated during alignment
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input logic [$clog2(3*`NF+5)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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input logic DivSticky, // divider sticky bit
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input logic [`NE+1:0] DivQe, // divsqrt exponent
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input logic [`DIVb:0] DivQm, // divsqrt significand
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// conversion signals
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input logic CvtCs, // the result's sign
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input logic [`NE:0] CvtCe, // the calculated expoent
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input logic CvtResSubnormUf, // the convert result is subnormal or underflows
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input logic [`LOGCVTLEN-1:0] CvtShiftAmt,// how much to shift by
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input logic ToInt, // is fp->int (since it's writting to the integer register)
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input logic [`CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (without msb)
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input logic IntZero, // is the integer input zero
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// final results
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output logic [`FLEN-1:0] PostProcRes,// postprocessor final result
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output logic [4:0] PostProcFlg,// postprocesser flags
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output logic [`XLEN-1:0] FCvtIntRes // the integer conversion result
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);
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// general signals
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@ -83,12 +67,6 @@ module divremsqrtpostprocess (
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logic Invalid; // invalid flag used to select results
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logic Guard, Round, Sticky; // bits needed to determine rounding
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logic [`FMTBITS-1:0] OutFmt; // output format
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// fma signals
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logic [`NE+1:0] FmaMe; // exponent of the normalized sum
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logic FmaSZero; // is the sum zero
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logic [3*`NF+5:0] FmaShiftIn; // fma shift input
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logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
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logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
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// division singals
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logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
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logic [`NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
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@ -109,7 +87,6 @@ module divremsqrtpostprocess (
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logic Signed; // is the opperation with a signed integer?
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logic IntToFp; // is the opperation an int->fp conversion?
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logic CvtOp; // convertion opperation
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logic FmaOp; // fma opperation
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logic DivOp; // divider opperation
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logic InfIn; // are any of the inputs infinity
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logic NaNIn; // are any of the inputs NaN
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@ -125,8 +102,8 @@ module divremsqrtpostprocess (
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assign Sqrt = OpCtrl[0];
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// is there an input of infinity or NaN being used
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assign InfIn = XInf|YInf|ZInf;
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assign NaNIn = XNaN|YNaN|ZNaN;
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assign InfIn = XInf|YInf;
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assign NaNIn = XNaN|YNaN;
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// choose the ouptut format depending on the opperation
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// - fp -> fp: OpCtrl contains the percision of the output
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@ -168,11 +145,10 @@ module divremsqrtpostprocess (
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// round to nearest max magnitude
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// calulate result sign used in rounding unit
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divremsqrtroundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
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divremsqrtroundsign roundsign( .DivOp, .Sqrt, .Xs, .Ys, , .Ms);
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divremsqrtround round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
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.Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt, .CvtResUf,
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.DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
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divremsqrtround round(.OutFmt, .Frm, .Plus1, .Qe,
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.Ms, .Mf, .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
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///////////////////////////////////////////////////////////////////////////////
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// Sign calculation
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@ -186,11 +162,11 @@ module divremsqrtpostprocess (
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// Flags
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///////////////////////////////////////////////////////////////////////////////
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divremsqrtflags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero,
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.Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
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.NaNIn, .FmaAs, .FmaPs, .Round, .IntInvalid, .DivByZero,
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.Guard, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
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.Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg);
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divremsqrtflags flags(.XSNaN, .YSNaN, .XInf, .YInf, .InfIn, .XZero, .YZero,
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.Xs, .Sqrt,
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.NaNIn, .Round, .DivByZero,
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.Guard, .Sticky, .UfPlus1,.DivOp, .FullRe, .Plus1,
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.Me, .Invalid, .Overflow, .PostProcFlg);
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///////////////////////////////////////////////////////////////////////////////
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// Select the result
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@ -198,9 +174,9 @@ module divremsqrtpostprocess (
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//negateintres negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
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specialcase specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid,
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.IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf,
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.NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes,
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.XInf, .YInf, .DivOp, .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
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divremsqrtspecialcase specialcase(.Xs, .Xm, .Ym, .XZero,
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.Frm, .OutFmt, .XNaN, .YNaN,
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.NaNIn, .Plus1, .Invalid, .Overflow, .InfIn,
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.XInf, .YInf, .DivOp, .DivByZero, .FullRe, .Rs, .Re, .Rf, .PostProcRes );
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endmodule
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@ -30,8 +30,8 @@
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module specialcase(
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input logic Xs, // X sign
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input logic [`NF:0] Xm, Ym, Zm, // input significand's
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input logic XNaN, YNaN, ZNaN, // are the inputs NaN
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input logic [`NF:0] Xm, Ym, // input significand's
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input logic XNaN, YNaN, // are the inputs NaN
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input logic [2:0] Frm, // rounding mode
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input logic [`FMTBITS-1:0] OutFmt, // output format
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input logic InfIn, // are any inputs infinity
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@ -53,7 +53,6 @@ module specialcase(
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logic [`FLEN-1:0] XNaNRes; // X is NaN result
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logic [`FLEN-1:0] YNaNRes; // Y is NaN result
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logic [`FLEN-1:0] ZNaNRes; // Z is NaN result
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logic [`FLEN-1:0] InvalidRes; // Invalid result result
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logic [`FLEN-1:0] UfRes; // underflowed result result
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logic [`FLEN-1:0] OfRes; // overflowed result result
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@ -73,7 +72,6 @@ module specialcase(
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if(`IEEE754) begin
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assign XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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assign YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
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assign ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
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assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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end else begin
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assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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@ -87,7 +85,6 @@ module specialcase(
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if(`IEEE754) begin
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assign XNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
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assign YNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
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assign ZNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
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assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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end else begin
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assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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@ -110,7 +107,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
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ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
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InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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end else begin
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InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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@ -124,7 +120,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
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YNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
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ZNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
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InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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end else begin
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InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
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@ -137,7 +132,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
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YNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF2]};
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ZNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF2]};
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InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
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end else begin
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InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
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@ -151,7 +145,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = (`FLEN)'(0);
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YNaNRes = (`FLEN)'(0);
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ZNaNRes = (`FLEN)'(0);
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InvalidRes = (`FLEN)'(0);
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end else begin
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InvalidRes = (`FLEN)'(0);
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@ -169,7 +162,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
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YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
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ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
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InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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end else begin
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InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
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@ -183,7 +175,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
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YNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`D_NF]};
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ZNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`D_NF]};
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InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
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end else begin
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InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
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@ -196,7 +187,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
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YNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`S_NF]};
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ZNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`S_NF]};
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InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
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end else begin
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InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
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@ -210,7 +200,6 @@ module specialcase(
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if(`IEEE754) begin
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XNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
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YNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`H_NF]};
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ZNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`H_NF]};
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InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
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end else begin
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InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
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95
src/fpu/divremsqrt/drsu.sv
Normal file
95
src/fpu/divremsqrt/drsu.sv
Normal file
@ -0,0 +1,95 @@
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///////////////////////////////////////////
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// drsu.sv
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//
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// Written: kekim@hmc.edu
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// Modified:19 May 2023
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit with postprocessing
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module drsu(
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input logic clk,
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input logic reset,
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input logic [`FMTBITS-1:0] FmtE,
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input logic XsE, YsE,
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input logic [`NF:0] XmE, YmE,
|
||||
input logic [`NE-1:0] XeE, YeE,
|
||||
input logic XInfE, YInfE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic XSNaNE, YSNaNE,
|
||||
input logic FDivStartE, IDivStartE,
|
||||
input logic StallM,
|
||||
input logic FlushE,
|
||||
input logic SqrtE, SqrtM,
|
||||
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic [2:0] Funct3E, Funct3M,
|
||||
input logic IntDivE, W64E,
|
||||
input logic [2:0] Frm,
|
||||
input logic [2:0] OpCtrl,
|
||||
input logic [`FMTBits:0] Fmt,
|
||||
input logic [1:0] PostProcSel,
|
||||
output logic FDivBusyE, IFDivStartE, FDivDoneE,
|
||||
output logic [`FLEN-1:0] FResM,
|
||||
output logic [`XLEN-1:0] FIntDivResultM,
|
||||
output logic [4:0] FlgM
|
||||
);
|
||||
|
||||
// Floating-point division and square root module, with optional integer division and remainder
|
||||
// Computes X/Y, sqrt(X), A/B, or A%B
|
||||
|
||||
logic [`DIVb+3:0] WS, WC; // Partial remainder components
|
||||
logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend)
|
||||
logic [`DIVb+3:0] D; // Iterator Divisor
|
||||
logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values
|
||||
logic [`DIVb+1:0] FirstC; // Step tracker
|
||||
logic Firstun; // Quotient selection
|
||||
logic WZeroE; // Early termination flag
|
||||
logic [`DURLEN-1:0] CyclesE; // FSM cycles
|
||||
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
|
||||
logic DivStartE; // Enable signal for flops during stall
|
||||
|
||||
// Integer div/rem signals
|
||||
logic BZeroM; // Denominator is zero
|
||||
logic IntDivM; // Integer operation
|
||||
logic [`DIVBLEN:0] nM, mM; // Shift amounts
|
||||
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
|
||||
logic [`XLEN-1:0] AM; // Original Numerator for postprocessor
|
||||
logic ISpecialCaseE; // Integer div/remainder special cases
|
||||
|
||||
divremsqrt divremsqrt(.clk, .reset, .XsE, .FmtE, .XmE, .YmE,
|
||||
.XeE, .YeE, .SqrtE, .SqrtM,
|
||||
.XInfE, .YInfE, .XZeroE, .YZeroE,
|
||||
.XNaNE, .YNaNE,
|
||||
.FDivStartE, .IDivStartE, .W64E,
|
||||
.StallM, .DivStickyM, .FDivBusyE, .QeM,
|
||||
.QmM,
|
||||
.FlushE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3M,
|
||||
.Funct3E, .IntDivE, .FIntDivResultM,
|
||||
.FDivDoneE, .IFDivStartE);
|
||||
divremsqrtpostprocess divremsqrtpostprocess(.Xs(XsE), .Ys(YsE), .Frm(Frm), .Fmt(Fmt), .OpCtrl,
|
||||
.XZero(XZeroE), .YZero(YZeroE), .XInf(XInfE), .YInf(YInfE), .XNaN(XNaNE), .YNaN(YNaNE), .XSNaN(XSNaNE),
|
||||
.YSNaN(YSNaNE), .PostProcSel,.DivSticky(DivStickyM), .DivQe(QeM), .DivQm(QmM), .PostProcRes(FResM), .PostProcFlg(FlgM));
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user