diff --git a/examples/verilog/riscvsingle/riscvsingle.sv b/examples/verilog/riscvsingle/riscvsingle.sv
index e9378e87a..85735b92a 100644
--- a/examples/verilog/riscvsingle/riscvsingle.sv
+++ b/examples/verilog/riscvsingle/riscvsingle.sv
@@ -227,8 +227,8 @@ module controller(
       7'b0000011: controls = 11'b1_00_01_0_0_0_1_0_0; // lw
       7'b0100011: controls = 11'b0_01_01_0_0_1_0_0_0; // sw
       7'b0110011: controls = 11'b1_xx_00_1_0_0_0_0_0; // R-type 
-      7'b1100011: controls = 11'b0_10_11_0_0_0_0_1_0; // beq
       7'b0010011: controls = 11'b1_00_01_1_0_0_0_0_0; // I-type ALU
+      7'b1100011: controls = 11'b0_10_11_0_0_0_0_1_0; // beq
       7'b1101111: controls = 11'b1_11_11_0_1_0_0_0_1; // jal
       default:    controls = 11'bx_xx_xx_x_x_x_x_x_x; // non-implemented instruction
     endcase
diff --git a/wallyVirtIO.patch b/linux/wallyVirtIO.patch
similarity index 100%
rename from wallyVirtIO.patch
rename to linux/wallyVirtIO.patch